KR20070004276A - Method of manufacturing array substrate - Google Patents

Abstract

A method for manufacturing an array substrate is provided to be capable of manufacturing the array substrate with three masks, by simultaneously forming a gate electrode and an active layer and forming a pixel electrode through back exposure using a thin film transistor, a data line, and a data line. A gate electrode(141) and an active layer(170) are simultaneously formed on a transparent substrate through a first mask. Source and drain electrodes(142,143) are formed on the resultant substrate through a second mask. A passivation layer(160) is formed through a third mask, wherein the passivation layer has a contact hole(165) exposing the drain electrode. A pixel electrode(150), which is electrically connected to the drain electrode through the contact hole, is formed by the gate electrode, the source electrode, and the drain electrode as a mask.

Description

Manufacturing Method of Array Substrate {METHOD OF MANUFACTURING ARRAY SUBSTRATE}

1 is a plan view of an array substrate according to the present invention.

FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

3A to 3G are cross-sectional views of a process for manufacturing the array substrate shown in FIG. 1.

<Explanation of symbols for main parts of the drawings>

100: array substrate 110: insulating substrate

120: gate line 130: data line

140: TFT 150: pixel electrode

160: shield 165: contact hole

170: active layer

The present invention relates to a method of manufacturing an array substrate, and more particularly, to a method of manufacturing an array substrate that can reduce the manufacturing cost.

In general, the liquid crystal display is a type of flat panel display and displays an image by using optical characteristics of the liquid crystal. The liquid crystal display includes a liquid crystal display panel displaying an image corresponding to image data input using light and a backlight assembly providing light to the liquid crystal display panel.

In the liquid crystal display panel, a thin film transistor (hereinafter, referred to as TFT) may include a gate electrode, an active layer formed on the gate electrode, and a source electrode and a drain electrode positioned to face each other with respect to the channel region on the active layer. It includes.

In the process of forming the liquid crystal display panel, a photolithography process using a mask is frequently used. Since the photolithography process uses an expensive mask, the manufacturing cost of the liquid crystal display panel increases as the number of masks increases. Accordingly, in the process of forming the liquid crystal display panel, a method of reducing the manufacturing cost by reducing the number of masks is emerging.

In accordance with this trend, a process of forming a liquid crystal display panel using four masks has been developed. The four-sheet mask process forms a metal layer for forming an active layer, a source electrode, and a drain electrode, and patterns the active layer in a process of forming the source electrode and the drain electrode by patterning the metal layer.

However, the four-sheet mask process does not fully satisfy the desire of consumers to reduce manufacturing costs.

Accordingly, the present invention is to solve such a problem, an object of the present invention to provide a method for manufacturing an array substrate having a structure capable of reducing the number of masks.

In order to achieve the above object of the present invention, a gate electrode and an active layer are simultaneously formed on a transparent substrate by a first mask, and a source electrode and a drain electrode are formed on the transparent substrate on which the active layer is formed by a second mask. . Next, a passivation layer having a contact hole exposing a part of the drain electrode is formed by a third mask, and a pixel electrode electrically connected to the drain electrode by using the gate electrode, the source electrode, and the drain electrode as a mask is formed. do.

Here, the present invention forms an insulating film to cover the side of the gate electrode, the contact hole is formed to expose one end of the drain electrode and a portion of the transparent substrate.

The pixel electrode forms a transparent conductive film on the entire surface of the transparent substrate on which the protective film is formed, and forms a photoresist on the transparent conductive film to provide exposure light from the rear surface of the transparent substrate to expose the photoresist. The photoresist is developed, and the transparent conductive film is developed by the developed photoresist. In this case, the photoresist is a negative photoresist.

According to the method of manufacturing the array substrate, the number of masks can be reduced by simultaneously forming the gate electrode and the active layer and forming the pixel electrode through the back exposure.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of an array substrate according to the present invention, and FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

As shown in FIG. 1 and FIG. 2, the array substrate 100 according to the present invention includes an insulating substrate 110, a gate line 120, a data line 130, and a thin film transistor (hereinafter, TFT). 140 and the pixel electrode 150. In addition, the array substrate 100 according to the present exemplary embodiment further includes an insulating layer 144, a passivation layer 160, and an active layer 170.

The insulating substrate 110 is made of a transparent material that can transmit light. For example, the insulating substrate 110 is made of glass.

The gate line 120 is formed on the insulating substrate 110 and is elongated in the first direction D1. The data line 130 is formed to extend in a second direction D2 perpendicular to the first direction D1 on the insulating substrate 110. The gate line 120 and the data line 130 are insulated from each other and cross each other. The pixel area PA is defined by the gate line 120 and the data line 130. In this case, the gate line 120 is formed on the active layer 170 and overlaps the active layer 170.

The TFT 140 is formed in the pixel area PA and includes a gate electrode 141, a source electrode 142, and a drain electrode 143. The gate electrode 141 is branched from the corresponding gate line 120, and the source electrode 142 is branched from the corresponding data line 130. In addition, the drain electrode 143 is formed to be spaced apart from the source electrode 142 and electrically connected to the pixel electrode 150.

Accordingly, the TFT 140 switches in response to the gate signal applied from the gate line 120, thereby outputting the data signal applied from the data line 130 to the pixel electrode 150.

The insulating layer 144 is formed to cover side surfaces of the gate electrode 141 and the gate line 120. At this time, the insulating film 144 is an oxide film. That is, the insulating layer 144 may include the gate electrode 141, the gate line 120, and the active substrate 170 on which the active layer 170 is formed, when the insulating substrate 110 is immersed in a diluent containing sulfuric acid or nitric acid. Side surfaces of the gate line 120 are oxidized. Meanwhile, the insulating layer 144 may be formed through plasma treatment with nitrogen gas N2 or oxygen gas O2.

The active layer 170 is formed to overlap each other on the gate electrode 141 and the gate line 120. The active layer 170 includes a semiconductor layer and an ohmic contact layer stacked on the semiconductor layer. For example, the semiconductor layer is made of amorphous silicon (a-Si), and the ohmic contact layer is made of amorphous silicon (n + a-Si) doped with a high concentration of n-type impurities. The ohmic contact layer is removed from the center portion to partially expose the semiconductor layer.

In this embodiment, the gate electrode 141, the gate line 120, and the active layer 170 are patterned by the same mask. Therefore, the active layer 170 is formed on the gate line 120.

The passivation layer 160 is formed on the insulating substrate 110 to cover the TFT 140 and the insulating layer 144. In this case, the passivation layer 160 includes a contact hole 165 for exposing a part of the drain electrode 143 and a part of the insulating substrate 110 of the TFT 140 to the outside.

The pixel electrode 150 is formed on the passivation layer 160. The pixel electrode 160 is made of a transparent conductive material through which light can pass. For example, the pixel electrode 150 is made of indium zinc oxide (IZO) or indium tin oxide (ITO). In this case, the pixel electrode 150 is electrically connected to the drain electrode 143 of the TFT 140 through the contact hole 165. In this case, the contact hole 165 is formed such that one end of the drain electrode 143 and a part of the insulating substrate 110 are exposed.

In addition, the pixel electrode 150 is patterned through back exposure using the TFT 140, the gate line 120, and the data line 130 formed under the mask.

That is, after depositing ITO or IZO on the protective layer 160, a photoresist is deposited on the ITO or IZO. The photoresist is a negative photoresist in which the exposed area is not developed. Subsequently, an exposure process of providing light for exposure from the back surface of the insulating substrate 110 is performed. Subsequently, after the development process, the ITO or IZO is etched at the portion where the exposure is not performed because it is covered by the TFT 140, the gate line 120, and the data line 130, and remains at the portion where the exposure is performed.

In this case, in the exposure process, the exposure time is relatively longer than that in the general case, and the overexposure to increase the amount of light is performed. Accordingly, the pixel electrode 150 is also patterned on one end of the drain electrode 143 that is covered by the drain electrode 143. Therefore, the pixel electrode 150 and the drain electrode 143 are electrically connected.

In the present embodiment described above, a total of three masks are used to form the array substrate. That is, one mask for forming the gate line 120, the gate electrode 141, and the active layer 170, one mask for forming the source electrode 142, and the drain electrode 143, and the contact hole 165. 1 mask is used. The pixel electrode 150 is formed by back exposure using the gate line 120, the data line 130, and the TFT 140 as a mask.

3A to 3G are cross-sectional views of a process for manufacturing the array substrate shown in FIG. 1.

As shown in FIG. 3A, the first metal film 200 is formed on the insulating substrate 110 made of glass by a sputtering method. The first metal layer 200 is made of chromium (Cr) or the like. Subsequently, a silicon film 210 is formed on the first metal film 200. The silicon film 210 includes an amorphous silicon (a-Si) film and an amorphous silicon (n + a-Si) film doped with a high concentration of n-type impurities stacked on the amorphous silicon film.

Referring to FIG. 3B, the first mask 300 having a predetermined pattern is positioned on the insulating substrate 110 on which the silicon film 220 is formed. The first mask 300 has a first opening 302 for forming the gate electrode 141 and a second opening 304 for forming the gate line 120.

The first metal layer 200 is patterned using the first mask 300 to form a gate electrode 141 and a gate line 120. In this case, the silicon layer 210 is also patterned at the same time to form the active layer 170 on the gate electrode 141 and the gate line 120.

Subsequently, the insulating substrate 110 on which the active layer 170 is formed is immersed in a diluent containing nitrogen or sulfuric acid. Accordingly, the insulating layer 144 covering the side surfaces of the gate electrode 141 and the gate line 120 is formed. On the other hand, the insulating film 144 may be formed by plasma treatment with nitrogen gas or oxygen gas.

As illustrated in FIG. 3C, the second metal film 220 is deposited on the insulating substrate 110 on which the active layer 170, the gate electrode 141, and the gate line 120 are formed.

Referring to FIG. 3D, the second mask 310 is positioned on the insulating substrate 110 on which the second metal film 220 is deposited. The second mask 310 may include a third opening 312 for forming the source electrode 142, a fourth opening 314 for forming the drain electrode 143, and a material for forming the data line 130. Five openings 316.

Next, the second metal layer 220 is patterned using the second mask 310 to form the source electrode 142, the drain electrode 143, and the data line 130. This completes the TFT 140.

As illustrated in FIG. 3E, the passivation layer 160 is deposited on the insulating substrate 110 on which the source electrode 142, the drain electrode 143, and the data line 130 are formed. Subsequently, the third mask 320 is positioned on the insulating substrate 110 on which the passivation layer 160 is formed. The third mask 320 includes a sixth opening 322 for forming the contact hole 165.

Subsequently, the passivation layer 160 is patterned using the third mask 320 to form the contact hole 165. The contact hole 165 exposes one end of the drain electrode 143 and a part of the insulating substrate 110.

Referring to FIG. 3F, a transparent conductive film 230 made of ITO or IZO is deposited on the insulating substrate 110 on which the contact hole 165 is formed to have a uniform thickness. Subsequently, a photoresist 240 having a negative characteristic in which the exposed portion is not etched is deposited on the transparent conductive film 230.

Next, as shown in FIG. 3G, exposure light for exposing the photoresist 240 is provided on the rear surface of the insulating substrate 110 on which the photoresist 240 is deposited. In this case, the overexposure that provides relatively more exposure light than the general exposure amount in the exposure process is performed.

At this time, the TFT 140, the gate line 120, and the data line 130 perform a mask function. That is, the TFT 140, the gate line 120, and the data line 130 block the exposure of the exposure light provided from the back to the photoresist 240.

Subsequently, as the development process is performed, the photoresist 240 of the portion where the exposure light is not provided is removed and patterned. The pixel electrode 150 is formed by developing the transparent conductive layer 230 using the patterned photoresist 240.

Accordingly, the pixel electrode 150 is formed in the pixel area PA defined by the gate line 120 and the data line 130. In addition, the pixel electrode 150 is formed to contact one end of the drain electrode 143 through the contact hole 165. As a result, the TFT 140 and the pixel electrode 150 are electrically connected.

As described above, the present invention simultaneously forms the gate electrode, the gate line, and the active layer. In addition, a pixel electrode is formed by back exposure using a TFT, a gate line, and a data line as a mask.

Therefore, the present invention can manufacture an array substrate using a total of three masks. Therefore, the manufacturing cost can be reduced.

In the detailed description of the present invention described above with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the invention described in the claims to be described later It will be understood that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

Claims (6)

Simultaneously forming a gate electrode and an active layer on the transparent substrate by a first mask; Forming a source electrode and a drain electrode on the transparent substrate on which the active layer is formed by a second mask; Forming a protective film having a contact hole exposing a part of the drain electrode by a third mask; And Forming a pixel electrode electrically connected to the drain electrode through the contact hole using the gate electrode, the source electrode, and the drain electrode as a mask. The method of claim 1, further comprising forming an insulating film to cover side surfaces of the gate electrode. The method of claim 1, wherein the contact hole is formed to expose a portion of the transparent substrate in contact with one end of the drain electrode and one end of the drain electrode. The method of claim 1, wherein the forming of the pixel electrode is performed. Forming a transparent conductive film on an entire surface of the transparent substrate on which the protective film is formed; Forming a photoresist on the transparent conductive film; Exposing the photoresist by providing exposure light from a rear surface of the transparent substrate; Developing the photoresist; And Developing the transparent conductive film by the developed photoresist. The method of claim 4, wherein the photoresist is a negative photoresist. The method of claim 1, Forming a gate line on the transparent substrate by the first mask; And Forming a data line crossing the gate line by the second mask; And the active layer is formed on top of the gate line so as to correspond to the gate line.

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