KR20120000432A - Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for fringe field switching mode liquid crystal display device and a method for fabricating the same are provided to reduce the capacitance of storage capacitor by forming an opening to each pixel electrode and common electrode. CONSTITUTION: A gate line is formed on a substrate on which a pixel region is formed. A data line(130) defines pixel region by crossing the gate line. A thin film transistor is electrically connected to the gate line and the data line. A pixel electrode comprises a plurality of first opening(oa1) on which rectangular shape protrusions are formed. A protective layer is formed on the pixel electrode. A common electrode(170) comprises a plurality of second opening coping with each pixel electrode.

Description

Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same}

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display device having improved aperture ratio and transmittance while reducing storage capacitor capacity.

Liquid crystal display devices (LCDs) are display devices using optical anisotropy and polarization properties of liquid crystals, and are widely used in displays of portable electronic devices, monitors of computers, and televisions.

The liquid crystal has an elongated molecular structure, which is oriented in orientation, and when placed in an electric field, the direction of molecular arrangement changes according to its size and direction. Accordingly, the liquid crystal display includes a liquid crystal panel in which a liquid crystal layer is positioned between two substrates on which electric field generating electrodes are formed, and artificially adjusts an arrangement direction of liquid crystal molecules through a change in an electric field generated between the two electrodes. Various images are displayed by changing the light transmittance accordingly.

In general, a liquid crystal display device includes an array substrate on which a plurality of wirings, switching elements, and pixel electrodes are formed, and a color filter substrate on which a color filter and a common electrode are formed, and the liquid crystal molecules between the two substrates are disposed between the pixel electrode and the common electrode. It is driven by an induced electric field, a vertical electric field in a direction perpendicular to the substrate.

However, the method of driving the liquid crystal by the vertical electric field has a problem that the viewing angle characteristics are not excellent.

To overcome this problem, a transverse electric field type liquid crystal display device has been proposed. In a transverse electric field type liquid crystal display, pixel electrodes and a common electrode are alternately formed on the same substrate, so that a horizontal electric field in a direction parallel to the substrate is induced between the two electrodes. Therefore, the liquid crystal molecules are driven by a horizontal electric field and move in a direction parallel to the substrate, and such a transverse electric field type liquid crystal display device has an improved viewing angle.

However, such a transverse electric field type liquid crystal display device has a low aperture ratio and low transmittance.

Therefore, in order to improve the disadvantage of the transverse electric field type liquid crystal display, a fringe field switching mode LCD for driving a liquid crystal by a fringe field has been proposed.

1 is a plan view of one pixel area in a conventional fringe field switching mode liquid crystal display array substrate.

As shown in the drawing, the gate wiring 43 is formed along one direction, and the data wiring 51 defining the pixel region is formed to cross the gate wiring 43.

A thin film transistor Tr connected to the gate line 43 and the data line 51 is formed in the pixel area, and the thin film transistor Tr includes the gate electrode 45, the active layer 46a, and the ohmic contact layer ( And a source electrode 55 and a drain electrode 58 formed of a semiconductor layer 46 formed of 46b).

In addition, the pixel electrode 60 is formed in each pixel region in contact with one end of the drain electrode 58 of the thin film transistor Tr. In this case, the pixel electrode 60 has a rectangular plate shape substantially corresponding to the entire pixel area.

The common electrode 75 is formed by overlapping the pixel electrode 60 with a protective layer (not shown). In this case, the common electrode 75 has a plurality of openings oa in the pixel area P. Have The common electrode 75 extends to the adjacent pixel area P to correspond to the entire surface of the display area including the plurality of pixel areas P. In FIG. Each of the openings oa of the common electrode 75 has a bar shape parallel to the data line 51.

FIG. 2 is a cross-sectional view of one pixel area of a conventional array substrate for fringe field switching mode liquid crystal display devices having the planar configuration. FIG. 2 is a cross-sectional view of a portion cut along the cutting line II-II of FIG. 1.

As shown, a gate electrode 45 and a gate wiring (not shown) are formed on the substrate 10, and a gate insulating film 30 covers the gate electrode 45 and the gate wiring (not shown). . An active layer 46a is formed on the gate insulating layer 30 to correspond to the gate electrode 45, and an ohmic contact layer 46b is spaced apart from each other on the active layer 46a.

In addition, source and drain electrodes 55 and 58 are spaced apart from each other on the ohmic contact layer 46b.

In addition, a pixel area P is defined and a data line 51 is formed on the gate insulating layer 30 to intersect the gate line (not shown), and the pixel is in contact with one end of the drain electrode 58. An electrode 60 is formed, and at this time, the pixel electrode 60 is formed corresponding to each pixel region P. As shown in FIG.

The passivation layer 70 is formed on the pixel electrode 60, and the common electrode 75 is formed on the entire display area. In this case, the common electrode 75 has a plurality of openings (ops) corresponding to the pixel electrode 60, and the common electrode 75 and the pixel electrode 60 overlapping each other are storage capacitors. ).

In the fringe field switching mode liquid crystal display including the array substrate 10 having the above-described structure, when a voltage is applied to the pixel electrode 60 and the common electrode 75, the pixel electrode 60 is common to the overlapping pixel electrode 60. A fringe field is formed between the electrodes 75. Therefore, even the liquid crystal molecules positioned on the electrodes are all operated, thereby improving the transmittance and aperture ratio compared to the transverse electric field type liquid crystal display device.

However, in the fringe field switching mode liquid crystal display device, since the storage capacitor formed between the pixel electrode 60 and the common electrode 75 is formed over the entire pixel region P, it is three times as large as that of the transverse field type liquid crystal display device. To have a capacity about five times as large.

If the capacity of the storage capacitor is too large, it is difficult to charge in high resolution models with short charge times or high frequency models.

To improve this, it is necessary to increase the line width of the gate line (43 in FIG. 1) or the data line 51 to reduce the resistance, or to increase the channel width of the thin film transistor Tr. However, when the area of the thin film transistor Tr is increased by increasing the line width of the gate wiring (43 in FIG. 1) and the data wiring 51 or increasing the panel width, the problem of reducing the transmittance and the luminance is reduced. Occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and reduces the capacity of the storage capacitor in each pixel region compared to the conventional fringe field switching mode liquid crystal display array substrate, thereby improving charging characteristics and further improving aperture ratio and transmittance. It is a first object of the present invention to provide an array substrate for a fringe field switching mode liquid crystal display device.

In addition, due to the characteristics of the array substrate for the fringe field switching mode liquid crystal display, pixel and common electrodes overlapping each other are formed in different layers, thereby minimizing fluctuations in transmittance and storage capacitors in the case of process errors, especially in the case of overlay shift. It is a second object of the present invention to provide an array substrate for a fringe field switched mode liquid crystal display device.

In order to achieve the above object, an array substrate for a fringe field switching mode liquid crystal display device according to the present invention comprises: a gate wiring extending in one direction on a substrate on which a pixel region is defined; A data line formed to cross the gate line and define the pixel area; A thin film transistor electrically connected to the gate line and the data line; A pixel electrode formed in contact with the drain electrode of the thin film transistor, the pixel electrode having a plurality of first openings each having a recessed portion and a convex portion having a quadrangular shape in a planar side thereof; A protective layer formed on the pixel electrode; A common electrode formed on the passivation layer, the common electrode having a plurality of second openings spaced apart from each other in correspondence with the pixel electrodes, wherein each of the plurality of second openings overlaps a side surface of the first opening; It is characterized by being arranged.

In this case, the recessed portions and the convex portions respectively provided on both side surfaces of the first opening have the same size and the same area.

In addition, the recessed portion and the convex portion provided in the first opening is characterized in that the recessed portion and the convex portion is configured to correspond to each of the opposite sides facing each other, wherein the width of the second opening of the depth of the recessed portion provided in the first opening 0.8 times to 1.2 times, and the width of the common electrode finger formed in the separation area between the second opening is characterized in that 0.8 to 1.2 times the width of the second opening. In addition, the depth of the recess is characterized in that 0.5 to 1.5 times the separation interval between the iron portion and the iron portion provided on both sides in the first opening.

In addition, a gate insulating film is formed between the gate wiring and the data wiring, and the pixel electrode is formed on the gate insulating film.

In addition, the pixel electrode and the common electrode are made of a transparent conductive material, and the pixel electrode and the common electrode overlapping each other with the protective layer interposed in the pixel area constitute a storage capacitor.

In addition, the pixel electrode and the plurality of first and second openings may be symmetrically bent in a central portion of the pixel area with respect to an imaginary line parallel to the gate wiring. The central portion of the pixel region may have a structure symmetrically bent with respect to an imaginary line parallel to the gate line.

The present invention provides an array substrate for a fringe field switching mode liquid crystal display device, wherein openings are formed in the pixel electrode and the common electrode, respectively, to reduce the capacitance of the storage capacitor formed between the two electrodes. Therefore, the charging characteristic can be improved, and the aperture ratio can be improved by reducing the width of the gate and data lines and the size of the thin film transistor.

Further, the openings provided in the pixel region are formed in such a shape that the convex portions formed on the other side thereof are exactly coincident with the portions formed on one side thereof, such as a lego block, and the depth of the recess portion and the width of the convex portions are the common electrode. The capacitance of the storage capacitor can be reduced by reducing the overlapping area of the pixel electrode and the common electrode in each pixel area by forming a level similar to the width of the opening provided in the opening. Therefore, the filling characteristic can be improved, and at the same time, the aperture ratio and the transmittance can be improved.

In addition, a first opening is formed on both sides of the recess formed on one side of the pixel electrode, and the convex and convex portions of the concave portion formed on the other side thereof are formed, and a second opening in the form of a bar is formed inside the common electrode. Is formed to minimize the overlap area variation and transmittance variation caused by the overlay shift of the common electrode and the pixel electrode overlapping each other, and can cope with the enlargement of the liquid crystal display device.

1 is a plan view of one pixel region in a conventional fringe field switching mode liquid crystal display array substrate.
FIG. 2 is a cross-sectional view of a portion taken along cut line II-II of FIG. 1. FIG.
3 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention.
4 is a cross-sectional view of a portion cut along the cutting line IV-IV of FIG.
5A and 5B are diagrams illustrating overlay shifts occurring due to a process error in forming a common electrode or a pixel electrode in an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention, respectively. 5A is a view showing that an overlay shift has occurred to the left.

Hereinafter, an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view of one pixel area of an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 4 is a cross-sectional view of a portion taken along the cutting line IV-IV of FIG. 3. . In this case, in FIG. 3, since the second common electrode is formed on the entire surface of the substrate, the second common electrode is not shown in plan view, but is indicated by a dotted line 170 at the boundary of each pixel region for convenience of description. In addition, in each pixel area, the first opening formed in the pixel electrode is shown by a solid line, and the second opening formed in the common electrode is shown by a dotted line.

 First, referring to FIG. 3, as shown in the drawing, a plurality of gate lines 107 are formed to be spaced apart from each other by a predetermined interval, and a plurality of gate lines 107 and a gate insulating film (not shown) are formed therebetween. A plurality of pixel regions P are defined to cross each other, and a plurality of data lines 130 are formed.

Each pixel area P is connected to the gate line 107 and the data line 130, and a thin film transistor Tr is formed. The thin film transistor Tr is sequentially stacked to form a gate electrode 108, a gate insulating film (not shown), an active layer (not shown) of pure amorphous silicon, and an ohmic contact layer (not shown) of impurity amorphous silicon. A semiconductor layer (not shown) and source and drain electrodes 133 and 136 spaced apart from each other.

In the drawing, although the thin film transistor Tr has a U-shaped channel as an example, the channel shape of the thin film transistor Tr depends on the structure of the source and drain electrodes 133 and 136. It can be variously modified. In addition, although the gate electrode 108 of the thin film transistor Tr is formed as part of the gate wiring 107 itself, the gate electrode 108 is formed in the pixel region P in the gate wiring 107. It may be formed by branching inside.

Next, as the most characteristic configuration of the present invention, each pixel region P is made of a transparent conductive material, and contacts the drain electrode 136 of the thin film transistor Tr, and one side thereof is a recess 143a. And a convex portion 143b, and the other side thereof is a form in which the concave portion 143b and the concave portion 143a are provided to correspond to the concave portion 143a and the convex portion 143b on the other side as if they are exactly matched with each other like a Lego block. A pixel electrode 170 having a plurality of first openings o a1 is formed.

In more detail with respect to the planar shape of the first opening (oa1), each of the first opening (oa1) has a width and the width so that the recessed portion (143a) and the convex portion (143b) on both sides of the first opening (oa1) is completely matched like a lego block. It is characterized by having the same size of depth, and the recessed portion 143a is disposed on one side thereof on both sides corresponding to each other, and the convex portion 143b is disposed on the other side thereof.

At this time, the depth of the recessed portion 143a and the width a of the convex portion 143b corresponding to the recessed portion 143a are the convex portions 143b and the convex portions 143b provided at both sides thereof in the first opening oa1. It is characterized in that it is about 0.5 to 1.5 times the spacing interval (b) between.

Meanwhile, the plurality of first openings oA1 are formed in the pixel electrode 155 in order to reduce the capacitance of the storage capacitor included in each pixel area P. Furthermore, the plurality of first openings oA1 are formed. ) Is formed so that both ends thereof form a straight bar, and the recessed portion 143a and the convex portion 143b are formed so that the storage capacitor capacity is reduced even when an overlay shift occurs due to manufacturing process error. This is to reduce the change in transmittance by minimizing the change. The change in the storage capacitor capacity caused by the overlay shift will be described later.

Next, as described above, the side end thereof overlaps the pixel electrode 155 having the plurality of second openings oa2 including the plurality of recesses 143a and the convex portions 143b and a protective layer (not shown). The common electrode 170 is formed over the entire display area. In this case, the common electrode 170 has a plurality of second openings oA2 having a bar shape in which a side end thereof forms a straight line corresponding to each pixel area P.

The plurality of second openings oa2 are formed to overlap the plurality of first openings oa1 provided in the pixel area P and the pixel electrodes 155 adjacent thereto, and each of the second openings oa2 is formed. The bar-shaped common electrode 170 located between the fingers is disposed to overlap the recessed portions 143a and the convex portions 143b provided at both ends of the second opening oa2.

That is, referring to the drawings, the pixel electrode 155 has two first openings oA1 formed therein, so that a total of four side ends of the first openings oA1 can be obtained. In this case, each pixel area ( A total of four second openings oa2 are formed in the common electrode 170 corresponding to P, and each of these second openings oa2 is formed to overlap each side end of each of the first openings oa1. In addition, the common electrode 170 fingers positioned between the second openings oa2 may also be formed such that one side or the other side thereof overlaps the recessed portions 143a or the convex portions 143b at both ends of the second opening oa2. It is characterized by being.

In this case, the width c of the second opening oa2 is the depth a of the recess 143a provided in the first opening oa1 or the width of the convex portion 143b corresponding to the recess 143a. It is preferable to have a 0.8 to 1.2 times of a), the width (d) of the common electrode 170 fingers formed in the separation area between the second opening (oa2) is the width (c) of the second opening (oa2) It is characterized in that it is formed so that about 0.8 to 1.2 times of.

As described above, the width c of the second opening oa2 is formed to be 0.8 to 1.2 times the depth a of the recess 143a or the width a of the convex portion 143b. This is to optimize the storage capacitor capacity variation when an overlay shift occurs. When the width c of the second opening oa2 is greater than 1.2 times the depth a of the recess 143a or the width a of the convex portion 143b, the second opening oa2 is defined as the second opening oa2. It is difficult to dispose to correspond to the side of the first opening (oa1), and furthermore the width (d) of the finger of the common electrode 170 having a bar shape (bar) located between the first opening (oa1) is reduced to a proper This is to prevent this because it may be a problem in fringe field formation.

The pixel electrode 155 and the second common electrode 170 overlapping each other form a storage capacitor together with a protective layer (not shown) interposed between the two electrodes 155 and 170.

 The array substrate 101 for the fringe field switching mode liquid crystal display according to the exemplary embodiment of the present invention having the above-described configuration may include a plurality of bar-shaped first openings oA1 provided in the common electrode 170. And the pixel electrode 155 and the common electrode 170 both form a straight bar shape or a rectangular shape.

However, although not shown in the drawings as a modified example, the plurality of second openings oA2 and the common electrode 170 having both of the concave-convex structures at both sides of the pixel electrode 155 and the pixel electrode 155 are provided. A plurality of bar-shaped second openings oA2 provided therein are symmetrical with respect to an imaginary line parallel to the gate line 107 of FIG. 3 crossing the central portion of each pixel area P. Referring to FIG. It can also be structured as In this case, the data line 130 may also be symmetrically bent with respect to the central portion of each pixel area P, thereby forming a zigzag shape for the entire display area.

In this way, a plurality of bar-shaped second openings oA2, a pixel electrode 155, and a plurality of first openings oA1 provided in the common electrode 170 are formed at the center of each pixel area P. FIG. By having a configuration symmetrically bent as a reference, a double domain is formed in each pixel region P, and an array substrate having such a configuration has an effect of suppressing color shift due to azimuth change of the liquid crystal display device. .

Hereinafter, the vertical structure of the array substrate for the fringe field switching mode liquid crystal display according to the present invention will be described with reference to FIG. 4.

First, in the fringe field switching mode liquid crystal display array substrate 101 according to the present invention, a gate wiring (not shown) extending in one direction is formed on a transparent substrate 101 serving as a base. A gate electrode 108 connected to the gate) is formed. At this time, in the exemplary embodiment of the present invention, the gate electrode 108 may be formed as part of the gate line itself (not shown) to improve the aperture ratio. However, the gate electrode 108 may be the gate line (not shown). ) May be formed inside the pixel region P in a branched manner.

On the other hand, the gate wiring (not shown) and the gate electrode 108 is a metal material having low resistance characteristics, for example, aluminum alloys such as aluminum (Al), aluminum-nedium (AlNd), copper (Cu), copper The alloy is made of one selected from the group consisting of molybdenum alloys such as chromium (Cr), molybdenum (Mo), and molybdenum (MoTi) to have a single layer structure or a multilayer structure made of two or more materials.

In the drawings, the gate wiring (not shown) and the gate electrode 108 are formed of a single metal material to form a single layer structure as an example.

Next, a gate insulating film 115 made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is disposed on the entire surface of the substrate 101 over the gate wiring and the gate electrode 108. Formed.

A semiconductor layer 120 formed of an active layer 120a of pure amorphous silicon and an impurity amorphous silicon and spaced apart from each other is formed on the gate insulating layer 115 to correspond to the gate electrode 108. It is.

In addition, source and drain electrodes 133 and 136 spaced apart from each other to expose a central portion of the active layer 120a are formed on the ohmic contact layer 120b which is more accurately spaced apart from each other above the semiconductor layer 120. have. In this case, the gate electrode 108, the gate insulating layer 115, and the source and drain electrodes 133 and 136 spaced apart from each other and sequentially stacked on the boundary of each pixel region P are thin films that are switching elements. A transistor Tr is formed.

In addition, a data line 130 is formed on the gate insulating layer 115 to cross the gate line (not shown) to define the pixel area P. In this case, the data line 130 is connected to the source electrode 133 of the thin film transistor Tr.

The data line 130 and the source and drain electrodes 133 and 136 may be formed of aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum alloy (Moti), and chromium (Cr). It can be made of a single layer structure or a multi-layer structure by consisting of any one or two or more of the materials. In the drawing, the data line 130 and the source and drain electrodes 133 and 136 have a single layer structure.

Meanwhile, in the drawing, the data line 130 and the gate insulating layer 115 have the same planar shape as that of the data line 130 and are completely overlapped to form the active layer 120a and the ohmic contact layer 120b. Although the semiconductor dummy pattern 121 including the first and second patterns 121a and 121b made of the same material is shown as an example, the semiconductor dummy pattern 121 is due to a manufacturing method. May be omitted.

Next, inside the pixel region P, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the gate insulating layer 115 as a characteristic feature of the present invention. And a pixel electrode 155 having a plurality of first openings oa1 formed at a side thereof having a recessed portion 143a and a convex portion 143b having a rectangular shape. At this time, each of the first opening (oa1) is a width (a) or recess (143a) of the convex portion (143b) so that the recessed portion (143a) and the convex portion (143b) corresponding to each other on both sides of the first opening (oa1) is completely matched like a lego block. Depth (a) is characterized by having the same size, there is a side portion corresponding to each other is characterized in that the recessed portion (143a) is disposed on one side and the corresponding side surface is arranged convex portion (143b).

Next, the pixel electrode 155, the pixel connection pattern 156, the common electrode 170, the thin film transistor Tr, and the data wire 130 are placed over an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride. A protective layer 160 made of (SiNx) or made of an organic insulating material such as benzocyclobutene (BCB) or photo acryl is formed on the entire display area.

Next, a common electrode 170 made of a transparent conductive material, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), is formed over the passivation layer 160 in the entire display area. In this case, the common electrode 170 has a plurality of second openings oA2 having a straight bar shape corresponding to the pixel electrode 155 and spaced apart from each other.

In this case, the second opening oa2 is disposed to overlap the recessed portion 143a or the convex portion 143b formed at both ends of the first opening oa1, and is disposed between the second opening oa2. The finger of 170 is also characterized in that any one of both side ends thereof is arranged to overlap the recessed portion 143a or the convex portion 143b of the first opening oa1.

Hereinafter, with reference to the drawings, the reason why the variation of the capacitance and transmittance of the storage capacitor is prevented when an overlay shift occurs due to a process error in the array substrate for the fringe field switching mode liquid crystal display according to the present invention. Explain.

5A and 5B illustrate an overlay shift due to a process error in forming a common electrode 170 or a pixel electrode 155 in an array substrate for a fringe field switching mode liquid crystal display according to an exemplary embodiment of the present invention. 5A shows that an overlay shift has occurred to the left side, and FIG. 5B shows that an overlay shift has occurred to the right side. At this time, for convenience, only the pixel electrode 155 and the common electrode 170 overlapping each other are illustrated, and the second opening oa2 provided in the common electrode 170 displays the normal design value in a solid line and overlay shifts. The shift is generated and the position shift is shown by the dotted line.

First, referring to FIG. 5A, even when the common electrode 170 is formed by shifting a predetermined interval to the left side due to a process error to the left, a change in the overlapping area between the common electrode 170 and the pixel electrode 155 occurs almost. It can be seen that.

That is, the recesses 143a and the convex portions 143b are provided at both sides of each of the first openings oa1, respectively, so that the second openings oa2 are shifted to the left, but on one side of the first openings oa1. The overlapped area with the concave portion 143a is reduced while the overlapped area with the convex portion 143b is increased, while the overlapped area with the concave portion 143a is increased while the overlapped area with the concave portion 143b is reduced. have.

Therefore, even if an overlay shift occurs, it can be seen that substantially no variation in the overlapping area between the first opening oa1 and the second opening oa2 occurs. As a result, even when an overlay shift occurs, the transmittance in each pixel area P is almost unchanged.

The change in the overlapping area between the first opening oa1 provided in the pixel electrode 155 and the second opening oa2 provided in the common electrode 170 does not occur due to an overlay shift. And the overlapping area between the pixel electrode 155 and the common electrode 170 except for the second openings oa1 and oa2 is also unchanged, so that the storage in each pixel area P is substantially changed by an overlay shift. It can be seen that no change in capacitor capacity occurs.

Meanwhile, referring to FIG. 5B, even when the common electrode 170 is shifted to the right by a predetermined distance due to a process error, the recessed portions 143a and the convex portions 143b provided on both sides of the first opening oa1 are formed. It can be seen that the change in the overlapped area between the common electrode 170 and the pixel electrode 155 hardly occurs, and thus the change in the storage capacitor capacity and transmittance hardly occurs.

The present invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

101: array substrate 107: gate wiring
108: gate electrode 120: semiconductor layer
130: data wiring 133: source electrode
136: drain electrode 143a: main portion (of the first opening)
143b: convex portion (of first opening) 155: pixel electrode
170: common electrode oa1: first opening
oa2: second opening P: pixel region
Tr: Thin Film Transistor

Claims (11)

A gate wiring formed in one direction on the substrate on which the pixel region is defined;
A data line formed to cross the gate line and define the pixel area;
A thin film transistor electrically connected to the gate line and the data line;
A pixel electrode formed in contact with the drain electrode of the thin film transistor, the pixel electrode having a plurality of first openings each having a recessed portion and a convex portion of a quadrangular shape in planar direction;
A protective layer formed on the pixel electrode;
A common electrode formed on the passivation layer and having a plurality of second openings spaced apart from each other in correspondence with the pixel electrodes;
Wherein each of the plurality of second openings is disposed to overlap a side surface of the first opening.
The method of claim 1,
The recessed portion and the convex portion provided on both sides of the first opening, respectively, have the same size and the same area, the array substrate for fringe field switching mode liquid crystal display device.
The method of claim 2,
The recessed portion and the convex portion provided in the first opening are configured such that the recessed portion and the convex portion correspond to both side surfaces facing each other, respectively.
The method of claim 3, wherein
The width of the second opening is 0.8 to 1.2 times the depth of the recessed portion provided in the first opening array substrate for a fringe field switching mode liquid crystal display device.
The method of claim 4, wherein
And a width of the common electrode finger formed in the separation area between the second openings is 0.8 to 1.2 times the width of the second opening.
The method of claim 5, wherein
And the depth of the recess is 0.5 to 1.5 times the separation distance between the convex portion and the convex portion provided at both sides of the first opening.
The method of claim 1,
A gate insulating film is formed between the gate wiring and the data wiring, and the pixel electrode is formed on the gate insulating film.
The method of claim 1,
And the pixel electrode and the common electrode are made of a transparent conductive material.
The method of claim 1,
And the pixel electrode and the common electrode overlapping each other with the protective layer interposed therebetween in the pixel region, forming a storage capacitor.
The method of claim 1,
The pixel electrode and the plurality of first openings and the second openings are symmetrically bent in a center portion of the pixel area with respect to an imaginary line parallel to the gate line. Board.
The method of claim 10,
And the data line has a structure symmetrically bent at a central portion of the pixel region with respect to a virtual line parallel to the gate line.

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