KR20110134597A - Method of identifying location of wafer and method of separating semiconductor chip using the same - Google Patents

Method of identifying location of wafer and method of separating semiconductor chip using the same Download PDF

Info

Publication number
KR20110134597A
KR20110134597A KR1020100054241A KR20100054241A KR20110134597A KR 20110134597 A KR20110134597 A KR 20110134597A KR 1020100054241 A KR1020100054241 A KR 1020100054241A KR 20100054241 A KR20100054241 A KR 20100054241A KR 20110134597 A KR20110134597 A KR 20110134597A
Authority
KR
South Korea
Prior art keywords
wafer
mirror
die
mirror die
stage
Prior art date
Application number
KR1020100054241A
Other languages
Korean (ko)
Inventor
김창진
Original Assignee
세크론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세크론 주식회사 filed Critical 세크론 주식회사
Priority to KR1020100054241A priority Critical patent/KR20110134597A/en
Publication of KR20110134597A publication Critical patent/KR20110134597A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE: A method for checking the location of a wafer and a semiconductor chip separating method using the same are provided to use a mirror die when a worker aligns manuals, thereby aligning manuals even on a rework wafer. CONSTITUTION: Wafers are aligned on a stage where a wafer is fixed(S210). The location of a wafer is aligned around a preset confirmation spot of the wafer(S220). The location of the aligned wafer is compared with a photographing image of a mirror die(S230). A first mirror die is photographed to obtain a photographing image for the first mirror die.

Description

METHODS OF IDENTIFYING LOCATION OF WAFER AND METHOD OF SEPARATING SEMICONDUCTOR CHIP USING THE SAME

The present invention relates to a method for locating a wafer and a method for separating a semiconductor chip using the same, and more particularly, to a method for locating a wafer for preventing map rolling and a method for separating a semiconductor chip using the same.

In general, in the manufacturing process of a semiconductor device, a plurality of semiconductor chips as unit devices are formed by a series of semiconductor manufacturing processes on a silicon wafer used as a semiconductor wafer.

Such semiconductor chips are individually cut through a sawing process in a state where they are adhered to an adhesive sheet to facilitate cutting of the semiconductor wafer. Thereafter, the cut semiconductor chips are supplied to the die bonding process, and the individual semiconductor chips are separated from the semiconductor wafer in the die bonding process and mounted on the lead frame or the substrate. At this time, a chip separating apparatus for separating the semiconductor chips individually is used.

The conventional semiconductor chip separating apparatus includes a stage for supporting a wafer having a plurality of sawing completed semiconductor chips, a holder for holding an adhesive sheet attached to the lower surface of the wafer, and a picker for picking the semiconductor chips. It is required to mount the wafer in the correct position on the stage. Therefore, it is necessary to confirm the position of the wafer seated on the stage.

1A is a flowchart for briefly explaining a conventional wafer positioning method. FIG. 1B is a flowchart for briefly explaining a manual alignment operation of an operator in the wafer positioning method of FIG. 1A.

According to FIGS. 1A and 1B, the conventional wafer positioning method includes the steps of aligning the wafer to a normal position on a stage on which the wafer is located (S110) and in the case where the wafer alignment step fails, an operator ( manual) to align the position of the wafer (S120).

Aligning the wafer to a normal position includes matching the center of the wafer and the stage and confirming whether or not the arrangement information of each die is matched based on previously input map data of the wafer.

In the step S120 of the operator manually aligning the position of the wafer, the step of moving the stage to a predetermined specific die position (S121), comparing an image of the specific die and an image of the specific die inputted in advance Step S122 and step S123 and the operator manually adjusts the position of the wafer (S124).

After the manual adjustment step, the pickup operation of the semiconductor chip is performed.

However, as the operator performs the wafer alignment process manually as described above, the wafer phenomena, i.e., the map slid, due to erroneous information or mistakes have occurred.

Therefore, the technical problem of the present invention has been conceived in this respect, the object of the present invention is to provide a method for locating a wafer for preventing map rolling.

Another object of the present invention is to provide a semiconductor chip separation method using the wafer positioning method.

In the wafer positioning method according to an embodiment for achieving the above object of the present invention, the wafer is aligned on the stage for fixing the wafer, the position of the wafer around the predetermined confirmation point of the wafer Is manually aligned, and then the alignment position of the wafer is reconfirmed by comparing the image of the mirror die with the reference image of the position of the manually aligned wafer.

In one embodiment of the present invention, the mirror die may be a die formed in the periphery of the wafer and no circuit is formed.

In one embodiment of the invention, the step of manually aligning the position of the wafer, comparing the captured image of the mirror die of the wafer with the reference image of the mirror die when the wafer is in position, and It may be performed by manually adjusting the stage such that the captured image and the reference image overlap.

In one embodiment of the present invention, the step of reconfirming the alignment position of the wafer may include imaging the mirror die of the wafer and comparing the photographed image with a reference image of the mirror die when the wafer is in position. This can be done by.

In one embodiment of the present invention, the mirror die includes first, second, third and fourth mirror dies, and the second to fourth mirror dies are in the clockwise direction from the first mirror die. At the periphery of the four squares forming a vertex may be formed sequentially.

In one embodiment of the present invention, in the step of double-checking the alignment position of the wafer, if the at least two or more mirror dies of the four mirror dies coincide with the reference image, the alignment position of the wafer is double-checked. The step of ending may be completed.

In the semiconductor chip separation method according to the present invention for achieving the object of the present invention, the wafer is aligned on the stage for fixing the wafer, the position of the wafer around the predetermined confirmation point of the wafer Sort by manual. Subsequently, the position of the manually aligned wafer is compared with a captured image of a mirror die and a reference image to confirm the alignment position of the wafer, and after the step of re-checking the alignment position of the wafer, Semiconductor chips are separated from the wafer.

According to the present invention described above, in the manual alignment operation of the operator, by using a mirror die as a designated die, mistakes due to confusion with surrounding adjacent dies can be avoided, and even manual rework wafers can be used. You can proceed with the alignment.

In addition, after the manual adjustment operation, the operation of confirming the position of the mirror die may be performed to prevent a map slippage due to an operator mistake.

1A is a flowchart for briefly explaining a conventional wafer positioning method.
FIG. 1B is a flowchart for briefly explaining a step of a manual alignment operation of an operator in the wafer positioning method of FIG. 1A.
2A is a flowchart illustrating a wafer positioning method according to an embodiment of the present invention.
FIG. 2B is a flowchart for explaining a step of a manual alignment operation of an operator in the wafer positioning method of FIG. 2A.
FIG. 2C is a flowchart for explaining a validity checking step of a manual alignment operation of an operator in the wafer positioning method of FIG. 2A.
3 is a plan view for explaining a wafer on which a mirror die is formed.
4 is a flowchart illustrating a method of separating a semiconductor chip according to another embodiment of the present invention.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are shown in an enlarged scale than actual for clarity of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Singular expressions include plural expressions unless the context clearly indicates otherwise.

In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to the accompanying drawings.

2A is a flowchart illustrating a wafer positioning method according to an embodiment of the present invention. FIG. 2B is a flowchart for explaining a step of a manual alignment operation of an operator in the wafer positioning method of FIG. 2A. FIG. 2C is a flowchart for explaining a validity checking step of a manual alignment operation of an operator in the wafer positioning method of FIG. 2A. 3 is a plan view for explaining a wafer on which a mirror die is formed.

In the wafer positioning method according to the present embodiment, the operation steps up to the manual alignment operation step of the operator are the same as the conventional operation steps described with reference to FIGS. 1A and 1B, and thus redundant descriptions thereof will be omitted.

Referring to FIGS. 2A to 3, when aligning the normal position of the wafer (S210) is normal, positioning of the wafer is completed. On the contrary, when the step S210 of aligning the normal position of the wafer is abnormal, the stage is moved to position the camera on the first mirror die 11 that is previously specified (S221). In the die formed on the periphery of the wafer, the outer edge portion becomes an arc shape, and a predetermined die outline shape is not obtained. Thus, a wafer without a circuit is used on a die at the periphery of the wafer. Thus, a die without a circuit is generally called a mirror die. The movement of the stage, for example, a driver (not shown) for driving the stage moves the stage on which the wafer is seated to position the camera on the first mirror die 11. The movement amount of the stage may be calculated using location information on the first mirror die stored in pre-entered map data.

The captured image of the first mirror die 11 is obtained to acquire a captured image of the first mirror die (S222). The captured image may represent an image of the first mirror die or an arrangement form with another die adjacent to the first mirror die.

The operator compares the captured image obtained in the step and the reference image obtained when the wafer is aligned at the correct position (S223). The operator adjusts the position of the stage such that the captured image and the reference image completely overlap each other (S224). When the operator determines that the captured image and the reference image overlap each other, the manual adjustment operation is terminated and the subsequent operation described below is performed.

The mirror die selected above is not limited to the first mirror die 11, and may select one or more of the other mirror dies 12, 13, 14 on the wafer. In addition, it is obvious that the mirror die may utilize a peripheral wafer in which a circuit is not formed in addition to the illustrated mirror dies 11, 12, 13, and 14.

When the operator adjusts the manual, the information on the mirror die can be used to avoid confusion with neighboring adjacent dies, and can also be applied to rework wafers.

When the manual alignment operation step of the worker is completed, the validity checking step (S230) of the manual alignment operation for reconfirming the alignment position of the wafer is started. The validity checking step (S230) of the manual sorting operation is not a manual operation, and is a process that is automatically calculated by using information of pre-entered map data. The camera is positioned again on the first mirror die 11 (S231). The camera is positioned on the first mirror die by moving the stage, and the movement amount of the stage may be calculated using location information stored in pre-entered map data.

The first mirror die 11 is photographed to obtain a captured image of the first mirror die (S232). In operation S233, it is determined whether the captured image secured in the above step is compared with the reference image of the mirror die obtained from the position information stored in the input map data. When the captured image coincides with the mirror die of the input map data, the camera is positioned on the second mirror die 12.

The same operation as that of determining whether the first mirror die is matched with the second mirror die 12 is also performed.

This operation is repeated by comparing and examining a plurality of mirror dies, that is, n (n is a natural number) mirror dies, and proceeding to the next step when a reference condition is met (not shown). For example, when two or more are matched by examining four mirror dies, or when two or more are matched by examining three mirror dies, the next step is proceeded.

Therefore, it is possible to avoid additional confusion and apply to rework wafers by determining whether wafer alignment is normal using only the mirror die.

4 is a flowchart illustrating a method of separating a semiconductor chip according to another embodiment of the present invention.

In the wafer positioning method according to the present embodiment, when the position of the wafer is normal, the same reference numerals are used as those of the embodiment described with reference to FIGS. 2A to 3 except for the step of separating the semiconductor chip from the wafer. And duplicate descriptions are omitted.

Referring to FIGS. 2A to 4, when aligning the normal position of the wafer (S210) is normal, positioning of the wafer is completed and the semiconductor chip is removed from the first working position where the first working die 15 is located. Separate. On the contrary, if abnormal, the operator starts a manual alignment operation (S220). The stage is moved to position the camera on the first mirror die 11 that is previously designated (S221). The movement of the stage, for example, a driver (not shown) for driving the stage moves the stage on which the wafer is seated to position the camera on the first mirror die. The movement amount of the stage may be calculated using location information on the first mirror die stored in pre-entered map data.

The captured image of the first mirror die 11 is obtained to acquire a captured image of the first mirror die (S222). The captured image may represent an image of the first mirror die or an arrangement form with another die adjacent to the first mirror die.

The operator compares the captured image obtained in the step and the reference image obtained when the wafer is aligned at the correct position (S223). The operator adjusts the position of the stage such that the captured image and the reference image completely overlap each other (S224). When the operator determines that the captured image and the reference image overlap each other, the manual adjustment operation is terminated and the subsequent operation described below is performed.

When the manual sorting operation (S220) of the worker is completed, a validity checking step of the manual sorting operation is performed (S230). The validity checking step (S230) of the manual sorting operation is not a manual operation, and is a process that is automatically calculated by using information of pre-entered map data. The camera is positioned again on the first mirror die 11 (S231). The camera is positioned on the first mirror die 11 by moving the stage, and the movement amount of the stage may be calculated by using the position information stored in the input map data.

The first mirror die 11 is photographed to obtain a captured image of the first mirror die (S232). In operation S233, it is determined whether the captured image secured in the above step is compared with the reference image of the mirror die obtained from the position information stored in the input map data. When the captured image coincides with the mirror die of the input map data, the camera is positioned on the second mirror die 12.

The same operation as that of determining whether the first mirror die is matched with the second mirror die 12 is also performed.

This operation is repeated by comparing a plurality of mirror dies, that is, n mirror dies (n is a natural number), and proceeding to the next step when a reference condition is met. For example, when two or more are matched by examining four mirror dies, or when two or more are matched by examining three mirror dies, the next step is proceeded.

Subsequently, when the position of the mirror dies is determined to be normal, the picker (not shown) is moved to the first working position where the preset first working die 15 is located, and the picker moves the first working die 15. Separate from the wafer (S240). In this case, the picker may be disposed on top of each of the semiconductor dies in a vacuum suction manner to separate the semiconductor die from the adhesive sheet individually.

Therefore, it is possible to avoid additional confusion and apply to rework wafers by determining whether wafer alignment is normal using only the mirror die.

As described above, according to the embodiment of the present invention, by using a mirror die as a reference for the operation in the manual alignment operation of the operator, it is possible to avoid confusion with surrounding adjacent dies. In addition, by checking the validity of the manual alignment operation using the information of the mirror die after the manual alignment operation, it is possible to prevent the map push due to a mistake of the operator and can be applied to a rework wafer.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

10 wafer 11 first mirror die
12: second mirror die 13: third mirror die
14: fourth mirror die 15: first working die

Claims (7)

Aligning the wafer on a stage to fix the wafer;
Manually aligning the position of the wafer with respect to a predetermined verification point of the wafer; And
And reconfirming the alignment position of the wafer by comparing the manually aligned position of the wafer with a captured image of a mirror die and a reference image. The wafer positioning method according to claim 1, wherein the mirror die is a die formed at a periphery of the wafer and no circuit is formed. The method of claim 2, wherein manually aligning the position of the wafer comprises:
Comparing the captured image of the mirror die of the wafer with a reference image of the mirror die when the wafer is in position; And
And manually adjusting the stage such that the captured image and the reference image overlap. The method of claim 2, wherein the step of double-checking the alignment position of the wafer,
Imaging the mirror die of the wafer; And
And comparing the captured image with a reference image of the mirror die when the wafer is in position. 5. The wafer of claim 4, wherein the mirror die comprises first, second, third, and fourth mirror dies, wherein the second to fourth mirror dies are located at the periphery of the wafer clockwise from the first mirror die. Wafer positioning method characterized in that the four vertices of the square formed sequentially. 6. The method of claim 5, wherein reconfirming the alignment position of the wafer, wherein reconfirming the alignment position of the wafer when at least two or more mirror dies of the four mirror dies coincide with the reference image. Wafer positioning method, characterized in that terminated. Aligning the wafer on a stage to fix the wafer;
Manually aligning the position of the wafer with respect to a predetermined verification point of the wafer;
Reconfirming the alignment position of the wafer by comparing a position of the manually aligned wafer to a reference image with a captured image of a mirror die; And
And separating the semiconductor chip of the wafer from the wafer after reconfirming the alignment position of the wafer.
KR1020100054241A 2010-06-09 2010-06-09 Method of identifying location of wafer and method of separating semiconductor chip using the same KR20110134597A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100054241A KR20110134597A (en) 2010-06-09 2010-06-09 Method of identifying location of wafer and method of separating semiconductor chip using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100054241A KR20110134597A (en) 2010-06-09 2010-06-09 Method of identifying location of wafer and method of separating semiconductor chip using the same

Publications (1)

Publication Number Publication Date
KR20110134597A true KR20110134597A (en) 2011-12-15

Family

ID=45501808

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100054241A KR20110134597A (en) 2010-06-09 2010-06-09 Method of identifying location of wafer and method of separating semiconductor chip using the same

Country Status (1)

Country Link
KR (1) KR20110134597A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170132441A (en) * 2016-05-24 2017-12-04 세메스 주식회사 Method of forming a recipe of a die bonging process
KR20180125250A (en) * 2017-05-15 2018-11-23 세메스 주식회사 Method of inspecting ejector pins

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170132441A (en) * 2016-05-24 2017-12-04 세메스 주식회사 Method of forming a recipe of a die bonging process
KR20180125250A (en) * 2017-05-15 2018-11-23 세메스 주식회사 Method of inspecting ejector pins

Similar Documents

Publication Publication Date Title
JP5771623B2 (en) Wafer handler including vision system
KR101803792B1 (en) Stems and methods for automatically verifying correct die removal from film frames
US10668569B2 (en) Laser processing apparatus
US9034735B2 (en) Laser processing method for workpiece
EP1316989B1 (en) Method and apparatus for calibrating marking position in chip scale marker
KR100915418B1 (en) Method for marking wafer, method for marking failed die, method for aligning wafer and wafer test equipment
CN107564833B (en) Semiconductor conduction band arranging device and semiconductor conduction band arranging method
KR20180088261A (en) Semiconductor manufacturing device and manufacturing method of semiconductor device
TWI608584B (en) Apparatus and method for calibrating a marking position
KR20200012731A (en) Alignment method
US20190200495A1 (en) Chip-placing method performing an image alignment for chip placement and chip-placing apparatus thereof
US6421456B1 (en) Semiconductor wafer on which recognition marks are formed and method for sawing the wafer using the recognition marks
KR20110134597A (en) Method of identifying location of wafer and method of separating semiconductor chip using the same
TW202107657A (en) Die pickup method
JPH04363047A (en) Cutting and dicing system
CN111508861A (en) Semiconductor element bonding apparatus
CN110783246A (en) Alignment method
KR20120030841A (en) Wafer marking device, marking position inspecting member and controlling method of wafer marking device
KR20110069214A (en) Method of confirming a position of a wafer and method of separating a semiconductor chip using the same
JP5372429B2 (en) How to divide a plate
CN108878315B (en) Method for checking thimble
TW201517205A (en) Processing method
KR102618804B1 (en) Method of forming a recipe of a die bonging process
KR101015598B1 (en) Method of adjusting a position of a wafer and method of separating a semiconductor chip using the same
JP6091392B2 (en) Mark confirmation jig

Legal Events

Date Code Title Description
A201 Request for examination
E601 Decision to refuse application