KR20110130209A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to stabilize the operation of a source drive IC by initializing a delay locked loop using an ESD detection circuit if a noise is mixed with an external clock signal due to ESD. CONSTITUTION: A timing controller outputs data and an external clock signal as a differential signal pair. One or more source drive ICs generate internal clock signals with higher frequency than the frequency of the external clock signal. The source drive IC samples data according to the internal clock signals and detects a noise section of the external clock signal. A first DLL(37) delays the external clock signal and generates a reference internal clock synchronized with data. A second DLL(39) delays the reference internal clock and generates the internal clock signals which are divided into N parts in one cycle of the reference internal clock.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), which is applied to a display device in portable information equipment, office equipment, computer, etc., and is also rapidly replaced by a cathode ray tube.

A liquid crystal display device includes a plurality of source drive integrated circuits (“ICs”) for supplying data voltages to data lines of a liquid crystal display panel, and gate pulses (or scan pulses) to gate lines of the liquid crystal display panel. ) And a plurality of gate drive ICs for sequentially supplying the < RTI ID = 0.0 >

The timing controller supplies digital video data, a clock signal for sampling digital video data, a control signal for controlling the operation of the source drive ICs, and the like through an interface such as mini LVDS (Low Voltage Differential Signaling). do. The source drive ICs convert digital video data input in series from a timing controller into a parallel scheme, and then convert an analog data voltage using a gamma compensation voltage to supply data lines.

The timing controller supplies signals required for the source drive ICs in a multi-drop method in which clock and digital video data are commonly applied to the source drive ICs. This data transfer method includes R data transfer wiring, G data transfer wiring, B data transfer wiring, control wirings for controlling output and polarity conversion of the source drive ICs, and clock transfer wirings between the timing controller and the source drive ICs. Many wires are needed, including.

As an example of RGB data transmission in the mini-LVDS interface method, the mini-LVDS interface method transmits the RGB digital video data and the clock as differential signal pairs, so that the timing when the radix data and the even data are simultaneously transmitted Between the controller and the source drive ICs, at least 14 wires are required, including 12 RGB data wires and 2 clock transmission wires when RGB data is 8-bit data. In addition to these wires, the source output enable signal and the polarity control signal are required. There is a need for more control wiring for transmitting the data. If the RGB data is 10-bit data, at least 18 wires are required. Therefore, it is difficult to reduce the width of the printed circuit board (PCB) disposed between the timing controller and the source drive ICs because many wirings should be formed.

The present invention provides a liquid crystal display device capable of minimizing signal transmission wirings between a timing controller and source drive ICs.

A liquid crystal display device of the present invention includes a timing controller for outputting data and an external clock signal as difference signal pairs; One or more source drive ICs generating internal clock signals having a higher frequency than the external clock signal, sampling the data according to the internal clock signals, and detecting a noise section of the external clock signal; A data wire pair for serially connecting the timing controller and the source drive ICs to serially transfer the data to the source drive ICs; And a clock signal wire pair connecting the timing controller and the source drive ICs in a cascade form to transmit the clock signal to the source drive ICs.

The external clock signal includes a normal clock having a frequency lower than a transmission frequency of the data and a special code having a period longer than a period of the normal clock. The special code is sent to the source drive ICs prior to the data.

Each of the source drive ICs uses a delay lock loop (DLL) to delay the external clock signal to generate a plurality of internal clock signals, sample the data using the internal clock signals, and convert the data into parallel data. And a data sampling and serial-to-parallel conversion unit for conversion.

The data includes video data including R data, G data and B data, and control data including control information for controlling the operation of the source drive ICs.

The data sampling and serial-to-parallel converter is configured to restore the control information to a source output enable signal for controlling the output timing of the source drive IC, and a polarity control signal for controlling the polarity of the data voltage output from the source drive IC. Occurs.

The data sampling and serial-to-parallel converter includes: a first DLL configured to delay the external clock signal to generate a reference internal clock synchronized with the data; A second DLL delaying the reference internal clock to generate internal clock signals equal to N (N is the number of bits of data x 2) within one period of the reference internal clock; A phase detector configured to sample the data using clocks synchronized with the center of the data among the internal clock signals, and detect edge information of the data using clocks synchronized with the edges of the data; A data alignment unit converting the data input from the phase detector into parallel data; A third DLL that delays the external clock signal to generate internal clock signals equally M (M is the number of bits of data) equally within one period of the external clock signal; And sampling the external clock signal using the internal clock signals input from the third DLL to detect the transition information of the data, and a noise period of the external clock signal based on the transition information of the data. And an ESD detector for detecting. The ESD detector initializes the third DLL when a noise period of the external clock signal is detected.

The third DLL outputs a high logic lock signal Phase_Lock when the rising edge of the external clock signal is synchronized with the rising edge of the last clock of the internal clock signals.

The ESD detector samples the external clock signal using the internal clock signals inputted from the third DLL, and outputs a low logic signal lock signal H_Lock when the external clock signal is generated at a normal period. ; A transition detector for sampling the external clock signal using the internal clock signals input from the third DLL and outputting a high logic lock signal T_Lock when one or more transitions occur within one period of the external clock signal. ; An inverter for inverting the lock signal input from the harmonic lock detector; An AND gate for outputting an AND operation result of the lock signals Phase_Lock, H_Lock, and T_Lock input from the third DLL, the harmonic lock detector, and the transition detector as an initialization control signal of the third DLL It is provided.

The data sampling and serial-to-parallel converter is configured to determine a delay value of the first DLL between the data and the external clock signal by using a sharpnessbot connected between the phase detector and the first DLL and a finite state machine (FSM). A temperature compensation loop is further provided that adjusts according to the time difference.

The present invention can minimize the signal transmission wires between the timing controller and the source drive ICs by connecting the timing controller and the source drive ICs in a point-to-point form and transmitting a clock signal to the source drive ICs in the cascade form. In addition, the present invention transmits a special code having a period longer than the normal clock of the external clock signal prior to data transmission, and if a noise is mixed into the external clock signal due to ESD using an ESD detection circuit, a delay lock loop ( By initializing the DLL, the operation of the source drive IC can be stabilized.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
2 is a timing diagram showing an external clock signal and data generated as a difference signal pair from a timing controller.
3 is a timing diagram showing a circuit configuration of the source drive IC shown in FIG.
FIG. 4 is a circuit diagram showing in detail the data sampling and serial-to-parallel converter shown in FIG. 3.
FIG. 5 is a waveform diagram illustrating an operation of the first DLL illustrated in FIG. 4.
FIG. 6 is a waveform diagram illustrating internal clock signals output from the second DLL illustrated in FIG. 4.
7 is a waveform diagram showing the operation of the phase detector shown in FIG.
8 is a waveform diagram illustrating an operation of the data alignment unit illustrated in FIG. 4.
FIG. 9 is a circuit diagram illustrating in detail the third DLL and the ESD detector illustrated in FIG. 4.
10 is a waveform diagram illustrating internal clock signals output from a third DLL.
11 and 12 are waveform diagrams showing the operation of the ESD detector shown in FIG.
FIG. 13 is a circuit diagram illustrating a D flip-flop of the special code detector shown in FIG. 4.
FIG. 14 is a waveform diagram illustrating the operation of the D flip-flop shown in FIG. 13.
15 is a waveform diagram showing an experimental result of the present invention.
16 is a waveform diagram showing an example of a packet configuration of control data.
17 and 18 are diagrams illustrating an example of a code mapping table of control data.
FIG. 19 is a diagram illustrating an input / output signal of a chip configuration of the maternality boter shown in FIG. 4.
20 is a view showing an input / output signal of the finite state machine shown in FIG.
21 is a diagram illustrating an example count operation of a finite state machine.
Fig. 22 is a waveform diagram showing an example of operation of the magority bot and the finite state machine.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Component names used in the following description are selected in consideration of ease of specification, and may be different from the actual product part names.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel LCP, a timing controller TCON, one or more source drive ICs SIC # 1 to SIC # 8, and Gate drive ICs (GIC).

The liquid crystal layer is formed between the glass substrates of the liquid crystal display panel LCP. The liquid crystal display panel LCP includes m × n liquid crystal cells Clc arranged in a matrix by a cross structure of m data lines DL and n gate lines GL.

A pixel array including data lines DL, gate lines GL, TFTs, and a storage capacitor Cst is formed on a lower glass substrate of the liquid crystal display panel LCP. The liquid crystal cells Clc are driven by an electric field between the pixel electrode supplied with the data voltage through the TFT and the common electrode supplied with the common voltage Vcom. The gate electrode of the TFT is connected to the gate line GL, and the drain electrode thereof is connected to the data line DL. The source electrode of the TFT is connected to the pixel electrode of the liquid crystal cell. The TFT is turned on according to the gate pulse supplied through the gate line GL to supply the positive / negative analog video data voltage from the data line DL to the pixel electrode of the liquid crystal cell Clc. A black matrix, a color filter, a common electrode, and the like are formed on the upper glass substrate of the liquid crystal display panel LCP.

The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. In the driving method, the pixel electrode 1 is formed on the lower glass substrate.

A polarizing plate is attached to each of the upper and lower glass substrates of the liquid crystal display panel LCP, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed. A spacer may be formed between the upper glass substrate and the lower glass substrate of the liquid crystal display panel LCP to maintain a cell gap of the liquid crystal cell Clc.

The liquid crystal display device of the present invention can be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, FFS mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller (TCON) is a vertical / horizontal synchronization signal (Vsync, Hsync) from an external system on chip (SoC) including a video source through interfaces such as LVDS (Low Voltage Differential Signaling) interface and Transition Minimized Differential Signaling (TMDS) interface. The external timing signal such as an external data enable signal (Data Enable, DE), a dot clock (CLK), and the like are received. The timing controller TCON is connected in series to each of the source drive ICs SIC # 1 to SIC # 8 in a point-to-point form.

The timing controller TCON generates data such as RGB digital video data and control data as a differential signal pair. The control data includes source control data for controlling the output timing of the data voltages output from the source drive ICs SIC # 1 to SIC # 8, polarities of the data voltages, and the like. The control data may include gate control data for controlling the operation timing of the gate drive IC (GIC). Alternatively, the timing controller TCON generates separate gate control signals for controlling the operation timing of the gate drive ICs GIC using timing signals input from an external Soc, and outputs the gate control signals. The gate drive ICs GIC may be transmitted through separate gate control wires (not shown) separated from the wire pairs.

The timing controller TCON simultaneously transmits data such as RGB digital video data and control data to the source drive ICs SIC # 1 to SIC # 8 through a pair of data wires represented by solid lines. The timing controller TCON generates the external clock signal EXTCLK as a difference signal pair, and the one or more source drive ICs SIC # 1 to SIC # through a pair of clock signal wires represented by a dotted line of the external clock signal EXTCLK. 8) to transmit. The external clock signal includes normal clocks generated in a section in which data exists within a frame period, and special codes longer than a normal clock. The normal clocks and special codes of the external clock signal EXTCLK are transmitted at a transmission frequency lower than that of the RGB digital video data. The special code is generated in the blank period immediately before the start of one frame period. The special code has a period different from that of the normal clock, and then informs the source drive ICs SIC # 1 to SIC # 8 that data is transferred to the source drive ICs SIC # 1 to SIC # 8. do.

The normal clock frequency of the external clock signal EXTCLK is 1 / N of the data transmission frequency when one sub-pixel data is transmitted per clock as shown in FIG. 2 (where N is the number of bits of the RGB digital video data). Low enough, when 1 pixel data is transmitted per clock, 1 / (N * 3, 3 is the number of subpixels included in 1 pixel). When transmitted, the normal clock frequency of the external clock signal EXTCLK is as low as 1/10 of the data transmission frequency. In addition, when 30 bits of R, G, and B subpixel data are transmitted per clock, the normal clock frequency of the external clock signal EXTCLK is lowered to 1/30 of the data transmission frequency.

The source drive ICs SIC # 1 to SIC # 8 are connected in a point-to-point form with the timing controller TCON through two pairs of data wire pairs. Each of the source drive ICs SIC # 1 to SIC # 8 may be connected to data lines of a liquid crystal display panel LCP through a chip on glass (COG) process or a tape automated bonding (TAB) process.

The source drive ICs SIC # 1 to SIC # 8 and the timing controller TCON are connected in a cascade form through a pair of clock signal wires. The source drive ICs SIC # 1 to SIC # 8 receive RGB digital video data and control data through data wire pairs, and receive external clock signal pairs through clock signal wire pairs. The source drive ICs SIC # 1 to SIC # 8 transfer an external clock signal pair input through a clock signal wire pair to a neighboring source drive IC. The source drive ICs SIC # 1 to SIC # 8 recover an external clock signal EXTCLK from an external clock signal pair, and use an external clock signal using a delay locked loop (DLL). Delaying (Clcok) generates the internal clock signals of the number of bits x 2 of RGB digital video data. The source drive ICs SIC # 1 to SIC # 8 sample the RGB digital video data and the control data using the restored internal clock signals and convert the sampled RGB digital video data into a parallel data system.

The source drive ICs SIC # 1 to SIC # 8 decode the control data input through the data wire pair by code mapping to restore the source control data and the gate control data. The source drive ICs SIC # 1 to SIC # 8 convert the RGB digital video data, which is converted into a parallel scheme according to the source control data, into positive / negative analog data voltages, thereby converting the data lines of the liquid crystal display panel LCP. Supply to (DL). The source drive ICs SIC # 1 to SIC # 8 may transmit gate control data to one or more of the gate drive ICs GIC.

The gate drive IC (GIC) may be connected to the gate lines of the lower glass substrate of the liquid crystal display panel through the TAP process or may be directly formed on the lower glass substrate of the liquid crystal display panel (LCP) by the gate in panel (GIP) process. . The gate drive IC GIC is sequentially supplied with the gate pulse to the gate lines GL according to the gate control data supplied from the timing controller TCON or supplied through the source drive ICs SIC # 1 to SIC # 8. Supply. The gate control data includes a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP controls the start horizontal line at which the scan starts in one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to a shift register in the gate drive IC GIC to sequentially shift the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive IC GIC.

3 is a block diagram illustrating an internal circuit configuration of the source drive ICs SIC # 1 to SIC # 8.

Referring to FIG. 3, each of the source drive ICs SIC # 1 to SIC # 8 may apply positive / negative data voltages to k data lines D1 to Dk (k is a positive integer less than m). Supply.

Each of the source drive ICs SIC # 1 to SIC # 8 includes a data sampling and serial-to-parallel converter 21, a digital to analog converter (DAC) 22, and an output circuit ( 23) and the like.

The data sampling and serial-to-parallel converter 21 generates internal clock signals using a DLL and converts them into parallel data by sampling and latching RGB digital video data serially inputted through data wire pairs according to the internal clock signals. do. In addition, the data sampling and serial-to-parallel converter 21 restores the control data input through the data wire pair by code mapping to generate source control data. The polarity control signal POL indicates the polarity of the positive / negative analog data voltages supplied to the data lines D1 to Dm. The source output enable signal SOE controls the output timing of the source drive ICs SIC # 1 to SIC # 8. When gate control data is encoded in the control data, the data sampling and serial-to-parallel converter 21 recovers the gate control data from the control data input through the data wire pair and transmits the gate control data to the gate drive IC (GIC). Gate control data includes gate start pulses, gate output enable signals, and the like.

The DAC 22 converts the RGB digital video data from the data sampling and serial-to-parallel converter 21 into the positive gamma compensation voltage GH and the negative gamma compensation voltage GL to convert the positive / negative analog video data. Generate voltage. The DAC 22 inverts the polarity of the positive / negative analog video data voltage in response to the polarity control signal POL.

The output circuit 23 supplies the charge share voltage or the common voltage Vcom to the data lines D1 to Dk through the output buffer during the high logic period of the source output enable signal SOE. The output circuit 23 supplies the positive / negative analog video day voltage to the data lines D1 to Dk through the output buffer during the low logic period of the source output enable signal SOE. The charge share voltage is generated when the data line to which the positive voltage is supplied and the data line to which the negative voltage is supplied are shorted, and have an average voltage level of the positive voltage and the negative voltage.

4 is a diagram illustrating the data sampling and serial-to-parallel converter 21 in detail.

Referring to FIG. 4, the data sampling and serial-to-parallel conversion unit 21 includes a first DLL 37, a second DLL 39, a phase detector 44, a data alignment unit 45, and a third DLL 32. , An electrostatic discharge (hereinafter, "ESD") detector 33, and a special code detector 34.

The first DLL 37 is a deskew DLL. The first DLL 37 receives an external clock signal EXTCLK through a clock wire pair and an operational transconductance amplifier 35, and also includes a linear equalizer 42. The data 43 is input through a preamplifier including an OTA 43. The OTAs 35 and 43 amplify the differential signal pairs to restore the high voltage external clock signal EXTCLK. The first DLL 37 delays the phase of the external clock signal Clok to generate the reference internal clock C0 synchronized with the rising edge of the data as shown in FIG. 5. Accordingly, the first DLL 37 corrects skew generated on the data transmission channel and the clock signal transmission channel by synchronizing the data with the reference internal clock C0. In order to synchronize the rising edge of the data with the reference internal clock C0 output from the first DLL 37, the data must also be generated in the same form as the external clock EXTCLK. To this end, the timing controller TCON transmits a preamble signal having the same waveform as the clock through the data wire pair before transmitting the control / video data. The data shown in FIG. 5 is a preamble signal. The first DLL 37 fixes a code for delaying the external clock signal EXTCLK after the phase lock operation of the data and the clock is completed. The low drop-out (LDO) regulator 36 generates a driving power supply of the first DLL 37 and removes noise of the driving power supply to stabilize the operation of the first DLL 37.

The second DLL 39 is a multi-phase DLL, and receives a phase lock signal Desk_LOCK and a reference internal clock C0 indicating whether the data (preamble signal) and the clock are synchronized. The second DLL 39 delays the reference internal clock C0 input from the first DLL 37 to uniformly equal N (N is the number of bits of data x 2) within one period of the reference internal clock C0. The first to twentieth internal clock signals MC1 to MC20 are generated. In the following description, N is assumed to be 20. The rising edge of the 20th internal clock signal MC20 delayed 20th from the reference internal clock C0 is synchronized with the rising edge of the reference internal clock C0. The second DLL 39 receives a feedback input of the twentieth internal clock signal MC20 to synchronize the rising edge of the reference internal clock C0 and the rising edge of the twentieth internal clock signal MC20. The internal clock signals MC1 ˜ MC20 generated from the second DLL 39 may be output to another external circuit through the clock buffer 41.

The phase detector 44 receives amplified data through the first through twentieth internal clock signals MC1 ˜ MC20 and the OTA 43 generated from the second DLL 39. The phase detector 44 samples data based on the odd-numbered clock signals MC1, MC3,... MC19 synchronized with the center of the data among the first to twentieth internal clock signals MC1 to MC20 as shown in FIG. 7. The edge information of the data is detected based on the even-numbered clock signals MC2, MC4, ... MC20 synchronized with the edges of the data. The edge information is used to compensate for the phase difference between the data and the external clock signal EXTCLK. The phase detector 44 may be implemented by a known Alexander PD (Phase detector), and may sample data using flip-flops that receive the internal clock signals MC1 to MC20 and data.

When data is sampled based on the internal clock signals MC1 to MC20 sequentially delayed from the second DLL 39, the serial data input to the data alignment unit 45 may be sequentially phased by a time difference between the internal clock signals. Delay. As illustrated in FIG. 8, the data alignment unit 45 latches serial input data input from the phase detector 44, converts the serial input data into parallel data, and outputs the parallel input data to the DAC 22.

As shown in FIGS. 9 and 10, the third DLL 32 receives the external clock signal EXTCLK, sequentially delays the external clock signal EXTCLK, and uniformly M within one period of the external clock signal EXTCLK. (M is the number of bits of data) The first to tenth internal clock signals C1 to C10 are generated. In the following description, it is assumed that M is 10. The rising edge of the tenth internal clock signal C10 delayed tenth from the external clock signal EXTCLK is synchronized with the rising edge of the external clock signal EXTCLK. The third DLL 32 receives the input of the tenth internal clock signal C10 in order to synchronize the rising edge of the external clock signal EXTCLK and the rising edge of the tenth internal clock signal C10, and receives the external clock signal EXTCLK. The lock signal Phase_Lock indicating phase lock is generated as a high logic when the rising edge of the C1 and the rising edge of the tenth internal clock signal C10 are synchronized. The third DLL 32 may be integrated with the second DLL 39 by sharing common circuits with the second DLL 39.

The ESD detector 33 receives the external clock signal EXTCLK and the first to tenth internal clock signals C1 to C10 generated by the third DLL 32. The ESD detector 33 uses an harmonic lock detector 92, a transition detector 93, an inverter 94, and an AND gate 95 as shown in FIG. Detects a noise section. The harmonic lock detector 92 receives the first to tenth internal clock signals C1 to C10 input from the third DLL 32 to sample the external clock signal EXTCLK. When the phases of the external clock signal EXTCLK and the internal clock signals C1 to C10 are locked within one period T of the external clock signal EXTCLK, the harmonic lock detector 92 is shown in FIG. Likewise, one or two transition generation positions of the external clock signal EXTCLK can be detected within 1T of the external clock signal EXTCLK. When there are three or more transition positions within 1T of the external clock signal EXTCLK as shown in FIG. 12, the harmonic lock detector 92 has the external clock signal EXTCLK and the internal clock signals C1 to C10 at 1.5T or more. It can be seen that the phase is fixed and the phase of the external clock signal EXTCLK and the internal clock signals C1 to C10 is fixed at 0.5T or less when there is no transition within one period of the external clock signal EXTCLK. . The harmonic lock detector 92 outputs the lock signal H_Lock of the low logic signal " 0 " when the internal clock signals C1 to C10 are fixed in phase within 1T of the external clock signal EXTCLK.

The transition detector 93 samples the external clock signal EXTCLK with the first to tenth internal clock signals C1 to C10 and generates a high logic when the one or more transitions occur within 1T of the external clock signal EXTCLK. The lock signal T_Lock of 1 "is output. The transition detector 93 inverts the lock signal T_Lock to low logic when 0 or 1 is detected within 1T of the external clock signal EXTCLK.

The inverter 94 inverts the lock signal H_Lock input from the harmonic lock detector 92 and outputs it to the AND gate 95. The AND gate 95 performs a final phase result of the AND operation of the lock signals Phase_Lock, H_Lock, and T_Lock input from the third DLL 32, the harmonic lock detector 92, and the transition detector 93. Output as a fixed lock signal. The output LOCKE of the AND gate 95 is input to the reset terminal of the third DLL 32.

When the external clock signal EXTCLK is normally generated, in Fig. 9, Phase_Lock is generated with high logic "1", H_Lock is low logic "0", and T_Lock is generated with high logic "1". Thus, in the steady state, the output of the AND gate 95 is generated with high logic. On the other hand, when Phase_Lock or T_Lock is low logic or H_Lock is high logic due to the influence of ESD, the output LOCKE of AND gate 95 is generated in low logic. At this time, the third DLL 32 ) Is reset to fix the phases of the external clock signal EXTCLK and the internal clock signals C1 to C10.

The special code detector 34 may be implemented with one D flip flop. The external clock signal EXTCLK is input to the input terminal D of the D flip flop, and the external clock signal EXTCLK delayed by 3T / 4 is input to the clock terminal of the D flip flop. The D flip-flop samples the external clock signal EXTCLK on the rising edge of the delayed external clock signal EXTCLK + 3T / 4 and outputs the sampling result. The high logic period (or pulse width period) of the special code is 1.5 times longer than the period T of the normal clock of the external clock signal EXTCLK as shown in FIG. 14. Therefore, when the special code is input, the D flip-flop outputs the special code detection signal SCDE to the high logic of 2T or more and 2T or more. The special code detection signal SCDE is input to the reset terminals of the first and second DLLs 37 and 39. Therefore, when a special code is detected, the first and second DLLs 37 and 39 are reset.

15 is a waveform diagram showing an experimental result of the data sampling and serial-to-parallel converter 21. In FIG. 15, EXT_DATA1 and EXT_DATA2 are test data generated from the timing controller TCON, and EXT_CLK1 and EXT_CLK2 are external clock signals EXTCLK generated from the timing controller TCON. RX1_OUT [1] to RX1_OUT [10] indicate the output of the data alignment unit 45 when EXT_DATA1 and EXT_CLK1 are input to the data sampling and serial-to-parallel conversion unit 21. RX2_OUT [1] to RX2_OUT [10] indicate the output of the data alignment unit 45 when EXT_DATA2 and EXT_CLK2 are input to the data sampling and serial-to-parallel conversion unit 21. As can be seen from the experimental result of FIG. 15, the data sampling and serial-to-parallel converter 21 can completely restore two types of test data.

The data sampling and serial-to-parallel converter 21 further includes a control data recovery unit 46. The control data recovery unit 46 stores the code mapping tables as shown in Figs. 17 and 18, and restores the control data input through the data wire pair based on the time information defined in the code mapping table.

The data sampling and serial-to-parallel converter 21 further includes a clock transmitter 31. The clock transmitter 31 converts the external clock signal EXTCLK into a low voltage difference signal pair and transmits it to another neighboring source drive IC.

16 is a waveform diagram illustrating an example of a packet configuration of control data transmitted through a data wire pair. 17 and 18 are diagrams illustrating an example of a code mapping table of control data.

16 to 18, the control data packet includes control start data CTR_Start, first and second SOE start data SOE_Start1, SOE_Start2, first and second SOE width data SOE Width1, SOE Width2, First and second option control data CRT1, CTR2, and the like.

The control start data CTR_Start is an identification code indicating a start of a control data packet and is generated with a code value different from that of the data start data DATA Start indicating a start of RGB digital video data. For example, the control start data CTR_Start may be generated as '101010' as shown in FIG. 17, while the data start data DATA Start may be generated as '010101'. During the blank period before the data start, dummy data not displayed on the liquid crystal display panel LCP may be transmitted through the data line pair. The dummy data may be replaced with a control data packet including additional control information not defined in the control data. That is, the control data packet is not limited to FIGS. 16 to 18 but can be extended.

The first and second SOE start data SOE_Start1 and SOE_Start2 define the number of external clock signals EXTCLK from the time when the control start data CTR_Start is received to the rising time of the source output enable signal SOE. After the special code, the control data recovery unit 46 totals 12 bits x the external clock signal EXTCLK by 6 bits of the first low-order bit LSB input from among 10 bits of the first and second SOE start data SOE_Start1 and SOE_Start2, respectively. Generate a pulse of the source output enable signal (SOE) to rise at the time elapsed by. Therefore, the rising time of the source output enable signal SOE may be adjusted according to the first and second SOE start data SOE_Start1 and SOE_Start2.

The first and second SOE width data SOE Width1 and SOE Width2 define a high logic duration (or high logic duration time) in the pulse of the source output enable signal SOE. The control data reconstructor 46 is a lower bit LSB 6 bits inputted first among 10 bits of the first and second SOE width data SOE Width1 and SOE Width2 after the rising time of the source output enable signal SOE. The pulses of the source output enable signal SOE are generated in high logic for a total of 12 bist x external clock signal EXTCLK time, and then inverted to low logic. Accordingly, the high logic duration of the source output enable signal SOE is adjustable according to the first and second SOE width data SOE Width1 and SOE Width2.

The first and second option control data CRT1 and CTR2 may include information of control signals necessary for controlling the source drive ICs SIC # 1 to SIC # 8 in addition to the source output enable signal SOE. The first and second option control data CRT1 and CTR2 include the polarity control signal POL, the charge share MODE On / Off, the horizontal polarity inversion period H2DOT, and the source drive ICs SIC #. Offset correction of 1 to SIC # 8, output power of source drive ICs SIC # 1 to SIC # 8, channel selection of source drive ICs SIC # 1 to SIC # 8, gate start pulse (GSP) Define source control data and gate control data. In order to improve the image quality, the rising time, pulse width, etc. of the source output enable signal SOE may be changed or turned on or off every horizontal period. The control data recovery unit 46 uses the information of the SOE start data SOE_Start1 and SOE_Start2, the SOE width data SOE Width1 and SOE Width2, and the first option control data CRT1 to output the source output enable signal SOE. Adjust the rising time, pulse width, and pulse on / off. The polarity inversion period H2DOT is an option signal for selecting the horizontal polarity inversion period of the data voltages simultaneously output from the source drive ICs SIC # 1 to SIC # 8 as horizontal 1 dot or horizontal 2 dots.

The data sampling and serial-to-parallel converter 21 may further include a majority voter 40 and a finite state machine 38.

The temperature compensation loop (Loop) composed of the phase detector 44, the mammity bot 40, the FSM 38, the first DLL 37, and the second DLL 39 has a data and an external clock due to temperature change. Compensate for the time difference between the signals EXTCLK. The mammity bot 40 and the FSM 38 are used to stabilize the loop while being less affected by noise mixed in data or the external clock signal EXTCLK.

19 is a view showing an input / output signal of the chip configuration of the mammity bot 40. 20 shows an input / output signal of the FSM 38. 21 is a diagram illustrating an example count operation of the FSM 38. 22 is a waveform diagram showing an example of the operation of the magority bot 40 and the FSM 38. As shown in FIG.

19 to 22, since the Alexander PD used as the phase detector 44 is a bang bang PD, when the output phase is fixed, UP <9: 0> and DN <9: 0> are periodically repeated. The mammity bot 40 outputs the final UP or DN by determining whether the number of UPs or the number of DNs is large by inputting UP 10bits and DN 10bits input from the phase detector 44. The FSM 38 receives Major_UP and Major_DN signals from the mammity bot 40 to operate the counter up or down as shown in FIG. 21.

When the deskew operation of the first DLL 37 is completed, the delay value of the delay line of the first DLL 37 is fixed, and during output of the second DLL 39 as shown in FIG. 22A. The odd internal clock signals MC1, MC3 ... MC19 are synchronized to the center of the data, and the even internal clock signals MC2, MC4 ... MC20 are synchronized to the edge of the data. Due to the internal temperature change of the chip of the source drive ICs (SIC # 1 to SIC # 8), as shown in FIG. 22B, the data delay is increased by t1 and the delay of the external clock signal EXTCLK is not changed. In this case, phase detector 44 generates an UP output. In the case of FIG. 22B, the FSM 38 advances an up count to increase the clock delay value of the first DLL 37 by t1. As shown in (c) of FIG. 22, in the case where the data delay is reduced by t1 due to the change in the chip internal temperature of the source drive ICs SIC # 1 to SIC # 8, and there is no change in the delay of the external clock signal EXTCLK. Phase detector 44 generates a DN output. In the case of (c) of FIG. 22, the FSM 38 advances the down count to decrease the clock delay value of the first DLL 37 by t1. Referring to FIG. 22D, since 10 bits are included in one external clock signal EXTCLK, the phase detector 44 outputs UP 10 bits and DN 10 bits. For example, if an edge of data is located between the second and third internal clock signals MC2 and MC3, UP <1> becomes high logic and if there is no edge, low logic. If an edge of data is positioned between the first and second internal clock signals MC1 and MC2, DN <1> becomes high logic, and if there is no edge, low logic. Similarly, since UP <10: 1> and DN <10: 1> have a high logic or low logic value, respectively, the number of UPs or DNs in one period of the external clock signal EXTCLK is compared. It is necessary to decide whether the loop direction is UP or DN. Thus, the mammity bot 40 is used to determine the final UP or DN and the output of the FSM 38 is used to increase or decrease the delay value of the first DLL 37.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

TCON: Timing Controllers SIC: Source Drive ICs
GIC: Gate Drive IC 21: Data Sampling and Parallel Converter
22: digital-to-analog converter (DAC) 23: output circuit
31: clock transmission unit 32: third DLL
33: ESD detector 34: Special code detector
37: first DLL 39: second DLL
38: finite state machine (FSM)
40: Majority Voter
46: control data recovery unit

Claims (7)

A timing controller for outputting data and an external clock signal as difference signal pairs;
One or more source drive ICs generating internal clock signals having a higher frequency than the external clock signal, sampling the data according to the internal clock signals, and detecting a noise section of the external clock signal;
A data wire pair for serially connecting the timing controller and the source drive ICs to serially transfer the data to the source drive ICs; And
A pair of clock signal wires connecting the timing controller and the source drive ICs in a cascade form to transmit the clock signal to the source drive ICs,
The external clock signal includes a normal code having a frequency lower than a transmission frequency of the data and a special code having a period longer than a period of the normal clock.
And the special code is transmitted to the source drive ICs prior to the data. The method of claim 1,
Each of the source drive ICs,
Delay the external clock signal using a delay lock loop (DLL) to generate a plurality of internal clock signals, and use the internal clock signals to sample the data and convert the data into parallel data. And a converting unit. The method of claim 2,
The data includes video data including R data, G data and B data, and control data including control information for controlling the operation of the source drive ICs,
The data sampling and serial-to-parallel converter,
Restoring the control information to generate a source output enable signal for controlling the output timing of the source drive IC and a polarity control signal for controlling the polarity of the data voltage output from the source drive IC; Device. The method of claim 1,
The data sampling and serial-to-parallel converter,
A first DLL configured to delay the external clock signal to generate a reference internal clock synchronized with the data;
A second DLL delaying the reference internal clock to generate internal clock signals equal to N (N is the number of bits of data x 2) within one period of the reference internal clock;
A phase detector configured to sample the data using clocks synchronized with the center of the data among the internal clock signals, and detect edge information of the data using clocks synchronized with the edges of the data;
A data alignment unit converting the data input from the phase detector into parallel data;
A third DLL that delays the external clock signal to generate internal clock signals equally M (M is the number of bits of data) equally within one period of the external clock signal; And
The external clock signal is sampled using the internal clock signals input from a third DLL to detect the transition information of the data, and a noise section of the external clock signal is determined based on the transition information of the data. Has an ESD detector for detecting,
And the ESD detector initializes the third DLL when a noise section of the external clock signal is detected. The method of claim 4, wherein
And the third DLL outputs a high logical lock signal (Phase_Lock) when the rising edge of the external clock signal and the rising edge of the last clock of the internal clock signals are synchronized. The method of claim 5, wherein
The ESD detector,
A harmonic lock detector for sampling the external clock signal using the internal clock signals inputted from the third DLL and outputting a low logic signal lock signal (H_Lock) when the external clock signal is generated at a normal period;
A transition detector for sampling the external clock signal using the internal clock signals input from the third DLL and outputting a high logic lock signal T_Lock when one or more transitions occur within one period of the external clock signal. ;
An inverter for inverting the lock signal input from the harmonic lock detector;
An AND gate for outputting an AND operation result of the lock signals Phase_Lock, H_Lock, and T_Lock input from the third DLL, the harmonic lock detector, and the transition detector as an initialization control signal of the third DLL Liquid crystal display comprising a. The method according to claim 1 or 4,
The data sampling and serial-to-parallel converter,
A temperature compensation loop that adjusts a delay value of the first DLL according to a time difference between the data and the external clock signal by using a mathematics botter connected to the phase detector and the first DLL and a finite state machine (FSM) Liquid crystal display device further comprising.

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