KR20110116036A - Soi 웨이퍼의 제조 방법 - Google Patents
Soi 웨이퍼의 제조 방법 Download PDFInfo
- Publication number
- KR20110116036A KR20110116036A KR1020117019761A KR20117019761A KR20110116036A KR 20110116036 A KR20110116036 A KR 20110116036A KR 1020117019761 A KR1020117019761 A KR 1020117019761A KR 20117019761 A KR20117019761 A KR 20117019761A KR 20110116036 A KR20110116036 A KR 20110116036A
- Authority
- KR
- South Korea
- Prior art keywords
- wafer
- insulating film
- soi
- ion implantation
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
- H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/60—Wet etching
- H10P50/64—Wet etching of semiconductor materials
- H10P50/642—Chemical etching
- H10P50/644—Anisotropic liquid etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Element Separation (AREA)
- Weting (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009043403A JP5244650B2 (ja) | 2009-02-26 | 2009-02-26 | Soiウェーハの製造方法 |
| JPJP-P-2009-043403 | 2009-02-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20110116036A true KR20110116036A (ko) | 2011-10-24 |
Family
ID=42665227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020117019761A Ceased KR20110116036A (ko) | 2009-02-26 | 2010-01-08 | Soi 웨이퍼의 제조 방법 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20110281420A1 (https=) |
| EP (1) | EP2402983B1 (https=) |
| JP (1) | JP5244650B2 (https=) |
| KR (1) | KR20110116036A (https=) |
| CN (1) | CN102326227A (https=) |
| WO (1) | WO2010098007A1 (https=) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150013164A (ko) * | 2012-05-24 | 2015-02-04 | 신에쯔 한도타이 가부시키가이샤 | Soi 웨이퍼의 제조방법 |
| KR20150052041A (ko) * | 2012-09-03 | 2015-05-13 | 신에쯔 한도타이 가부시키가이샤 | Soi 웨이퍼의 제조방법 |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009124060A1 (en) | 2008-03-31 | 2009-10-08 | Memc Electronic Materials, Inc. | Methods for etching the edge of a silicon wafer |
| EP2359390A1 (en) | 2008-11-19 | 2011-08-24 | MEMC Electronic Materials, Inc. | Method and system for stripping the edge of a semiconductor wafer |
| JP5477277B2 (ja) * | 2010-12-20 | 2014-04-23 | 信越半導体株式会社 | Soiウェーハの製造方法 |
| US8853054B2 (en) | 2012-03-06 | 2014-10-07 | Sunedison Semiconductor Limited | Method of manufacturing silicon-on-insulator wafers |
| JP6056516B2 (ja) * | 2013-02-01 | 2017-01-11 | 信越半導体株式会社 | Soiウェーハの製造方法及びsoiウェーハ |
| US9177967B2 (en) * | 2013-12-24 | 2015-11-03 | Intel Corporation | Heterogeneous semiconductor material integration techniques |
| CN105280541A (zh) * | 2015-09-16 | 2016-01-27 | 中国电子科技集团公司第五十五研究所 | 一种用于超薄半导体圆片的临时键合方法及去键合方法 |
| FR3076393A1 (fr) * | 2017-12-28 | 2019-07-05 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de transfert d'une couche utile |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534380B1 (en) * | 1997-07-18 | 2003-03-18 | Denso Corporation | Semiconductor substrate and method of manufacturing the same |
| JPH11121310A (ja) * | 1997-10-09 | 1999-04-30 | Denso Corp | 半導体基板の製造方法 |
| JP3030545B2 (ja) | 1997-07-19 | 2000-04-10 | 信越半導体株式会社 | 接合ウエーハの製造方法 |
| DE69917819T2 (de) * | 1998-02-04 | 2005-06-23 | Canon K.K. | SOI Substrat |
| JP4313874B2 (ja) * | 1999-02-02 | 2009-08-12 | キヤノン株式会社 | 基板の製造方法 |
| JP4304879B2 (ja) | 2001-04-06 | 2009-07-29 | 信越半導体株式会社 | 水素イオンまたは希ガスイオンの注入量の決定方法 |
| FR2880184B1 (fr) * | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
| US20080315349A1 (en) * | 2005-02-28 | 2008-12-25 | Shin-Etsu Handotai Co., Ltd. | Method for Manufacturing Bonded Wafer and Bonded Wafer |
| JP2007141946A (ja) * | 2005-11-15 | 2007-06-07 | Sumco Corp | Soi基板の製造方法及びこの方法により製造されたsoi基板 |
-
2009
- 2009-02-26 JP JP2009043403A patent/JP5244650B2/ja active Active
-
2010
- 2010-01-08 CN CN2010800086820A patent/CN102326227A/zh active Pending
- 2010-01-08 WO PCT/JP2010/000076 patent/WO2010098007A1/ja not_active Ceased
- 2010-01-08 EP EP10745896.0A patent/EP2402983B1/en active Active
- 2010-01-08 US US13/145,275 patent/US20110281420A1/en not_active Abandoned
- 2010-01-08 KR KR1020117019761A patent/KR20110116036A/ko not_active Ceased
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20150013164A (ko) * | 2012-05-24 | 2015-02-04 | 신에쯔 한도타이 가부시키가이샤 | Soi 웨이퍼의 제조방법 |
| KR20150052041A (ko) * | 2012-09-03 | 2015-05-13 | 신에쯔 한도타이 가부시키가이샤 | Soi 웨이퍼의 제조방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102326227A (zh) | 2012-01-18 |
| JP2010199353A (ja) | 2010-09-09 |
| US20110281420A1 (en) | 2011-11-17 |
| EP2402983A1 (en) | 2012-01-04 |
| EP2402983B1 (en) | 2015-11-25 |
| WO2010098007A1 (ja) | 2010-09-02 |
| JP5244650B2 (ja) | 2013-07-24 |
| EP2402983A4 (en) | 2012-07-25 |
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| PA0105 | International application |
St.27 status event code: A-0-1-A10-A15-nap-PA0105 |
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| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
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| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
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| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
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| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
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| PE0801 | Dismissal of amendment |
St.27 status event code: A-2-2-P10-P12-nap-PE0801 |
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| A201 | Request for examination | ||
| PA0201 | Request for examination |
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| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
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| E13-X000 | Pre-grant limitation requested |
St.27 status event code: A-2-3-E10-E13-lim-X000 |
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| P11-X000 | Amendment of application requested |
St.27 status event code: A-2-2-P10-P11-nap-X000 |
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| P13-X000 | Application amended |
St.27 status event code: A-2-2-P10-P13-nap-X000 |
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| E601 | Decision to refuse application | ||
| PE0601 | Decision on rejection of patent |
St.27 status event code: N-2-6-B10-B15-exm-PE0601 |
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| R18-X000 | Changes to party contact information recorded |
St.27 status event code: A-3-3-R10-R18-oth-X000 |
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| P22-X000 | Classification modified |
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| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |