KR20110114307A - Method for fabricating semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device that can improve alignment error or poor contact when forming a line pattern having a fine line width and spacing and a pad or contact connected to the line pattern. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes increasing overlapping margins of a fine pattern in the form of a line connected to the contact or the pad before forming the contact or the pad in the semiconductor device.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a pattern formation method using a SPT (Spacer Patterning Technology) process.

As the integration of semiconductor devices increases, the size of patterns is reduced. Accordingly, various manufacturing equipment and process methods for forming fine patterns have been proposed. As a representative example, looking at the Rayleigh equation, the size of the fine pattern in the semiconductor device is proportional to the wavelength of light used in the exposure process and inversely proportional to the size of the lens. Therefore, a method of reducing the wavelength of light or increasing the size of the lens used in the exposure process has been mainly used for forming a fine pattern.

This method requires the development of new manufacturing equipment, increases equipment investment costs, and causes difficulties in operating the equipment. Therefore, a double patterning technology for printing a circuit pattern by performing an exposure process for photoresist patterning twice using different masks as a method of forming a fine pattern conforming to high integration even using existing equipment. ) And SPT (Spacer Patterning Technology) method using a spacer as an etching mask for generating a fine pattern has been proposed.

The SPT method forms a predetermined pattern on the etched layer, deposits an insulating layer having a predetermined thickness on the sidewalls and the upper side of the pattern, and then forms a spacer on the sidewall of the insulating layer with a material having a different etching selectivity. Subsequently, the insulating layer interposed between the pattern and the spacer formed in the outer portion is removed, and the lower etching layer is etched using the spacer formed in the pattern and the outer portion as an etching mask. Through this, it is possible to form a pattern having a line width and an interval corresponding to the width of the spacer on the semiconductor substrate. Hereinafter, a dual SPT method will be described in which the SPT method is improved.

1A to 1F are plan views illustrating a method of manufacturing a semiconductor device according to a general dual SPT method.

Referring to FIG. 1A, a first pattern 104 is formed on an etched layer 102 deposited on a semiconductor substrate.

Referring to FIG. 1B, first spacers 106 are formed on sidewalls of the first pattern 104. The first spacer 106 is formed by depositing a material having an etching selectivity different from that of the material constituting the first pattern 104 and then performing an etch-back process.

Referring to FIG. 1C, an insulating film (not shown) is deposited on the first pattern 104 and the first spacer 106, and then the second pattern 108 is formed by performing an etch back process. The second pattern 108 includes a material having an etch selectivity equivalent to the material constituting the first pattern 104. The formation of the second pattern 108 is similar to that of forming the first spacer 106, but there are differences in materials.

Referring to FIG. 1D, a second spacer 110 is formed on sidewalls of the second pattern 108. In this case, the material constituting the second spacer 110 may include a material having an etching selectivity different from that of the material constituting the second pattern 108.

Referring to FIG. 1E, the first pattern 104 and the second pattern 108 except for the first spacer 106 and the second spacer 110 are removed using the difference in the etching selectivity. In addition, by using a separate mask 120, unnecessary portions connecting to one end of the plurality of line patterns 112 are removed.

Referring to FIG. 1F, the exposed etched layer 102 is patterned using the remaining first and second spacers 106 and 110 as an etch mask to form a plurality of line patterns 112.

As described above, a plurality of line patterns 112 having minute line widths and spacings may be formed through the double SPT method. In this case, the line width of the line pattern 112 is the same as the line width of the first and second spacers 106 and 110, and the interval between the line patterns 112 is the line width of the first pattern 104 and the second pattern 108. Determined by Since the second pattern 108 is also formed in the same manner as the first and second spacers 106 and 110, the ratio of the line width and the spacing of the line pattern 112 is 1: 1.

The contact 114 is formed on the pad region formed at the other end of the line pattern 112. In this case, the contact 114 may be formed by partially etching the insulating film (not shown) deposited on the line pattern 112 to form a contact hole (not shown), and then filling the contact hole with a conductive material. have.

FIG. 2 is a plan view illustrating a problem of a semiconductor device formed according to the general dual SPT method described with reference to FIGS. 1A to 1F.

As shown, the above-described dual SPT method enables the formation of fine line patterns 112A and 112B in a semiconductor device, but is electrically connected to the fine pattern because the spacing between the line patterns 112A and 112B is very narrow. Problems may occur when the contact lines 114A and 114B having a large line width are formed.

1E and 1F, the process margin is sufficient to form two contacts 114A connected to the line pattern 112A formed by the second spacer 110 formed on the outside of the second pattern 108. The process margin is insufficient to form two contacts 114B connected to the line pattern 122B formed by the first spacer 106 formed between the second pattern 108 and the first pattern 104. .

Since the aforementioned double SPT method forms the second pattern 108 formed between the two spacers 106 and 110 in the same manner as the spacer forming method, it is impossible to increase or decrease the line width of the second pattern 108. Do. Therefore, when the pad or contact is formed at the end of the line pattern 112, the pad or contact occupies a larger area than the line pattern 112 and is electrically connected to or adjacent to the adjacent line pattern 112. It is more likely to connect. That is, there is a problem in that an additional additional process is required to reduce defects and to reduce process margin in the process for forming the pad or contact due to the lack of overlap margin of the pad or contact with respect to the line pattern.

In order to solve the above problems, the present invention forms a pattern formed on the two spacers in the double SPT method by an exposure process using a mask to sufficiently secure the gap between the two spacers or to form two pads or contacts The present invention provides a method of manufacturing a semiconductor device capable of increasing an overlap margin of a line pattern having a fine line width and a gap and a pad or a contact connected to the line pattern by widening the gap at a predetermined position.

The present invention provides a method of forming a first pattern on an etched layer, forming a first spacer on sidewalls of the first pattern, and forming a second pattern on sidewalls of the first spacer. Forming a second spacer on a sidewall, and etching the first spacer and the second spacer to form a plurality of first spacer patterns and a plurality of second spacer patterns, wherein the plurality of first spacers The first protruding regions of the pattern are formed in opposite directions, and the second protruding regions of the plurality of second spacer patterns are formed in opposite directions.

Preferably, the manufacturing method of the semiconductor device comprises the steps of forming a fine pattern corresponding to the first spacer pattern and the second spacer pattern; And forming pads or contacts on the fine patterns corresponding to the first and second protruding regions.

Preferably, the adjacent first and second protruding regions are formed in opposite directions, or when the first and second protruding regions are formed in the same direction, an interval between the first and second protruding regions is equal to or greater than three times the line width. It is characterized by.

Preferably, the spacing between the fine patterns is the same as the line width of the second pattern, and the spacing between the protrusion patterns in the region where the contact or the pad is formed is the line width of the first or second spacer. It is characterized in that more than three times.

Preferably, the second pattern is formed through a patterning process including an exposure process after depositing an insulating film.

Preferably, the spacing between the fine patterns is the same as the line width of the second pattern, and in the region where the contact or the pad is formed, the fine patterns are formed in opposite directions.

Preferably, when the first pattern is formed, a dummy pattern spaced apart by an arbitrary distance is further formed, and the second pattern is formed by a spacer forming process of etching an etchback process after depositing an insulating film. .

Preferably, the method of manufacturing the semiconductor device further includes separating each of the first spacer and the second spacer into a pair of spacers.

Preferably, the first spacer and the second spacer is characterized in that the etching selectivity is different from the first pattern and the second pattern.

Preferably, the etching selectivity of the first spacer and the second spacer is the same, and the etching selectivity of the first pattern and the second pattern is the same.

Preferably, the first spacer, the second spacer, the first pattern, and the second pattern may include one of an oxide film, a polysilicon film, a carbon film, and a nitride film.

The present invention has the advantage of increasing the overlap margin when forming a pad or contact connected to the fine line pattern in the semiconductor device using the double SPT method. Furthermore, when the present invention is applied to secure overlapping margins even when connecting a plurality of patterns having different line widths and spacing in the semiconductor device, alignment errors or contact defects between components may be improved during the formation of the highly integrated semiconductor device. Can be.

1A to 1F are plan views illustrating a method of manufacturing a semiconductor device according to a general dual SPT method.
FIG. 2 is a plan view illustrating a problem of a semiconductor device formed according to the general dual SPT method described with reference to FIGS. 1A to 1F.
3A to 3G are plan views illustrating a method of manufacturing a semiconductor device in accordance with a dual SPT method according to an embodiment of the present invention.
4A to 4G are plan views illustrating a method of manufacturing a semiconductor device in accordance with a dual SPT method according to another embodiment of the present invention.

In the double patterning method (DPT) using a plurality of spacers, since the pattern formed between the plurality of spacers is not formed by an exposure process, overlapping margins may be increased when connecting another pattern having a large line width to a fine pattern formed by the plurality of spacers. Although the manufacturing process of the semiconductor device is not large, it is difficult. However, in the present invention, a pattern formed between the plurality of spacers is formed by an exposure process using a mask to adjust the spacing between the plurality of spacers in consideration of the overlap margin. In addition, the present invention allows a plurality of spacers to be formed to extend to a position where a pad or a contact is formed by using a mask to which a dummy pattern is added before forming a plurality of spacers without adding a separate exposure process using a mask. A method for manufacturing a semiconductor device is provided. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3G are plan views illustrating a method of manufacturing a semiconductor device in accordance with a dual SPT method according to an embodiment of the present invention.

Referring to FIG. 3A, a first pattern 304 having a line shape is formed on an etched layer 302 deposited on a semiconductor substrate. At the end of the first pattern 304 including the line region 304A and the pad region 304B, a wide line width is formed to secure a space for connecting the pad or the contact, and the first pattern 304 is adjacent to the adjacent first pattern 304. Different lengths are formed.

Referring to FIG. 3B, the first spacer 306 is formed on the sidewall of the first pattern 304. The first spacer 306 may include a material having an etching selectivity different from that of the material constituting the first pattern 304.

Referring to FIG. 3C, after depositing an insulating film (not shown) on the first pattern 304 and the first spacer 306, the line widths of the first pattern 304 and the first spacer 306 may be greater than the sum of the line widths. Patterning is performed using a mask defining a second pattern 308 having a wide line width. Here, the second pattern 308 including the line region 308A and the pad region 308B includes a material having an etching selectivity equivalent to that of the material constituting the first line pattern 308.

In order to secure the overlap margin, the line width of the pad region 308B of the second pattern 308 is greater than the sum of the line widths of the pad region 304B of the first pattern 304 and the first spacer 306. It is formed to be at least three times wider than the line width of 306. On the other hand, the line region 308A of the second pattern 308 is larger than the line width of the first spacer 306 by the line width of the first region 306 and the line region 304A of the first pattern 304. It is formed to have a line width.

Referring to FIG. 3D, a second spacer 310 is formed on sidewalls of the second pattern 308. In this case, the material constituting the second spacer 310 may include a material having an etching selectivity different from that of the material constituting the second pattern 308.

Referring to FIG. 3E, the first pattern 304 and the second pattern 308 except for the first spacer 306 and the second spacer 310 are removed using the difference in the etching selectivity.

Referring to FIG. 3F, portions of the first and second spacers 306 and 310 are removed in the region where the pad or contact is to be formed. By performing an etching process using the mask 420, each of the first and second spacers 306 and 310 is divided into a pair of spacers 306A, 306B, 310A, and 310B. At this time, protruding regions in directions facing each other are formed at ends of the paired spacers 306A and 306B or 310A and 310B. Protruding regions of neighboring spacers 306A and 310B, or 306B and 310A, are formed in the same direction as each other.

Referring to FIG. 3G, the exposed etched layer 302 is patterned using the remaining first and second spacers 306A, 306B, 310A, and 310B as an etch mask to form a plurality of line patterns 312A and 312B. In addition, the contact / pads 314A and 314B are formed at one end of the plurality of line patterns 312 using a mask defining the position of the contact or pad. Unlike the related art, in the present invention, the line patterns 312A and 312B connected to the contacts / pads 314A and 314B are sufficiently spaced apart from each other to increase the overlap margin of the contacts / pads 314A and 314B. The distance between the line pattern 312B formed by the second spacer 310 and the line pattern 312A formed by the first spacer 306 is widened by three times or more of the line width of the first spacer 306, thereby making contact / It is easy to connect the pads 314A and 314B with different line patterns 312A and 312B without colliding with each other.

As described above, in one embodiment of the present invention by performing an exposure process using a mask during the formation of the second pattern 308 formed after the formation of the first spacer 306 and before the formation of the second spacer 310. In the region where the contact or pad is formed, the gap between the first spacer 306 and the second spacer 310 may be sufficiently widened. As a result, when forming the contacts / pads 314A and 314B in the future, the overlap margin can be secured sufficiently stably to suppress the occurrence of defects in the semiconductor device.

However, the manufacturing method of the semiconductor device described above has a disadvantage in that the manufacturing cost of the semiconductor device increases because a mask must be additionally manufactured due to an exposure process for forming the second pattern 308. Hereinafter, another embodiment of the present invention, which can secure sufficient overlap margin when forming a contact or pad without performing an exposure process using a separate mask, will be described.

4A to 4G are plan views illustrating a method of manufacturing a semiconductor device in accordance with a dual SPT method according to another embodiment of the present invention.

Referring to FIG. 4A, a first pattern 404 having a line shape is formed on an etched layer 402 deposited on a semiconductor substrate. At the end of the first pattern 404 including the line region 404A and the pad region 404B, a wide line width is formed to secure a space for connecting a pad or a contact, and the first pattern 404 is adjacent to the neighboring first pattern 404. Different lengths are formed. In addition, a dummy pattern 450 is further formed for each pad region 404B of the first pattern 404. Here, the interval between the pad region 404B of the first pattern 404 and the dummy pattern 450 is three times the line width of the spacer formed in the subsequent process.

Referring to FIG. 4B, first spacers 406 are formed on sidewalls of the first pattern 404 and the dummy pattern 450. The first spacer 406 may include a material having an etching selectivity different from that of the material constituting the first pattern 404. Although the distance between the pad region 404B of the first pattern 404 and the dummy pattern 450 was three times the line width of the spacer, the pad region 404B of the first pattern 404 after the first spacer 406 was formed. ) And the dummy pattern 450 remain only as wide as the line width of the spacer.

Referring to FIG. 4C, an insulating film (not shown) is deposited on the first pattern 404, the dummy pattern 450, and the first spacer 406, and then an etch back process is performed to form the second pattern 408. Here, the second pattern 408 includes a material having an etching selectivity equivalent to the material constituting the first pattern 104. As in the related art, the formation of the second pattern 408 is similar to that of forming the first spacer 406, and there is no need to perform an exposure process using a separate mask. However, after the formation of the second pattern 408, the space between the pad region 404B and the dummy pattern 450 of the first pattern 404 is due to the first spacer 406 and the second pattern 408. Not left.

Referring to FIG. 4D, a second spacer 410 is formed on sidewalls of the second pattern 408. In this case, the material constituting the second spacer 410 includes a material having an etching selectivity different from that of the material constituting the second pattern 408. Since there is no empty space between the pad region 404B of the first pattern 404 and the dummy pattern 450, the second spacer 410 may not be formed.

Referring to FIG. 4E, the first pattern 404 and the second pattern 408 except for the first spacer 406 and the second spacer 410 are removed using the difference in the etching selectivity. In addition, a portion of the first and second spacers 406 and 410 are removed in the area where the pad or contact is to be formed. By performing an etching process using the mask 420, each of the first and second spacers 406 and 410 is divided into a pair of spacers 406A, 406B, 410A, and 410B. In this case, protruding regions in the directions facing each other are formed at the end portions of the pair of spacers 406A and 406B separated from the first spacer 406, and the pair of spacers 410A and the second spacer 410 separated from each other. Protruding regions in opposite directions are formed at the ends of 410B, while protruding regions of neighboring spacers 406A and 410A, or 406B and 410B are formed in opposite directions.

Referring to FIG. 4F, a plurality of line patterns 412A and 412B are formed by patterning the exposed etching target layer 402 by using the remaining first and second spacers 406A, 406B, 410A, and 410B as etching masks. In addition, the contact / pads 414A and 414B are formed at one end of the plurality of line patterns 412A and 412B using a mask defining a contact or pad location. Here, since the line patterns 412A and 412B connected to the contacts / pads 414A and 414B are formed to be sufficiently spaced apart from each other due to the dummy pattern 450, the overlap margins of the contacts / pads 414A and 414B are increased. . Specifically, ends of the line pattern 412B formed by the second spacer 410 and the line pattern 412A formed by the first spacer 406 are formed in opposite directions. Accordingly, it is easy to connect the contacts / pads 414A and 414B with different line patterns 412A and 412B without colliding with each other.

As described above, in the present invention, when forming a pad or contact having a large line width connected to a line pattern formed at a fine line width and an interval, the overlap margin is increased by performing an exposure process using a separate mask or forming a dummy pattern. Provided are a method of manufacturing a semiconductor device. The shape of the line pattern formed by using an exposure process or a dummy pattern using a separate mask may vary according to the shape of the mask or dummy pattern, and when properly disposed in an area where a pad or a contact is formed, the overlapping margin may be maximized. Can be. Due to the increase in the overlap margin, problems such as misalignment or interference and electrical shorts that may occur when pads or contacts are formed in the semiconductor device may be solved.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (11)

Forming a first pattern on the etched layer;
Forming a first spacer on sidewalls of the first pattern;
Forming a second pattern on sidewalls of the first spacer;
Forming a second spacer on sidewalls of the second pattern; And
Etching the first spacer and the second spacer to form a plurality of first spacer patterns and a plurality of second spacer patterns,
The first protruding regions of the plurality of first spacer patterns are formed in opposite directions, and the second protruding regions of the plurality of second spacer patterns are formed in opposite directions. The method of claim 1,
Forming a fine pattern in correspondence with the first spacer pattern and the second spacer pattern; And
And forming pads or contacts on the fine patterns corresponding to the first and second protruding regions. The method of claim 1,
The adjacent first and second protruding regions are formed in opposite directions, or when the first and second protruding regions are formed in the same direction, an interval between the first and second protruding regions is equal to or greater than three times the line width. The manufacturing method of the semiconductor element. The method of claim 2,
The spacing between the fine patterns is the same as the line width of the second pattern, and the spacing between the protruding patterns in a region where the contact or the pad is formed is at least three times the line width of the first or second spacer. The manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 4, wherein
And the second pattern is formed through a patterning process including an exposure process after depositing an insulating film. The method of claim 3, wherein
The spacing between the fine patterns is the same as the line width of the second pattern, and in the region where the contact or the pad is formed, the fine pattern is formed in a direction opposite to each other. The method according to claim 6,
When the first pattern is formed, a dummy pattern spaced apart by an arbitrary distance is further formed, and the second pattern is formed by a spacer forming process of etching an etchback process after depositing an insulating film. Way. The method of claim 3, wherein
And separating each of the first spacer and the second spacer into a pair of spacers. The method of claim 3, wherein
The first spacer and the second spacer is a semiconductor device manufacturing method, characterized in that the etching selectivity is different from the first pattern and the second pattern. The method of claim 9,
The etching selectivity of the first spacer and the second spacer is the same, and the etching selectivity of the first pattern and the second pattern is the same. The method of claim 9,
And the first spacer, the second spacer, the first pattern, and the second pattern include one of an oxide film, a polysilicon film, a carbon film, and a nitride film.

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