KR20110111981A - Semiconductor light emitting device and fabrication method thereof - Google Patents

Abstract

The embodiment relates to a semiconductor light emitting device and a method of manufacturing the same.
In an embodiment, a semiconductor light emitting device may include a first semiconductor layer including a plurality of rods; An air gap portion between the rods of the first semiconductor layer; A substrate including at least one hole connected to the rod and the air gap portion under the first semiconductor layer; And a plurality of compound semiconductor layers formed on the first semiconductor layer.

Description

Semiconductor light emitting device and method of manufacturing the same {Semiconductor light emitting device and fabrication method

The embodiment relates to a semiconductor light emitting device and a method of manufacturing the same.

Group III-V nitride semiconductors are spotlighted as core materials of light emitting devices such as light emitting diodes (LEDs) or laser diodes (LDs) due to their physical and chemical properties. The III-V nitride semiconductor is usually made of a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

A light emitting diode (LED) is a kind of semiconductor device that transmits and receives a signal by converting electricity into infrared light or light using characteristics of a compound semiconductor.

 It is widely used as a light emitting device for obtaining light of an LED or LD (Laser Diode) using such a nitride semiconductor material, and is applied as a light source of a product such as a keypad light emitting part of a terminal, an electric signboard, a lighting device, and the like.

The embodiment provides a semiconductor light emitting device having a photonic crystal structure capable of reducing crystal defects of a semiconductor layer and improving light extraction effects, and a method of manufacturing the same.

The embodiment provides a semiconductor light emitting device including a plurality of rods and / or air gaps under a first semiconductor layer and a method of manufacturing the same.

The embodiment provides a semiconductor light emitting device and a method of manufacturing the same, wherein the mask layer between the substrate and the first semiconductor layer is exposed and then the mask layer is removed to form an air gap portion corresponding to the size of the mask layer. do.

The embodiment provides a semiconductor light emitting device and a method of manufacturing the same, in which a plurality of rods and air gaps are disposed under a first semiconductor layer so that the growth substrate can be easily removed.

According to an embodiment, a semiconductor light emitting device may include a first semiconductor layer including a plurality of rods below; An air gap portion between the rods of the first semiconductor layer; A substrate including at least one hole connected to the rod and the air gap portion under the first semiconductor layer; And a plurality of compound semiconductor layers formed on the first semiconductor layer.

A method of manufacturing a semiconductor light emitting device according to the embodiment includes forming a mask layer having a plurality of rod holes on a substrate; Forming a plurality of rods using the Group III-V compound semiconductor through the plurality of rod holes; Removing the mask layer to form an air gap portion; And forming a first semiconductor layer on the plurality of rods.

A method of manufacturing a semiconductor light emitting device according to the embodiment includes forming a mask layer having a plurality of rod holes on a substrate; Forming a light emitting structure including a first semiconductor layer through the plurality of rod holes; Forming a hole through a lower surface of the substrate to expose the mask layer; Removing the mask layer to form a plurality of rod and air gap portions under the first semiconductor layer.

The embodiment can improve light extraction efficiency.

The embodiment can reduce defects due to epitaxial growth.

The embodiment can improve light extraction efficiency by using a photonic crystal structure.

Embodiments may use hybrid photonic crystals to reduce crystal defects due to epitaxial growth and to improve light extraction efficiency.

The embodiment can improve the reliability of the semiconductor light emitting device.

The embodiment can minimize damage to the semiconductor crystal structure by the LLO method.

1 to 7 illustrate a process of manufacturing a semiconductor light emitting device according to the first embodiment.
FIG. 8 is a horizontal semiconductor light emitting device using FIG. 6.
9 to 15 illustrate a process of fabricating a semiconductor light emitting device according to the second embodiment.
FIG. 16 is a view illustrating a horizontal semiconductor light emitting device using FIG. 15.
FIG. 17 illustrates a vertical semiconductor light emitting device using FIG. 15.
FIG. 18 illustrates a vertical semiconductor light emitting device using FIG. 15.
19 and 20 illustrate a process of fabricating a semiconductor light emitting device according to a third embodiment.
21 is a side cross-sectional view showing a light emitting device package according to the embodiment.

In the description of an embodiment, each layer (film), region, pattern or structure is formed to be "on" or "under" the substrate, each layer (film), region, pad or pattern. In the case described, "on" and "under" include both the meanings of "directly" and "indirectly". In addition, the criteria for the top or bottom of each layer will be described with reference to the drawings.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

1 to 7 illustrate a process of manufacturing a semiconductor light emitting device according to the first embodiment.

1 and 2, a mask layer 113A is formed on the substrate 110. The substrate 110 may use at least one of sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, Ge. Here, after forming a buffer layer (not shown) on the substrate 110, the mask layer 113A may be formed on the buffer layer (not shown).

The mask layer 113A may be formed of a material such as SiO ₂ , SiO _x , SiN _x , SiO _x N _y , W, or the like to a predetermined thickness, for example, 20 μm or less. The additive mask layer 113A is deposited by a plasma enhanced chemical vapor deposition (PECVD) or a sputtering method.

After the mask pattern is disposed on the mask layer 113A, a plurality of rod holes 114 are formed by patterning the same by an etching method such as photolithography.

The rod hole 114 may be formed in a columnar shape, for example, a circular columnar shape or a polygonal columnar shape, but is not limited thereto. An upper surface of the substrate may be exposed through the mask layer 113A in the rod hole 114. The etching method may use a dry etching method, but is not limited thereto.

The rod hole 114 may be formed in a mesh shape that is arranged in a row / column direction at regular or irregular intervals, and this shape may be changed by the mask pattern.

2 and 3, a plurality of rods 115 using group III-V compound semiconductors are formed in the rod holes 114 between the mask layers 113A. The tops will grow to a thickness that does not seal together. The rod 115 stops growing in a state where the width W2 of the upper portion is larger than the width W1 of the lower portion, and is formed in a form that is not sealed with other rods. As shown in the plan view of FIG. 4, the plurality of rods 115 have a predetermined gap 116 with a partial region between adjacent rods 116, and the upper end of the mask layer 113A Exposed.

The rod 115 may include an undoped semiconductor layer or a semiconductor layer doped with a first conductive dopant, and the first conductive dopant may include an N-type dopant.

3 and 5, the mask layer 113A is removed through the gap 116 using a wet etching solution. The wet etching is performed for a predetermined time using a solution capable of etching the mask layer 113A (eg, HF or / and NH ₄ F, etc.), and thus the mask layer 113A is shown in FIG. 5. Completely removed.

An air gap portion 113 is formed in the region where the mask layer 113A is removed, and the air gap portions 113 are connected to each other. Accordingly, the air gap 113 and the plurality of rods 115 are formed on the substrate 111.

The gaps 116 between the plurality of rods 115 may be formed at intervals of 5 μm or less or at intervals in which semiconductor materials are not grown through the air gap portion 113.

The first semiconductor layer 121 using the group III-V group compound semiconductor on the plurality of rods 115, the active layer 123 on the first semiconductor layer 121, and the second conductive semiconductor on the active layer 123. Layer 125 may be formed.

The first semiconductor layer 121 may be formed in a single layer structure or a multilayer structure on the plurality of rods 115. The single layer structure may be formed of a first conductive semiconductor layer, and the multilayer structure may include a structure in which an undoped semiconductor layer is formed in a lower layer and a first conductive semiconductor layer is formed in an upper layer.

The Group III-V compound semiconductor includes, for example, a semiconductor such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. The first conductive dopant may be doped into the Group III-V compound semiconductor. When the first conductive semiconductor layer is an N-type semiconductor layer, the first conductive dopant is an N-type dopant and includes Si, Ge, Sn, Se, and Te.

The growth equipment of the Group III-V group nitride semiconductors includes electron beam evaporators, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), and dual-type thermal evaporator sputtering. ), Metal organic chemical vapor deposition (MOCVD), and the like, but is not limited thereto.

After the first semiconductor layer 121 is grown from the plurality of rods 115, the first semiconductor layer 121 is grown so as to further promote horizontal growth on the air gap 113 and is sealed with each other. The upper surface of the first semiconductor layer 121 may be flattened.

When the first semiconductor layer 121 and the plurality of rods 115 are GaN, they may be formed by CVD (or MOCVD). For example, a group gas such as trimethylgallium (TMGa) or triethylgallium (TEGa) is used for the source gas for Ga, and ammonia (NH ₃ ), monomethylhydrazine (MMHy) or Group 5 gases such as dimethylhydrazine (DMHy) can be used.

The first semiconductor layer 121 may be grown by controlling growth conditions such as a growth temperature, a ratio of a Group 5 gas to a Group 3 gas, and a growth pressure. In this case, the first semiconductor layer 121 is grown from the plurality of rods 115 at the initial stage of growth (vertical growth promoting condition), and the gap 116A region of the air gap portion 113 as the growth time passes. Are grown and sealed together (horizontal growth promoting conditions). When the first semiconductor layer 121 is grown, a first conductive dopant may be added.

The vertical growth promoting condition increases the pressure, lowers the growth temperature, and the Ga flow rate allows vertical growth using a number of conditions selectively. In addition, the horizontal growth promoting conditions may be grown by controlling the vertical growth conditions in the opposite direction, such as gradually increasing the growth temperature of the vertical growth promoting conditions. These growth conditions can be adjusted within the technical scope of the embodiment.

Since the first semiconductor layer 121 is disposed on the air gap 113, defects in the first semiconductor layer 121 may be minimized. That is, defects due to lattice mismatch with the substrate 110 can be reduced.

The active layer 123 may be formed of a single quantum well structure, a quantum line structure, a quantum dot structure, or a multi-quantum well structure, and may emit light of visible light such as light of blue wavelength, light of red wavelength, and light of green wavelength. It may include a material that emits light. In the quantum well structure, a well layer and a barrier layer may be formed periodically, and the well layer may be formed with a band gap lower than that of the barrier layer. A conductive cladding layer may be formed on or under the active layer 123, and the conductive cladding layer may be formed of an AlGaN-based semiconductor.

The second conductive semiconductor layer 125 may be formed of semiconductors doped with a second conductive dopant, for example, compound semiconductors such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, or the like. It can be made of either. When the second conductive semiconductor layer 125 is a P-type semiconductor layer, the second conductive dopant may be a P-type dopant, and at least one of Mg, Zn, Ca, Sr, and Ba may be added.

The semiconductor light emitting device 100 may be selectively formed on the second conductive semiconductor layer 125 from a transparent electrode layer (not shown), a reflective electrode layer (not shown), and a first electrode (not shown). The transparent electrode layer may be formed by selecting from materials of ITO, ZnO, IrOx, RuOx, NiO. The reflective electrode layer may optionally include Al, Ag, Pd, Rh, Pt, Ir, and the like.

When the first semiconductor layer 121 includes a P-type semiconductor layer, the second conductive semiconductor layer 125 may be implemented as an N-type semiconductor layer. In addition, an N-type semiconductor layer or a P-type semiconductor layer may be formed on the second conductive semiconductor layer 125. Accordingly, the light emitting structure may be implemented as any one of an N-P junction structure, a P-N junction structure, an N-P-N junction structure, and a P-N-P junction structure.

 6 and 7, the light emitting structures 121, 123, and 125 are disposed on the substrate 111 in a shape spaced apart from each other by the rods 115 to reduce defects due to epitaxial growth and to extract light. It can be improved.

The refractive index of the first semiconductor layer 121 is 2.12 to 2.44, and the refractive index of the air gap 113 is 1. Due to the difference in refractive index, the first semiconductor layer 121 and the air gap 113 may change the critical angle of the traveling light, thereby improving the light extraction effect. The air gap 113 may improve the light extraction effect by providing a two-dimensional photonic crystal structure under the first semiconductor layer 121.

8 is a side cross-sectional view illustrating a horizontal semiconductor light emitting device using FIG. 6.

Referring to FIG. 8, the semiconductor light emitting device 100A exposes the first semiconductor layer 121 and forms a first electrode 131 through mesa etching, and a second electrode on the second conductive semiconductor layer 125. 133 may be formed.

Here, a transparent electrode layer or roughness structure may be disposed on the second conductive semiconductor layer 125 or on the second electrode 133 as a light extracting material or a current spreading material.

9 to 15 illustrate a process of fabricating a semiconductor light emitting device according to the second embodiment. In the description of the second embodiment, the same parts as in the first embodiment are referred to the first embodiment, and redundant description will be briefly described.

9 and 10, a mask layer 153A is formed on the substrate 151. The substrate 151 may use at least one of sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, Si, GaP, InP, and Ge.

The mask layer 153A may be formed of a material such as SiO ₂ , SiO _x , SiN _x , SiO _x N _y , W, or the like to a predetermined thickness, for example, 20 μm or less. The additive mask layer 153A is deposited by plasma enhanced chemical vapor deposition (PECVD) or a sputtering method.

After the mask pattern is disposed on the mask layer 153A, a plurality of rod holes 154 are formed by patterning the same by an etching method such as photolithography.

The rod hole 154 may be formed in a columnar shape, for example, a circular columnar shape or a polygonal columnar shape, but is not limited thereto. An upper surface of the substrate may be exposed through the mask layer 153A in the rod hole 154. The etching method may use a dry etching method, but is not limited thereto.

The rod hole 154 may be formed in a mesh shape that is arranged in a row / column direction at regular or irregular intervals, and this shape may be changed by the mask pattern.

Referring to FIG. 11, a plurality of rods 155 using group III-V compound semiconductors are formed in the rod holes 154 between the mask layers 153A, and the rods 155 have upper ends of each other. It is encapsulated and grown to form the first semiconductor layer 161.

The first semiconductor layer 161 using the group III-V compound semiconductor on the plurality of rods 155, the active layer 163 on the first semiconductor layer 161, and the second conductive semiconductor on the active layer 163. Layer 165 may be formed sequentially.

The first semiconductor layer 161 may be formed of the same material or different materials as those of the plurality of rods 155. The plurality of rods 155 may be formed of an undoped semiconductor or a conductive semiconductor using a group III-V compound semiconductor. The first semiconductor layer 161 may be formed of a first conductive semiconductor layer.

The Group III-V compound semiconductors include, for example, semiconductors such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, and the like. When the first semiconductor layer 161 is an N-type semiconductor layer, the first conductive dopant is an N-type dopant and includes Si, Ge, Sn, Se, and Te.

After the first semiconductor layer 161 is grown from the plurality of rods 155, the first semiconductor layer 161 may be sealed on the mask layer 153A, and an upper surface thereof may be flattened. The first semiconductor layer 161 may be grown by controlling growth conditions such as a growth temperature, a ratio of a Group 5 gas to a Group 3 gas, and a growth pressure. These growth conditions can be adjusted within the technical scope of the embodiment.

Since the first semiconductor layer 161 is disposed on the mask layer 153A, defects in the first semiconductor layer 161 may be minimized. That is, defects due to lattice mismatch with the substrate 151 can be reduced.

An active layer 163 and the second conductive semiconductor layer 165 are formed on the first semiconductor layer 161. The first semiconductor layer 161, the active layer 163, and the second conductive semiconductor layer 165 may be defined as a light emitting structure 160. In addition, the light emitting structure 160 may have an N-type semiconductor layer stacked on the second conductive semiconductor layer 125. For a description of the light emitting structure and the material layer stacked thereon, see the first embodiment. Shall be.

A hole 151A penetrates through the bottom of the substrate 151 to an upper surface thereof. The hole 151A is a passage that exposes the mask layer 153A, and may be formed in a plurality of holes as shown in FIG. 12, or may be formed in a polygonal or circular shape as in the hole 151B of FIG. 13. That is, the hole 151B may be formed in an open loop shape or a closed loop shape. Such a hole shape may be variously changed within the technical scope of the embodiment.

14 and 15, the chip boundary region D1 is etched to expose the edge portion B1 of the mask layer 153A.

The mask layer 153A is wet-etched through the holes 151A and the chip boundary region of the substrate 151 to remove the mask layer 153A. The wet etching is performed for a predetermined time using a solution capable of etching the mask layer 153A (eg, HF or / and NH ₄ F, etc.), and thus the mask layer 153A is shown in FIG. 15. Completely removed.

An air gap portion 153 is formed in a region where the mask layer 153A is removed, and the air gap portions 153 are connected to each other. Accordingly, the air gap portion 153 and the plurality of rods 155 are disposed between the substrate 151 and the first semiconductor layer 161.

In the semiconductor light emitting device 101, light emitting structures 161, 163, and 165 are grown on the substrate 151 through the rod 155, thereby reducing defects due to epitaxial growth and improving light extraction effects.

The light extraction effect can be improved by changing the critical angle of the light propagated by the difference in the refractive index of the first semiconductor layer 161 and the refractive index of the air gap portion 153. The air gap part 153 may improve light extraction by providing a two-dimensional photonic crystal structure under the first semiconductor layer 161.

FIG. 16 is a side cross-sectional view illustrating a horizontal semiconductor light emitting device using FIG. 15.

Referring to FIG. 16, the semiconductor light emitting device 101A exposes the first semiconductor layer 161 through mesa etching to form a first electrode 131, and a second electrode on the second conductive semiconductor layer 165. 133 may be formed.

Here, a transparent electrode layer or a roughness structure may be disposed on the second conductive semiconductor layer 165 or on the second electrode 133 as a light extracting material or a current spreading material, but is not limited thereto.

17 is a side cross-sectional view illustrating a vertical semiconductor light emitting device using FIG. 15.

Referring to FIG. 17, the semiconductor light emitting device 102 forms the first electrode 131A through the bottom surface of the substrate 151 and the hole 151A. The first electrode 131A is formed in the plurality of rods and / or the air gap regions through the holes 151A of the substrate 151, and thus may be electrically connected to the bottom of the first semiconductor layer 161. . Accordingly, the first semiconductor layer 161 is supplied with power through the lower portion of the substrate, and the power supply structure may vary depending on the shape and structure of the hole 151A of the substrate 151.

17 is a side cross-sectional view illustrating a vertical semiconductor light emitting device using FIG. 15.

Referring to FIG. 17, the semiconductor light emitting device 102 forms the first electrode 131A through the bottom surface of the substrate 151 and the hole 151A. The first electrode 131A is formed in the plurality of rods and / or the air gap regions through the holes 151A of the substrate 151, and thus may be electrically connected to the bottom of the first semiconductor layer 161. . Accordingly, the first semiconductor layer 161 is supplied with power through the lower portion of the substrate, and the power supply structure may vary depending on the shape and structure of the hole 151A of the substrate 151.

FIG. 18 is a diagram illustrating another example of the vertical semiconductor light emitting device of FIG. 15.

15 and 18, the semiconductor light emitting device 103 forms the second electrode layer 133A on the second conductive semiconductor layer 165 of FIG. 15. The second electrode layer 133A may be formed of at least one layer using a reflective electrode layer, a conductive support member, or the like.

The reflective electrode layer may optionally include Al, Ag, Pd, Rh, Pt, Ir, and the like, and the conductive support member 156 may be copper (Cu-copper), gold (Au-gold), or nickel (Ni-nickel). , Molybdenum (Mo), copper-tungsten (Cu-W), carrier wafers (eg, Si, Ge, GaAs, ZnO, SiC, etc.) may be optionally included.

After removing the substrate 151 of FIG. 15 under the first semiconductor layer 161, the first electrode 131B is formed under the first semiconductor layer 161. The removal method of the substrate 151 of FIG. 15 may be removed by a laser lift off (LLO) method.

Here, when the substrate is removed, the substrate 151 of FIG. 15 is separated from the rod 155 of the first semiconductor layer 161, so that the gas between the rods is discharged to the outside through the air, Crack defects due to expansion coefficient differences can be minimized to propagate inside the semiconductor layer, thereby improving device yield and reliability. That is, the rod 155 of the first semiconductor layer 161 may reduce the damage of the semiconductor layer crystal structure by the LLO method.

In addition, when the substrate is removed, when the rod size of the first semiconductor layer 161 has a relatively narrow diameter, the wet etching rate of the lower rod of the first semiconductor layer 161 may be relatively fast and stable. LLO schemes can be provided.

An inductively coupled plasma / reactive ion etching (ICP / RIE) process may be performed on the bottom surface of the first semiconductor layer 161 from which the substrate is removed, but is not limited thereto. In this case, part of the rod 155 may be removed.

The first electrode 131B may be formed before or after chip separation, but is not limited thereto. The rod 155 may be removed from a surface under the first semiconductor layer 161 to form a conductive semiconductor having a simple flat layer or an uneven pattern. These features can be changed within the technical scope of the embodiment.

The semiconductor light emitting device 103 is separated by a chip unit by using an expanding and breaking process after etching the mesa. The embodiment has described a semiconductor light emitting device, for example, an LED, as an example, but can be applied to other semiconductor devices that can be formed on the substrate, and the technical features are not limited to the above embodiments.

The first electrode 131B may directly contact the plurality of rods 155 and the first semiconductor layer 153A. In this case, since the plurality of rods 115 operate in a roughness under the first semiconductor layer 161, the light extraction effect may be improved.

19 and 20 illustrate a process of fabricating a semiconductor light emitting device according to a third embodiment. In the description of the third embodiment, the same parts as in the second embodiment are referred to the second embodiment, and redundant description thereof will be briefly described.

Referring to FIG. 19, the semiconductor light emitting device 104 has a structure in which a mask layer 153A is formed after a third semiconductor layer 170 is formed on a substrate 151. The third semiconductor layer 170 may be formed to a predetermined thickness using a group 2 to group 6 compound semiconductor, and may include, for example, a ZnO layer, a buffer layer, an undoped semiconductor layer, and the like. Since the process after the formation of the third semiconductor layer 170 is the same as in the second embodiment, a detailed description thereof will be omitted.

19 and 20, when the hole 151 is formed in the substrate 151, the semiconductor light emitting device 104 is formed to remove the third semiconductor layer 170, and the mask layer ( After exposing 153A, the mask layer 153A may be removed by wet etching. In this case, the third semiconductor layer 170 between the mask layer 153A and the substrate 151 may be removed and may remain, but is not limited thereto.

The substrate 151 may be separated by wet etching the region of the air gap portion 153 and the plurality of rods 155 from which the mask layer 153A has been removed or by removing the region by a laser lift-off method. In this case, the substrate 151 is separated together with the third semiconductor layer 170.

21 is a cross-sectional view of a light emitting device package including a light emitting device according to the embodiment.

Referring to FIG. 21, the light emitting device package 30 according to the embodiment includes a body 31, a first lead electrode 32 and a second lead electrode 33 installed on the body 31, and the body ( 31, the light emitting device 100A according to the embodiment (s) electrically connected to the first lead electrode 32 and the second lead electrode 3, and surrounding the light emitting device 100A. The molding member 37 is included.

The body 31 may include a silicon material, a synthetic resin material, or a metal material, and an inclined surface may be formed around the light emitting device 100A.

The first lead electrode 32 and the second lead electrode 33 are electrically separated from each other, and provide power to the light emitting device 100A. In addition, the first lead electrode 32 and the second lead electrode 33 may increase light efficiency by reflecting light generated by the light emitting device 100A, and heat generated by the light emitting device 100A. It may also play a role in discharging it to the outside.

The light emitting device 100A may be installed on the body 31 or on the first lead electrode 32 or the second lead electrode 33.

The light emitting device 100A may be electrically connected to the first lead electrode 32 and the second lead electrode 33 by a wire 36, a flip chip method, or a die bonding method. .

The molding member 37 may surround the light emitting device 100A to protect the light emitting device 100A. In addition, the molding member 37 may include a phosphor to change the wavelength of light emitted from the light emitting device 100A. The phosphor may be coated on the light emitting device 100A, added to the molding member 37, or disposed in a predetermined spaced form.

The light emitting device according to the embodiment (s) may be packaged in a semiconductor substrate such as a resin material or silicon, an insulating substrate, a ceramic substrate, or the like, and may be used as a light source such as an indicator device, a lighting device, or a display device. In addition, each embodiment is not limited to each embodiment, it can be selectively applied to other embodiments disclosed above, but is not limited to each embodiment.

The light emitting device or the light emitting device package according to the embodiment (s) may be configured as a light emitting module by being arranged in one or a plurality of units on a substrate, and the light emitting module may be an indicator device (for example, a traffic light) or an illumination device (for example It can be used as a light source or a unit such as a lighting lamp, a headlamp, a street lamp, a fluorescent lamp), or a display device (eg, an LCD panel). The light output path of the light emitting module may include a light guide plate for surface light, a reflecting plate for reflecting light, an optical sheet such as a diffusion sheet or a prism sheet for controlling the diffusion or polarization of light, and the like, but are not limited thereto. Each embodiment is not limited to each embodiment, but may be selectively applied to other embodiments disclosed above, but is not limited to each embodiment.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

Although the above description has been made based on the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains may not have been exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

101, 101A, 102, 103: semiconductor light emitting element, 110: substrate, 113A: mask layer, 114: rod hole, 115: rod, 113A: air gap portion, 116: gap, 121,161: first semiconductor layer, 123,163: active layer, 125,165: agent 2 conductive semiconductor layer, 151: substrate

Claims (18)

A first semiconductor layer including a plurality of rods below;
An air gap portion between the rods of the first semiconductor layer;
A substrate including at least one hole connected to the rod and the air gap portion under the first semiconductor layer; And
A semiconductor light emitting device comprising a plurality of compound semiconductor layers formed on the first semiconductor layer. The semiconductor light emitting device of claim 1, further comprising at least one second semiconductor layer including a group 2 to 6 compound semiconductor under the rod of the first semiconductor layer. The semiconductor light emitting device of claim 1, further comprising a first electrode formed in a hole of the substrate and a rod of the first semiconductor layer inside the hole. The semiconductor light emitting device of claim 1, wherein the first semiconductor layer comprises at least one of an undoped semiconductor layer including a Group III-V compound semiconductor and a first conductive semiconductor layer. device. The semiconductor light emitting device of claim 1, wherein the hole of the substrate penetrates from the lower surface of the substrate to the upper surface of the substrate, the shape of which is formed in a plurality of hole shapes, an open loop shape, or a closed loop shape. device. The semiconductor light emitting device of claim 5, wherein the air gap portion is connected to each other between the rods of the first semiconductor layer. The semiconductor light emitting device of claim 1, wherein the rod comprises a columnar shape or a horn shape, and the plurality of rods are arranged at regular or irregular intervals. The semiconductor light emitting device of claim 1, further comprising an uneven pattern formed on at least one of a lower surface of the first semiconductor layer and an upper surface of the substrate. The semiconductor light emitting device of claim 1, wherein the plurality of compound semiconductor layers comprises an active layer and a second conductive semiconductor layer formed on the active layer. The semiconductor light emitting device of claim 9, further comprising at least one of a second electrode, a reflective electrode layer, a transparent electrode layer, and an N-type semiconductor layer formed on the second conductive semiconductor layer. Forming a mask layer having a plurality of rod holes on the substrate;
Forming a plurality of rods using the Group III-V compound semiconductor through the plurality of rod holes;
Removing the mask layer to form an air gap portion; And
And forming a first semiconductor layer on the plurality of rods. Forming a mask layer having a plurality of rod holes on the substrate;
Forming a light emitting structure including a first semiconductor layer through the plurality of rod holes;
Forming a hole through a lower surface of the substrate to expose the mask layer;
Removing the mask layer to form a plurality of rod and air gap portions under the first semiconductor layer. The method of claim 12, wherein the exposing the mask layer comprises exposing the mask layer by etching a chip boundary region after forming the light emitting structure. The method of claim 11, wherein the rod hole comprises at least one of a columnar shape, a horn shape, and a horn shape. The method according to claim 11 or 12, wherein a second semiconductor layer is formed on the substrate, and then the mask layer is formed. The method of claim 15, wherein the first semiconductor layer comprises an undoped semiconductor or a semiconductor doped with a first conductive dopant. The method of claim 12, further comprising forming a first electrode under the first semiconductor layer through the hole in the lower portion of the substrate and the hole. 13. The method of claim 11 or 12, further comprising: removing the substrate by wet etching through an air gap portion of the first semiconductor layer; And forming a first electrode on the plurality of rods.

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