KR20110108219A - Three dimensional semiconductor memory device and method of fabricating the same - Google Patents

Abstract

A three-dimensional semiconductor device and a method of manufacturing the same are provided. The device includes a conductive structure disposed on a substrate, including conductive patterns stacked in turn, a semiconductor pattern penetrating through the conductive structure and inserted into an upper surface of the substrate, and an insulating film structure interposed between the semiconductor pattern and the conductive structure. do. In addition, the semiconductor pattern extends horizontally under the insulating film structure to directly contact the sidewalls of the substrate.

Description

Three-dimensional semiconductor device and its manufacturing method {Three Dimensional Semiconductor Memory Device And Method Of Fabricating The Same}

The present invention relates to a semiconductor device, and more particularly, to a three-dimensional memory semiconductor device including three-dimensionally arranged memory cells.

3D-IC memory technology is a technology for increasing memory capacity, and refers to various technologies related to three-dimensionally arranging memory cells. In addition to the 3D-IC memory technology, memory capacity can be increased through (1) pattern refinement technology and (2) multi-level cell (MLC) technology. However, pattern refinement involves a costly problem, and MLC techniques are limited in terms of the number of bits per cell that can be increased. For this reason, 3D-IC technology seems to be an inevitable way to increase memory capacity. Of course, when pattern refinement and MLS technologies are combined with 3D-IC technology, it is expected that pattern refinement and MLS technologies will also develop independently of 3D-IC technology.

As one of the 3D-IC technologies, punch-and-plug technology has recently been proposed. The punch-and-plug technique involves sequentially forming multiple layers of thin films on a substrate and then forming plugs through the thin films. This technology has attracted much attention recently because it can greatly increase the memory capacity of a 3D memory device without significantly increasing the manufacturing cost.

One object of the present invention is to provide a method of manufacturing a three-dimensional semiconductor device capable of preventing a decrease in operating current and an increase in resistance of a string.

 One object of the present invention is to provide a three-dimensional semiconductor device capable of preventing a decrease in operating current and an increase in resistance of a string.

Provided is a method of manufacturing a three-dimensional semiconductor device including a semiconductor pattern inserted into an upper surface of a substrate. The method forms a mold structure on a substrate, forms an opening through the mold structure to expose the top surface of the substrate, sequentially forms a vertical film and a first semiconductor film covering the inner wall of the opening, and the opening A through groove for penetrating the first semiconductor film and the vertical film to expose the upper surface of the substrate again at the bottom of the substrate; and isotropically etching the vertical film exposed through the through groove to undercut the vertical film. After forming the region, forming a second semiconductor layer connecting the substrate and the first semiconductor layer to the undercut region.

In some embodiments, the vertical film and the first semiconductor film are formed so as to cover the inner wall of the opening to have a substantially conformal thickness, and the sum of the deposition thicknesses of the vertical film and the first semiconductor film is It may be less than half the width of the opening. In this case, the forming of the through groove may be performed by anisotropically etching the first semiconductor layer to form a semiconductor spacer exposing the top surface of the vertical layer at the bottom of the opening, and then anisotropically etching the vertical layer exposed by the semiconductor spacer. It may include the step.

In example embodiments, the forming of the through groove may include forming a passivation layer spacer exposing a bottom surface of the first semiconductor layer on an inner sidewall of the first semiconductor layer before anisotropically etching the first semiconductor layer. It may further include. The passivation layer spacer may be formed of a material having an etching selectivity with respect to the first semiconductor layer. In addition, the passivation layer spacer may be formed to a thickness thinner than half the difference between the half of the opening width and the sum of the deposition thicknesses of the vertical layer and the first semiconductor layer.

In example embodiments, an isotropic etching of the first semiconductor layer using the passivation layer spacer as an etching mask may be further performed before forming the undercut region. In addition, the passivation spacer may be removed during the step of forming the undercut region.

In example embodiments, the vertical layer may include a capping layer, a charge storage layer, and a tunnel layer that sequentially cover an inner wall of the opening, and the forming of the undercut region may beotropically form the charge storage layer exposed by the through hole. Etching to form a first undercut region exposing the capping layer and the tunnel layer. Thereafter, the capping layer and the tunnel layer exposed by the first undercut region are isotropically etched to form a second undercut region.

In example embodiments, the vertical layer may include a capping layer, a charge storage layer, and a tunnel layer that sequentially cover an inner wall of the opening, and the forming of the undercut region may include the tunnel layer and the capping exposed by the through hole. Isotropically etching the film to form a first undercut region exposing the charge storage film. Thereafter, the charge storage layer exposed by the first undercut region is isotropically etched to form a second undercut region.

Provided is a three-dimensional semiconductor device including a semiconductor pattern inserted in an upper surface of a substrate. The device includes a conductive structure disposed on a substrate, including conductive patterns stacked in turn, a semiconductor pattern penetrating through the conductive structure and inserted into an upper surface of the substrate, and an insulating film structure interposed between the semiconductor pattern and the conductive structure. It may include. In addition, the semiconductor pattern may extend horizontally under the insulating layer structure to directly contact the sidewall of the substrate.

In example embodiments, the substrate may be formed of a semiconductor material having fewer crystal defects than the semiconductor pattern.

In example embodiments, the semiconductor pattern may include a semiconductor spacer covering an inner sidewall of the insulating layer structure and a semiconductor body portion covering the inner sidewall of the semiconductor spacer. In this case, a bottom surface of the semiconductor spacer may be inserted deeper into the substrate than a bottom surface of the insulating film structure, and the semiconductor body may extend horizontally under the insulating film structure to directly contact the sidewall of the substrate.

According to some embodiments of the present invention, an undercut region is formed under the vertical pattern, and the undercut region is formed with a semiconductor material connecting the substrate and the semiconductor spacer. Accordingly, problems of the decrease in the operating current and the increase in the resistance of the string to be described with reference to FIG. 65 can be prevented.

1 to 11 are perspective views illustrating a method of manufacturing a 3D semiconductor device according to a first embodiment of the present invention.
12 to 21 are perspective views illustrating a method of manufacturing a three-dimensional semiconductor device according to a second embodiment of the present invention.
22 to 24 are perspective views illustrating three-dimensional semiconductor devices according to the first embodiment of the present invention.
25 to 27 are perspective views illustrating three-dimensional semiconductor devices according to a second embodiment of the present invention.
28 to 43 are perspective views for describing embodiments of the present invention related to the structure of an information storage film.
44 to 46 are cross-sectional views illustrating 3D semiconductor devices in accordance with modified embodiments.
47 and 48 are perspective views illustrating three-dimensional semiconductor devices according to other modified embodiments.
49 and 50 are perspective views illustrating three-dimensional semiconductor devices according to comparative examples.
51 to 64 are cross-sectional views illustrating specific embodiments of forming the undercut region described with reference to FIG. 24.
65 and 66 are cross-sectional views for comparing and explaining three-dimensional semiconductor devices according to example embodiments.
67 is a block diagram schematically illustrating an example of a memory card including a flash memory device according to the present invention.
68 is a block diagram briefly showing an information processing system equipped with a memory system according to the present invention.

Objects, other objects, features and advantages of the present invention will be readily understood through the following preferred embodiments associated with the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate or a third film may be interposed therebetween. In addition, in the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical contents. In addition, although the terms first, second, third, etc. are used to describe various regions, films, etc. in various embodiments of the present specification, these regions, films should not be limited by these terms. . These terms are only used to distinguish any given region or film from other regions or films. Thus, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment.

The 3D semiconductor device according to example embodiments may include a cell array region, a peripheral circuit region, a sense amplifier region, a decoding circuit region, and a connection region. In the cell array region, a plurality of memory cells and bit lines and word lines for electrical connection to the memory cells are disposed. Circuits for driving the memory cells are disposed in the peripheral circuit region, and circuits for reading information stored in the memory cells are disposed in the sense amplifier region. The connection area may be disposed between the cell array area and the decoding circuit area, and a wiring structure may be disposed to electrically connect the word lines and the decoding circuit area.

In the following, technical features related to a part of the cell array region of the three-dimensional semiconductor device will be mainly described. Meanwhile, Korean Patent Application No. 2009-0126854, filed December 18, 2009, Korean Patent Application No. 2010-0014751, filed February 18, 2010, and Korean Patent Application No. 2010, filed January 22, 2010 -0006124, Korean Patent Application No. 2009-0099370, filed on October 19, 2009, US Patent Application No. 12 / 480,399, filed on June 8, 2009, is not only the cell array region (a peripheral circuit region or a connection region). Technical features related to other areas). The contents disclosed in Korean Patent Application Nos. 2009-0126854, 2010-0014751, 2010-0006124, 2009-0099370 and US Patent Application No. 12 / 480,399 are incorporated in their entirety as part of this application.

In addition, the Korean Patent Application No. 2010-0006124 discloses a configuration of forming a memory structure in multiple layers by repeating the step of forming the memory structure. The technical idea of the present invention can be extended to embodiments of forming a multilayer memory structures by repeatedly forming a memory structure to be described below.

[Method-Part 1 Example ]

1 to 11 are perspective views illustrating a method of manufacturing a 3D semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1, the mold structure 100 is formed on the substrate 10. The substrate 10 may be one of materials having semiconductor characteristics, insulating materials, and a semiconductor or a conductor covered by the insulating material. For example, the substrate 10 may be a silicon wafer.

According to a modified embodiment, a lower structure (not shown) including at least one transistor may be disposed between the substrate 10 and the template structure 100. However, in the following description, an embodiment in which the mold structure 100 is directly formed on the substrate 10 will be described for easier understanding of the technical spirit of the present invention. Nevertheless, the technical spirit of the present invention is not limited thereto.

The mold structure 100 may include a plurality of insulating layers 121 to 129 and 120 and a plurality of sacrificial layers 131 to 138 and 130. The insulating layers 120 and the sacrificial layers 130 may be alternately and repeatedly stacked as illustrated. The sacrificial layer 130 may be formed of a material that can be etched with an etch selectivity with respect to the insulating layer 120. That is, in the process of etching the sacrificial layer 130 using a predetermined etching recipe, the sacrificial layer 130 may be formed of a material that can be etched while minimizing the etching of the insulating layer 120. As is known, such etch selectivity may be quantitatively expressed through a ratio of an etching rate of the sacrificial layer 130 to an etching rate of the insulating layer 120. In example embodiments, the sacrificial layer 130 may provide an etch selectivity of 1:10 to 1: 200 (more specifically, 1:30 to 1: 100) with respect to the insulating layer 120. It may be one of the materials. For example, the insulating film 120 may be at least one of a silicon oxide film and a silicon nitride film, and the sacrificial film 130 may be different from the insulating film 120 selected from a silicon film, a silicon oxide film, silicon carbide, and a silicon nitride film. It may be a substance. In the following description, an embodiment in which the insulating layers 120 are silicon oxide layers and the sacrificial layers 130 are silicon nitride layers will be described.

In some embodiments, as illustrated, the sacrificial layers 130 may be formed to have substantially the same thickness. In contrast, the thicknesses of the insulating layers 120 may not all be the same. For example, the lowermost layer 121 of the insulating layers 120 is formed to be thinner than the sacrificial layer 130, and the third layer 123 from the bottom and the third layer 127 from the top are the sacrificial layers. The film 130 may have a thickness greater than that of the film 130, and the rest of the insulating layers 120 may be thinner or thicker than the sacrificial film 130. However, the thickness of the insulating layers 120 may be variously modified from those shown, and the number of layers constituting the mold structure 100 may also be variously modified.

2 and 3, after forming the openings 105 penetrating the mold structure 100, a vertical film 150 conformally covering the inner walls of the openings 105 is formed. The vertical layer 150 may extend horizontally from the openings 105 to cover the upper surface of the mold structure 100.

According to this embodiment, the openings 105 may be formed in a hole shape. That is, each of the openings 105 may be formed in a shape whose depth is at least five times larger than its width. In addition, according to this embodiment, the openings 105 may be formed two-dimensionally on the upper surface (ie, the xy plane) of the substrate 10. That is, each of the openings 105 may be an isolated region formed spaced apart from others along the x and y directions.

The forming of the openings 105 may include forming a predetermined mask pattern defining a position of the openings 105 on the mold structure 100 and using the mold structure 100 as an etching mask. May comprise anisotropic etching. Meanwhile, since the mold structure 100 includes at least two kinds of different films, the sidewall of the opening 105 may not be completely perpendicular to the upper surface of the substrate 10. For example, the closer to the upper surface of the substrate 10, the width of the opening 105 may be reduced. This non-uniformity of the width of the opening 105 can cause non-uniformity in the operating characteristics of the three-dimensionally arranged transistors. A more detailed description of this non-uniformity and ways to improve it are disclosed in US Application No. 12 / 420,518, which is hereby incorporated by reference in its entirety as part of this application.

Meanwhile, in the embodiment in which the mold structure 100 is directly formed on the substrate 10, the opening 105 may be formed to expose the top surface of the substrate 10 as shown. In addition, as a result of over-etch in the anisotropic etching step, the substrate 10 below the opening 105 may be recessed to a predetermined depth as shown.

The vertical layer 150 may be composed of one thin film or a plurality of thin films. For example, the vertical layer 150 may include at least one of thin films used as memory elements of a charge trapping nonvolatile memory transistor. Embodiments of the present invention may be variously divided according to what the thin films constituting the vertical film 150. These refined embodiments will be described again in detail later with reference to FIGS. 28-35.

Referring to FIG. 4, a vertical pattern 155 and a semiconductor spacer 165 are formed to sequentially cover inner walls of each of the openings 105. In this step, after forming the first semiconductor film conformally covering the resultant on which the vertical film 150 is formed, the first semiconductor film and the vertical film 150 are anisotropically etched at the bottom of the openings 105. And exposing an upper surface of the substrate 10. Accordingly, the vertical pattern 155 and the semiconductor spacer 165 may be formed in a cylindrical shape having both open ends. Further, as a result of over-etching in the anisotropic etching of the first semiconductor film, as shown, the upper surface of the substrate 10 exposed by the semiconductor spacer 165 may be recessed. Can be.

Meanwhile, during the anisotropic etching step, a portion of the vertical layer 150 positioned below the semiconductor spacer 165 may not be etched. In this case, the vertical pattern 155 may be the semiconductor spacer 165. It may have a bottom portion interposed between the bottom surface and the top surface of the substrate 10. In example embodiments, the etching of the exposed surface of the vertical pattern 155 may be further performed using the semiconductor spacer 165 as an etching mask. In this case, as shown in FIG. 24, an undercut region may be formed under the semiconductor spacer 165, and the length of the vertical pattern 155 may be shorter than the length of the semiconductor spacer 165.

In addition, an upper surface of the mold structure 100 may be exposed as a result of anisotropic etching of the first semiconductor layer and the vertical layer 150. Accordingly, each of the vertical patterns 155 and each of the semiconductor spacers 165 may be localized in the openings 105. That is, the vertical patterns 155 and the semiconductor spacers 165 may be two-dimensionally arranged on an xy plane.

The first semiconductor film may be a polycrystalline silicon film formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. In addition, the first semiconductor film may be formed to a thickness selected from a range of 1/50 to 1/5 of the width of the opening 105. According to a modified embodiment of the present invention, the first semiconductor film may be formed using one of epitaxial techniques. Korean Application No. 2010-0009628, filed Feb. 2, 2010, discloses epitaxial techniques that can be used to implement the technical idea of the present invention, the disclosures of which are hereby incorporated in their entirety as part of this application. do. According to another modified embodiment of the present invention, the first semiconductor film may be one of an organic semiconductor film and carbon nanostructures.

5 and 6, the second semiconductor layer 170 and the buried insulating layer 180 are sequentially formed on the resultant product on which the vertical pattern 155 is formed.

The second semiconductor film 170 may be a polycrystalline silicon film formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. In example embodiments, the second semiconductor layer 170 may be conformally formed to have a thickness that does not completely fill the opening 105. That is, as shown in the drawing, the second semiconductor layer 170 may define a pinhole 105a in the opening 105.

The buried insulating layer 180 may be formed to fill the pinhole 105a, and may be one of insulating materials and a silicon oxide layer formed using an SG process. According to an embodiment, before the buried insulating layer 180 is formed, a hydrogen annealing step may be further performed to heat-treat the resultant product on which the second semiconductor film 170 is formed in a gas atmosphere containing hydrogen or deuterium. Many of the crystal defects present in the semiconductor spacer 165 and the second semiconductor film 170 may be healed by this hydrogen annealing step.

According to a modified embodiment of the present invention, the second semiconductor film 170 may be formed to fill the openings 105 in which the semiconductor spacer 165 is formed. In this case, the buried insulating film 180 may be formed. The forming step may be omitted. 23 and 24 exemplarily show the final result according to this modified embodiment.

Referring to FIG. 7, trenches 200 are formed through the mold structure 100 to expose sidewalls of the sacrificial layers 130 and the insulating layers 120. The trenches 200 may be spaced apart from and intersected between the openings 105 as shown.

The forming of the trenches 200 may include forming an etch mask on the upper portion of the mold structure 100 or on the buried insulating layer 180, and then, until the upper surface of the substrate 10 is exposed. And anisotropically etching the films under the etch mask. Accordingly, as shown, the second semiconductor layer 170 and the buried insulating layer 180 may be patterned on the mold structure 100 to define upper inlets of the trenches 200. As a result of the over-etch in the anisotropic etching step, the substrate 10 under the trench 200 may be recessed to a predetermined depth as shown.

Meanwhile, since the etching targets are substantially the same, similarly to the opening 105, the trenches 200 may have a reduced width as they are closer to the upper surface of the substrate 10. Such non-uniformity of the width of the trenches 200 may cause non-uniformity in the operating characteristics of transistors that are three-dimensionally arranged. A more detailed description of this inhomogeneity and ways to improve it are disclosed in US Application No. 12 / 420,518, filed April 8, 2009, which is hereby incorporated by reference in its entirety as part of this application. do.

According to one embodiment, as shown, a pair of trenches 200 may be formed on both sides of each of the openings 105. That is, the numbers of the openings 105 and the trenches 200 having the same y coordinate and arranged along the x-axis direction may be substantially the same. However, the technical idea of the present invention is not limited to these embodiments. For example, Korean Patent Application No. 2009-0126854, filed December 18, 2009, discloses modified embodiments related to the relative placement of the trenches 200 with respect to the openings 105. The contents disclosed in Korean Patent Application No. 2009-0126854 are incorporated in their entirety as part of this application.

Referring to FIG. 8, the exposed sacrificial layers 130 are selectively removed to form recess regions 210 between the insulating layers 120.

The recess regions 210 may be gap regions formed to extend horizontally from the trenches 200, and may be formed to expose sidewalls of the vertical patterns 155. More specifically, an outer boundary of the recess region 210 is defined by the insulating layers 120 positioned at upper and lower portions thereof and the trenches 200 positioned at both sides thereof. . In addition, an internal boundary of the recessed region 210 is defined by the vertical patterns 155 that vertically penetrate it.

The forming of the recess regions 210 may horizontally etch the sacrificial layers 130 using an etch recipe having an etch selectivity with respect to the insulating layers 120 and the vertical patterns 155. It may include the step. For example, when the sacrificial layers 130 are silicon nitride layers and the insulating layers 120 are silicon oxide layers, the horizontal etching step may be performed using an etchant including phosphoric acid.

Referring to FIG. 9, horizontal structures HS may be formed to fill the recess regions 210. The horizontal structure HS may include horizontal patterns 220 covering an inner wall of the recess region 210 and a conductive pattern 230 filling the remaining space of the recess region 210.

The forming of the horizontal structures HS may include forming a horizontal layer and a conductive layer which sequentially fill the recess regions 210, and then removing the conductive layer in the trenches 200 to form the recess region. And leaving the conductive patterns 230 in the holes 210.

Similar to the case of the vertical layer 150, the horizontal layer or the horizontal patterns 220 may be formed of one thin film or a plurality of thin films. In example embodiments, the horizontal pattern 220 may include a blocking dielectric layer of the charge trapping nonvolatile memory transistor. As described above, embodiments of the present invention may be subdivided in various ways according to what the thin films constituting each of the vertical layer 150 and the horizontal pattern 220 are. These refined embodiments will be described again in detail later with reference to FIGS. 28-35.

The conductive layer may be formed to fill the recess regions 210 covered by the horizontal layer. In this case, the trenches 200 may be completely or partially filled by the conductive layer. The conductive layer may include at least one of doped silicon, metal materials, metal nitride layers, and metal silicides. For example, the conductive film may include a tantalum nitride film or tungsten. In an embodiment, the conductive layer may be formed to conformally cover the inner wall of the trench 200. In this case, the forming of the conductive pattern 230 may include forming the conductive layer in the trench 200. Removing the film by a method of isotropic etching. In example embodiments, the conductive layer may be formed to fill the trench 200. In this case, the forming of the conductive pattern 230 may include anisotropically etching the conductive layer in the trench 200. It may include.

According to the exemplary embodiment of the present invention for the flash memory, after the conductive patterns 230 are formed, the impurity regions 240 may be further formed. The impurity regions 240 may be formed through an ion implantation process, and may be formed in the substrate 10 exposed through the trench 200. Meanwhile, the impurity regions 240 may have a different conductivity type from that of the substrate 10. Alternatively, an area (hereinafter, a contact area) of the substrate 10 in contact with the second semiconductor film 170 may have the same conductivity type as the substrate 10. Accordingly, the impurity regions 240 may form a P-junction with the substrate 10 or the second semiconductor film 170.

In example embodiments, each of the impurity regions 240 may be connected to each other to be in an equipotential state. According to another embodiment, each of the impurity regions 240 may be electrically separated to have different potentials. According to another embodiment, the impurity regions 240 may constitute a plurality of independent source groups including a plurality of different impurity regions, and each of the source groups may be electrically connected to have different potentials. Can be separated.

Referring to FIG. 10, an electrode separation pattern 250 may be formed to fill the trenches 200. The forming of the electrode isolation pattern 250 may include forming an electrode isolation layer on a resultant product on which the impurity regions 240 are formed, and then etching the resultant to expose the upper surface of the mold structure 100. It may include. The electrode separator may be formed of at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, and the etching may be performed using a planarization technique such as a chemical-mechanical polishing technique or an etch back technique. As a result of the planarization etching, the buried insulating film 180 and the second semiconductor film 170 are buried patterns 185 locally disposed in each of the openings 105, as shown. The semiconductor body portions 175 may be formed.

According to an embodiment of the present invention, the vertical pattern 155, the semiconductor spacer 165, and the semiconductor body 175 may constitute one vertical structure VS, and may be disposed on the substrate 10. A plurality of vertical structures VS, which are two-dimensionally arranged while penetrating the mold structure 100, may be formed. According to the above configuration, the position where the vertical structures VS are disposed is defined by the openings 105. The buried pattern 185 may also constitute the vertical structure VS.

Referring to FIG. 11, upper plugs 260 may be formed on upper portions of the vertical structures VS, and upper wirings 270 may be formed on upper portions of the upper plugs 260. have.

In example embodiments, an upper region of the semiconductor spacer 165 and the semiconductor body 175 may have an upper impurity region (not shown). The bottom of the upper impurity region may be higher than the top surface of the uppermost layer of the horizontal structures HS. In addition, the upper impurity region may be doped with a different conductivity type from a portion of the semiconductor spacer 165 disposed below it. Accordingly, the upper impurity region may constitute a lower region and a diode. According to this embodiment, the upper plugs 260 may be one of doped silicon and metallic materials.

According to another embodiment, the upper plugs 260 may be silicon films doped with a conductive type different from those of the semiconductor spacer 165 and the semiconductor body 175. In this case, the upper plugs 260 may form a P & I junction with the semiconductor spacer 165 and the semiconductor body 175.

Each of the upper wires 270 may be electrically connected to the semiconductor spacer 165 and the semiconductor body 175 through the upper plug 260 and may cross the horizontal structures HS. Can be. According to an embodiment for NAND flash memory, the upper interconnections 270 may be used as bit lines that connect one ends of a plurality of cell strings.

[Method-second Example ]

12 to 21 are perspective views illustrating a method of manufacturing a three-dimensional semiconductor device according to a second embodiment of the present invention. For brevity, the technical features of the second embodiment, which are substantially the same as the first embodiment described above, may be omitted in the following description.

1 and 12, openings 106 penetrating the mold structure 100 are formed. According to this embodiment, the openings 106 may comprise a hexahedron shaped portion whose aspect ratios of the cross sections projected on the xy plane and the xz plane are at least five or more. That is, the lengths in the y and z directions of the opening 106 may be five times larger than the length in the x direction thereof.

Referring to FIG. 13, a preliminary vertical pattern 154 and a preliminary semiconductor spacer 164 are formed to sequentially cover an inner wall of each of the openings 106. In this step, after forming a vertical film and a first semiconductor film covering the inner walls of the openings 106 in turn, the first semiconductor film is anisotropically etched to remove the upper surface of the substrate 10 from the bottom of the opening 106. Exposing it. As a result of over-etching in the anisotropic etching of the first semiconductor film, as shown, the upper surface of the substrate 10 exposed by the preliminary semiconductor spacer 164 may be recessed. have.

On the other hand, as in the previous embodiment, the vertical film may be composed of one thin film or a plurality of thin films, as will be described in detail later with reference to FIGS. 36 to 43, embodiments of the present invention are the vertical The thin films constituting the film may be subdivided in various ways according to what they are.

14 and 15, a second semiconductor layer 170 and a string defining mask 182 are sequentially formed on a resultant product on which the preliminary vertical pattern 154 is formed. The second semiconductor film 170 may be a polycrystalline silicon film formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques, and the string defining mask 182 may use an esoteric technique. It may be one of the insulating materials and silicon oxide film formed by.

The forming of the string defining mask 182 may include forming a string separation layer filling the openings 106 on the resultant product on which the second semiconductor layer 170 is formed, and then crossing the openings 106. Patterning the string separator. The patterning of the string separator may include anisotropically etching the string separator using an etch recipe having an etch selectivity with respect to the second semiconductor layer 170. In example embodiments, the patterning of the string isolation layer may be performed to expose the second semiconductor layer 170 at the bottom of the opening 106.

Accordingly, each of the string definition masks 182 extends downwardly from the upper pattern 182a and the upper pattern 182a across the upper portions of the openings 106 to partially cover the openings 106. It may have filling patterns 182b that fill. Surfaces of the second semiconductor layer 170 may be exposed between the extension patterns 182b. That is, the extension patterns 182b may be formed to expose sidewalls and a bottom surface of the second semiconductor film 170 positioned therebetween.

Referring to FIG. 16, the second semiconductor layer 170 and the preliminary semiconductor spacer 164 are sequentially patterned using the string definition masks 182 as an etching mask. The patterning step may include isotropically etching the second semiconductor film 170 and the preliminary semiconductor spacer 164 using an etch recipe having an etch selectivity with respect to the preliminary vertical pattern 154. .

According to one embodiment, during the patterning step, the preliminary vertical pattern 154 may be etched together to expose sidewalls of the mold structure 100. In this case, the preliminary vertical pattern 154 is horizontally separated to form two-dimensionally arranged vertical patterns 155, and the preliminary semiconductor spacer 164 is horizontally separated and arranged two-dimensionally. The semiconductor spacers 165 are formed. That is, vertical patterns 155 and semiconductor spacers 165 that are two-dimensionally arranged on the substrate 10 are formed between the string definition masks 182 and the mold structure 100. In addition, as a result of the patterning process, the second semiconductor layer 170 also forms horizontally separated second semiconductor patterns 174. As illustrated, the second semiconductor patterns 174 may include semiconductor body parts 175 interposed between the semiconductor spacers 165 and the string defining masks 182.

According to another embodiment, the second semiconductor patterns 174 may be separated by the patterning process, but the preliminary vertical pattern 154 may remain on the inner walls of the openings 106. That is, the patterning process may be performed so as not to expose the sidewall of the mold structure 100. 27 is a perspective view showing a portion of the final result according to this modified embodiment. When the vertical film is formed of a plurality of thin films, some of the plurality of thin films constituting the vertical film or the preliminary vertical pattern 154 may remain on the inner wall of the openings 106.

Referring to FIGS. 17 and 18, after forming the string isolation layers ISO filling the openings 106 between the string definition masks 182, the sacrificial layers may pass through the mold structure 100. 130 and trenches 200 exposing sidewalls of the insulating layers 120 are formed.

The string separators ISO may be formed of at least one of insulating materials. In addition, the string isolation layers ISO may be formed in a shape similar to that of the string definition masks 182. That is, each of the string separators ISO extends downwardly from the upper separation pattern ISOa and the upper separation pattern ISOa to horizontally cross the openings 106 to fill the openings 106. It may have parts (not shown).

The trenches 200 may be formed to cross between the openings 105 and may be formed using the method of the first embodiment described with reference to FIG. 9. The semiconductor body parts 175 constituting the second semiconductor pattern 174 are separated from each other by the trenches 200, and the extension patterns 182b constituting the string definition mask 182 may be separated from each other. Can be separated. Accordingly, the semiconductor body parts 175 may be two-dimensionally arranged on the substrate 10 similarly to the vertical patterns 155 and the semiconductor spacers 165.

According to the above-described configuration, a plurality of vertical structures VS and a plurality of string separation layers ISO disposed therebetween may be disposed in one opening 106, and each of the vertical structures VS may be disposed. May include one semiconductor body 175, a pair of vertical patterns 155, and a pair of semiconductor spacers 165. The vertical structure VS may further include the extension pattern 182b.

Subsequently, as shown in FIG. 19, after the exposed sacrificial layers 130 are selectively removed to form recess regions 210 between the insulating layers 120, as shown in FIG. 20, Horizontal structures HS may be formed to fill the recess regions 210. The recess regions 210 and the horizontal structures HS may be formed using the method of the first embodiment described with reference to FIGS. 8 and 9. Accordingly, the horizontal structure HS may include horizontal patterns 220 covering the inner wall of the recess region 210 and a conductive pattern 230 filling the remaining space of the recess region 210. . In addition, as shown in FIG. 20, after the conductive patterns 230 are formed, impurity regions 240 may be further formed in the substrate 10 exposed through the trench 200. .

Afterwards, as shown in FIG. 21, electrode isolation patterns 250 filling the trenches 200, upper plugs 260 and upper plugs 260 connected to each of the vertical structures VS. Upper wirings 270 are connected to each other. The electrode separation patterns 250, the upper plugs 260, and the upper wirings 270 may be formed using the method of the first embodiment described with reference to FIGS. 10 and 11.

[3D Semiconductor Device]

Hereinafter, 3D semiconductor devices according to the inventive concepts will be described with reference to FIGS. 22 to 27. 22 to 27, in order to reduce the complexity in the drawings and to better understand the technical spirit of the present invention, some of the elements constituting the 3D semiconductor device are intentionally omitted. For those skilled in the art, this omitted part will be omitted from the parts shown in the drawings and from the manufacturing methods described above, a separate description thereof is omitted. In addition, for brevity of description, descriptions of technical features overlapping with the manufacturing methods described above may be omitted. However, the three-dimensional semiconductor device to be described herein needs to have all or completely the technical features described in the above-described manufacturing method, in that it can be manufactured through variations of the manufacturing method described above or other manufacturing methods. There is no.

[Structure-First Example  And that Variants ]

FIG. 22 is a perspective view illustrating a 3D semiconductor device according to a first embodiment of the present invention, and FIGS. 23 and 24 are perspective views illustrating a 3D semiconductor device according to modified first embodiments.

Referring to FIG. 22, horizontal structures HS are three-dimensionally arranged on the substrate 10, and vertical structures VS vertically penetrating the horizontal structures HS are disposed on the substrate 10. It is arranged in two dimensions.

Each of the horizontal structures HS includes a conductive pattern 230 and a horizontal pattern 220. The conductive pattern 230 is disposed such that its long axis is parallel to the top surface (ie, xy plane) of the substrate 10. In addition, a plurality of openings 105 penetrated by the vertical structures VS are formed in the conductive pattern 230. The horizontal pattern 220 may be interposed between the conductive pattern 230 and the vertical structures VS. That is, the horizontal pattern 220 may cover the inner sidewall of the conductive pattern 230 or the sidewalls of the openings 105. In addition, according to this embodiment, the horizontal patterns 220 may extend horizontally from the openings 105 to cover the top and bottom surfaces of the conductive pattern 230.

The conductive pattern 230 may include at least one of doped silicon, metal materials, metal nitride layers, and metal silicides. For example, the conductive pattern 230 may include a tantalum nitride film or tungsten. The horizontal pattern 220 may be composed of one thin film or a plurality of thin films. According to an embodiment, the horizontal pattern 220 may include at least a blocking insulating layer used as a memory element of the charge trapping nonvolatile memory transistor.

Each of the vertical structures VS may include a semiconductor pattern SP connected to an upper surface of the substrate 10 and a vertical pattern 155 interposed between the semiconductor pattern SP and the horizontal structures HS. It may include. In example embodiments, the semiconductor pattern SP may include a semiconductor spacer 165 and a semiconductor body 175. The semiconductor spacer 165 may have a cylindrical shape in which upper and lower inlets are open, and the semiconductor body 175 covers an inner wall of the semiconductor spacer 165 and an upper surface of the substrate 10. It may be cup-shaped. That is, the semiconductor body portion 175 is formed to a thickness that does not completely fill the opening 105, the pinhole 105a may be defined therein. According to this embodiment, as shown, the pinholes 105a may be filled by the buried patterns 185.

The vertical pattern 155 may have a cylindrical shape in which upper and lower inlets are open, and may include a bottom portion extending below the semiconductor spacer 165. The vertical pattern 155 vertically extends between the semiconductor pattern SP and the horizontal structures HS to form a single body covering the entire outer wall of one semiconductor pattern SP, as shown. Can be.

In example embodiments, the semiconductor pattern SP may be one of materials having semiconductor properties. For example, each of the semiconductor spacer 165 and the semiconductor body 175 may be one of polycrystalline silicon, an organic semiconductor film, and carbon nanostructures. The vertical pattern 155 may be composed of one thin film or a plurality of thin films. According to one embodiment, the vertical pattern 155 may include at least a tunnel insulating film used as a memory element of the charge trapping nonvolatile memory transistor.

On the other hand, the horizontal structures HS and the vertical structures VS are localized intersecting regions (or channel regions) therebetween, and vertically adjacent regions perpendicular to the intersection regions. And horizontally adjacent regions horizontally adjacent to the intersection regions. The vertical contiguous regions may be defined as sidewalls of the vertical structure VS positioned between the horizontal structures HS, and the horizontal contiguous regions are positioned between the vertical structures VS. It can be defined as surfaces of (HS). According to an aspect of the present invention, the horizontal pattern 220 and the vertical pattern 155 is disposed in the crossing areas, the horizontal pattern 220 extends to the horizontal adjacent areas, the vertical pattern ( 155 extends into the vertically adjacent regions.

Referring to FIG. 23, the semiconductor body 175 may be formed to substantially completely fill the opening 105 in which the semiconductor spacer 165 is formed. According to one embodiment, a void may be formed inside the semiconductor body 175.

Meanwhile, the semiconductor body 175 or the semiconductor spacer 165 may be formed through chemical vapor deposition by experiencing a crystal structure changing step (e.g., an epitaxial technique including a laser annealing step). It may have a crystal structure different from. For example, the semiconductor body 175 or the semiconductor spacer 165 may be formed such that its lower region and its upper region have different grain sizes. The semiconductor body 175 or the semiconductor spacer 165 according to the above-described or later embodiments may have the same technical features described above with respect to the crystal structure.

Referring to FIG. 24, the length of the vertical pattern 155 may be shorter than the length of the semiconductor spacer 165. In other words, an under-cut region 77 defining a bottom surface of the vertical pattern 155 may be formed under the semiconductor spacer 165. Such a structure may be obtained by isotropically etching the lower region of the vertical pattern 155 using the semiconductor spacer 165 as an etching mask as described above with reference to FIG. 4. The undercut region 77 may be filled by the semiconductor body 175. The vertical structures VS according to the above-described or later embodiments may have the same technical features described above with respect to the undercut area.

[Structure-Second Example  And that Variants ]

25 is a perspective view illustrating a 3D semiconductor device according to a second embodiment of the present invention, and FIGS. 26 and 27 are perspective views illustrating a 3D semiconductor device according to modified second embodiments. For brevity of description, a description of technical features that overlap with the three-dimensional semiconductor device according to the first embodiment described with reference to FIGS. 22 to 24 may be omitted.

Referring to FIG. 25, horizontal structures HS are three-dimensionally arranged on the substrate 10, and vertical structures VS are disposed between the horizontal structures HS. The vertical structures VS are two-dimensionally arranged on the substrate 10 and disposed to face sidewalls of the horizontal structures HS.

Each of the horizontal structures HS includes a conductive pattern 230 and a horizontal pattern 220. The conductive pattern 230 may be formed in a line shape whose long axis is parallel to the upper surface of the substrate 10. The horizontal pattern 220 may not only be interposed between the conductive pattern 230 and the vertical structures VS and may extend horizontally to cover the top and bottom surfaces of the conductive pattern 230. However, one sidewall of the conductive pattern 230 spaced apart from the vertical structure VS may not be covered by the horizontal pattern 220. That is, the cross-section of the horizontal pattern 220 projected on the xz plane may be a "c" or "u" shape.

Each of the vertical structures VS may include a semiconductor pattern SP connected to an upper surface of the substrate 10 and a vertical pattern 155 interposed between the semiconductor pattern SP and the horizontal structures HS. It may include. According to one embodiment, one semiconductor pattern SP constituting one vertical structure VS may include a pair of semiconductor spacers 165 and one semiconductor body portion 175 disposed therebetween. Can be.

The semiconductor body portion 175 may include a pair of sidewalls vertically crossing the horizontal structures HS and a bottom portion connecting bottom surfaces of the sidewall portions. That is, the semiconductor body portion 175 may include a horseshoe-shaped portion. Each of the semiconductor spacers 165 may include a hexahedral portion interposed between the sidewall portion of the semiconductor body 175 and the vertical pattern 155. The sidewalls of the semiconductor body 175 and the thicknesses of the semiconductor spacer 165 in the x direction may be smaller than a distance between the pair of horizontally adjacent conductive patterns 230. An extension pattern 182b of the string defining mask 182 may be disposed between sidewalls of the semiconductor body 175 as illustrated in FIG. 15.

The vertical pattern 155 may have a hexahedron shape, but its thickness in the x direction may be smaller than a distance between a pair of horizontally adjacent conductive patterns 230. That is, the vertical pattern 155 may be in the form of an elongated plate. In addition, the vertical pattern 155 may further include a bottom portion extending downward of the semiconductor spacer 165. As illustrated, the vertical pattern 155 may extend vertically and continuously to form an entire sidewall of the semiconductor spacer 165. Can cover.

26 and 27, the semiconductor body 175 may be formed to substantially completely fill the opening 105 in which the semiconductor spacer 165 is formed. In example embodiments, a discontinuous interface 179 or a void may be formed in the semiconductor body 175. Meanwhile, as described with reference to FIG. 23, the semiconductor body 175 or the semiconductor spacer 165 may experience a crystal structure changing step (e.g., an epitaxial technique including a laser annealing step). It may have a crystal structure different from that of polycrystalline silicon formed through chemical vapor deposition.

Referring to FIG. 27, the vertical pattern 155 may include a horizontal extension part 155e extending horizontally as described with reference to FIG. 16. That is, the horizontal extension part 155e may be disposed between the semiconductor body parts 175 adjacent to each other and may contact the sidewall of the string isolation layer ISO.

Meanwhile, as described below with reference to FIGS. 36 to 43, according to embodiments of the charge trapping nonvolatile memory device, the vertical pattern 155 may include a tunnel insulating film TIL and a charge storage film CL. It may further include, and may further include a capping film (CPL) as shown additionally. In some exemplary embodiments, the horizontal extension part 155e may include both the tunnel insulating film TIL and the charge storage film CL. According to some of these embodiments, as shown in FIG. 27, the horizontal extension part 155e includes only the capping layer CPL, and the charge storage layer CL and the tunnel insulating layer TIL are It may be horizontally separated by the string separator ISO. This separation can be implemented through the manufacturing method described with reference to FIG. 16.

[ Information storage ]

When the technical idea of the present invention is used to implement a charge trapping nonvolatile memory device, the horizontal pattern 220 and the vertical pattern 155 in the above-described embodiments may constitute an information storage layer of a memory cell transistor. Can be. In this case, the number and type of thin films constituting each of the horizontal and vertical patterns 220 and 155 may vary, and the technical idea of the present invention may be subdivided into various embodiments based on the diversity. For example, embodiments of the present invention related to an information storage film may be classified as shown in Table 1 below.

Information storage Corresponding drawing VS HS SP TIL CL CPL BIL1 230 28/36 ^[1] SP TIL CL BIL1 230 29/37 SP TIL CL BIL1 230 30/38 SP TIL CL BIL1 BIL2 230 31/39 SP TIL CL BIL1 BIL2 230 32/40 SP TIL CL CPL BIL1 230 33/41 ^[2] SP TIL CL CPL BIL1 230 34/42 ^[3] SP TIL CL CPL BIL1 BIL2 230 35/43 TIL: Tunnel Insulating Layer BIL: Blocking Insulating Layer
CL: Charge storing Layer CPL: CaPping Layer
[1]: CPL with uniform thickness
[2]: for CPL with recessed sidewalls
[3]: In case of vertically separated CPL

When the technical idea of the present invention is used to implement a flash memory, as shown in Table 1 and FIGS. 28 to 43, the information storage film includes a tunnel insulating film TIL, a charge storage film CL, and a first blocking insulating film BIL1. ) May be included. In example embodiments, the data storage layer may further include a second blocking insulating layer BIL2 disposed between the first blocking insulating layer BIL1 and the conductive pattern 230. In addition, the data storage layer may further include a capping layer CPL interposed between the charge storage layer CL and the first blocking insulating layer BIL1. The films constituting the information storage film can be formed using a deposition technique (eg, chemical vapor deposition or atomic layer deposition technique) that can provide excellent step coverage.

As shown in Table 1 and FIGS. 28 to 43, the vertical structure VS includes at least a tunnel insulating film TIL, and the horizontal structure HS includes the first and second blocking insulating films BIL1 and BIL2. ) At least one. In this case, according to some embodiments, as illustrated in FIGS. 28, 29, 31, 33-37, 39, and 41-43, the vertical structure VS may include the charge storage layer CL. In addition, according to other embodiments, as shown in FIGS. 30, 32, 38, and 40, the horizontal structure HS may include the charge storage layer CL.

When the vertical structure VS includes the charge storage layer CL, as illustrated in FIGS. 28, 33-36, and 41-43, the vertical structure VS further includes the capping layer CPL. can do. However, as illustrated in FIGS. 29, 31, 37, and 39, the vertical structure VS and the horizontal structure HS may directly contact each other without the capping layer CPL.

The sidewall thickness of the capping layer CPL may be non-uniform. For example, the sidewalls of the capping layer CPL adjacent to the horizontal structure HS may be horizontally recessed while the recess regions 210 are formed. In this case, as shown in FIGS. 33 and 41, the thickness of the capping layer CPL is between the horizontal structures HS than in the region a (or the channel region) adjacent to the horizontal structure HS. May be thicker in region (b) (or vertically adjacent region). Alternatively, as shown in FIGS. 34 and 42, the capping layer CPL remains locally in the vertical adjacent region b, and the horizontal structure HS stores the charge in the channel region a. Direct contact with the sidewall of the film CL. However, as exemplarily illustrated in FIGS. 28 and 36, the sidewall thickness of the capping layer CPL may be substantially uniform.

According to some embodiments of the present invention, as shown in FIGS. 31, 32, 35, 39, 40, and 43, the horizontal structure HS may include both the first and second blocking insulating layers BIL1 and BIL2. It may include.

Meanwhile, in the type and method of forming the material, the charge storage film CL may be one of insulating films rich in trap sites and insulating films including nanoparticles, and may be one of chemical vapor deposition or atomic layer deposition techniques. It can be formed using. For example, the charge storage layer CL may include one of an insulating film including a trap insulating film, a floating gate electrode, or conductive nano dots. More specifically, the charge storage layer CL may include at least one of a silicon nitride film, a silicon oxynitride film, a silicon-rich nitride film, nanocrystalline silicon, and a laminated trap layer. It may include one.

The tunnel insulating layer TIL may be one of materials having a band gap larger than that of the charge storage layer CL, and may be formed using one of chemical vapor deposition or atomic layer deposition techniques. For example, the tunnel insulating film TIL may be a silicon oxide film formed using one of the above-described deposition techniques. In addition, the tunnel insulating film TIL may further experience a predetermined heat treatment step performed after the deposition process. The heat treatment step may be a rapid thermal nitriding process (RTN) or an annealing process performed in an atmosphere including at least one of nitrogen and oxygen.

The first and second blocking insulating films BIL1 and BIL2 may be formed of different materials, and one of the first and second blocking insulating films BIL1 and BIL2 may be smaller than the tunnel insulating film TIL. It may be one of materials having a band gap larger than that of the charge storage layer CL. In addition, the first and second blocking insulating layers BIL1 and BIL2 may be formed using one of chemical vapor deposition or atomic layer deposition techniques, and at least one of them may be formed through a wet oxidation process. . In example embodiments, the first blocking insulating film BIL1 is one of high dielectric films, such as an aluminum oxide film and a hafnium oxide film, and the second blocking insulating film BIL2 has a dielectric constant smaller than that of the first blocking insulating film BIL1. It may be a material having. In example embodiments, the second blocking insulating layer BIL2 may be one of the high dielectric layers, and the first blocking insulating layer BIL1 may be formed of a material having a dielectric constant smaller than that of the second blocking insulating layer BIL2. According to a modified embodiment, in addition to the first and second blocking insulating layers BIL1 and BIL2, at least one additional blocking insulating layer interposed between the charge storage layer CL and the conductive pattern 230. H) may be further formed.

The capping layer CPL may be a material capable of providing an etch selectivity with respect to the charge storage layer CL or the sacrificial layer 130. For example, when the sacrificial layer 130 is a silicon nitride layer, the capping layer CPL may be a silicon oxide layer. In this case, in the removal process of the sacrificial layer 130 to form the recess regions 210, the capping layer CPL is an etch stop layer to prevent etch damage of the charge storage layer CL. Can function. 28, 33, 35, 36, 41, and 43, when the capping layer CPL remains between the conductive pattern 230 and the charge storage layer CL, the capping layer C The CPL may be formed of a material that may contribute to preventing leakage (eg, back-tunneling) of charge stored in the charge storage layer CL. For example, the capping layer CPL may be one of a silicon oxide layer and a high dielectric layer.

[Deformed Examples ]

44 to 46 are cross-sectional views illustrating 3D semiconductor devices in accordance with modified embodiments.

44 to 46, at least one upper select line USL may be formed between the upper interconnection 270 and the horizontal structures HS. The upper selection line USL may be used as a gate electrode of the upper selection transistor, which controls the flow of current through the upper wiring 270 and the semiconductor pattern SP. The upper select transistor may be a MOS field effect transistor. In this case, an upper gate insulating layer UGI may be interposed between the upper select line USL and the semiconductor pattern SP. In order to control the current flow, the upper select line USL is in a direction crossing the upper wiring 270 (for example, in a direction parallel to the horizontal structure HS or the conductive pattern 230). Can be formed.

In example embodiments, the upper selection line USL may be formed using a process different from that of the conductive pattern 230 constituting the horizontal structure HS. In example embodiments, the upper selection line USL and the conductive pattern 230 may be formed of the same material by using the same process.

In addition, in some embodiments, the upper gate insulating film UGI is formed using the same process as one of the horizontal pattern 220 and the vertical pattern 155, thereby substantially the same material and the same as one of the above. It may be formed in a thickness. Alternatively, the upper gate insulating layer UGI may include the same thin film forming one of the horizontal pattern 220 and the vertical pattern 155. In example embodiments, the upper gate insulating layer UGI may be formed independently through a manufacturing process different from the horizontal pattern 220 and the vertical pattern 155.

45 and 46, an upper semiconductor pattern USP may be interposed between the upper wiring 270 and the semiconductor pattern SP, and the upper selection line USL may include the upper semiconductor pattern ( USP) can be formed around. In example embodiments, the upper semiconductor pattern USP may be the same conductive type as the semiconductor pattern SP. In addition, a pad PAD may be further formed between the upper semiconductor pattern USP and the upper plug 260.

As illustrated in FIG. 46, at least one lower selection line LSL may be formed between the substrate 10 and the horizontal structures HS. A lower semiconductor pattern LSP may be interposed between the substrate 10 and the semiconductor pattern SP, and the lower selection line LSL may be formed around the lower semiconductor pattern LSP. The lower selection line LSL may be used as a gate electrode of the lower selection transistor, which controls the flow of current through the impurity region 240 and the semiconductor pattern SP. A lower gate insulating layer LGI may be interposed between the lower selection line LSL and the lower semiconductor pattern LSP.

47 and 48 are perspective views illustrating three-dimensional semiconductor devices according to other modified embodiments. 47 and 48 are perspective views for describing modifications of the 3D semiconductor devices described with reference to FIGS. 22 and 25, respectively.

47 and 48, a metal pattern 255 connected to the impurity region 240 may be formed in the trench 200. In addition, trench spacers 245 may be further formed on sidewalls of the trench 200 for electrical separation between the metal pattern 255 and the conductive patterns 230.

The metal pattern 255 may be formed of a metallic material (for example, tungsten), and a barrier metal film (for example, metal nitride; not shown) between the impurity region 240 and the metal pattern 255. ) Or a silicide film (not shown) may be further formed. The trench spacers 245 may be one of insulating materials (eg, silicon oxide layers).

The metal pattern 255 and the trench spacer 245 may be formed after the formation of the impurity region 240 described with reference to FIG. 9 or 20. More specifically, the trench spacer 245 may be formed by forming an insulating film that conformally covers the inner wall of the trench 200, and then anisotropically etching it to expose the top surfaces of the impurity regions 240. In addition, the metal pattern 255 may be formed by filling the trench 200 in which the trench spacer 245 is formed with a metal film and then etching the planarized portion thereof.

The metal pattern 255 and the trench spacer 245 may be formed to not only vertically penetrate the conductive patterns 230 but also to cross the semiconductor patterns SP horizontally. According to one embodiment, the thickness (ie, z-direction length) and length (ie, y-direction length) of the metal pattern 255 may be substantially the same as those of the trench 200.

Since the metal pattern 255 is connected to the impurity region 240 while having a lower specific resistance than the impurity region 240, the metal pattern 255 may contribute to improving a transmission speed of an electrical signal passing through the impurity regions 240. have. In addition, since the upper surface of the metal pattern 255 is located higher than the upper surface of the uppermost layer of the conductive patterns 230, the technical difficulty in the wiring forming process for electrical connection to the impurity region 240 is reduced. Can be. In addition, since the metal pattern 240 may function as a shielding layer between the conductive patterns 230, the capacitive coupling between the horizontally adjacent conductive patterns 230 may be reduced. Can be. As a result, disturbance problems in program and read operations can be alleviated.

[ Comparative Examples ]

49 and 50 are perspective views illustrating three-dimensional semiconductor devices according to comparative examples.

Punch-and-plug technology can be used to three-dimensionally implement a flash memory device having a charge storage film as a memory element. In this case, according to the formation order between the films for the information storage and the semiconductor plug used as the active region, the punch-and-plug technique is a storage-first way and a plug-first way. ) Can be separated. 49 and 50 illustrate cross-sectional views of a 3D NAND flash memory device to which a storage first method and a plug first method are applied, respectively.

As shown in FIG. 49, in the case of the storage first method, the tunnel insulating film TIL, the charge storage film CL, and the blocking insulating film BLL, which are used as memory elements, are all formed to cover the inner wall of the opening 105. On the other hand, as shown in FIG. 50, in the plug-first method, the tunnel insulating film TIL, the charge storage film CL, and the blocking insulating film BLL, which are used as memory elements, all cover the surface of the conductive pattern 230. It is formed to cover.

According to the reservoir first method, the forming of the opening 105 is performed after the deposition of the word line WL. In this case, due to the difficulty in forming the opening 105, the word line WL according to the storage first method is formed of doped polycrystalline silicon, which has a relatively high resistivity compared to metal. According to embodiments of the present invention, as described with reference to FIG. 9 or 20, the word line WL (ie, the conductive pattern 230) is formed after the opening 105 is formed. . Accordingly, in the embodiments of the present invention, the conductive pattern 230 may be formed of a metallic material without being constrained by the constraint of the storage first method.

Meanwhile, according to the plug-first method, after the recess regions 210 are formed between the insulating layers 120, the films constituting the memory element and the conductive pattern 230 are formed in the recess regions 210. It is deposited on the inner wall in turn. In this case, as shown in FIG. 50, all of the films constituting the memory element (that is, the tunnel insulating film TIL, the charge storage film CL, and the blocking insulating film BLL) may form the recess regions 210. Because of the filling, the thickness t2 of the conductive pattern 230 is reduced than the thickness t1 of the recess region 210. This reduction in thickness may cause technical problems such as an increase in the vertical distance between the conductive patterns 230 or an increase in the resistance of the conductive pattern 230, which may be intensified with an increase in the degree of integration. In contrast, according to embodiments of the present invention, since a portion of the films constituting the memory element (ie, the horizontal pattern 220) fills the recess regions 210, the plug priority method may be used. Technical problems can be suppressed.

[ Undercut  Method of Forming Region and Its Structure]

A three-dimensional semiconductor device in which the undercut region 77 defines the bottom surface of the vertical pattern 155 has been exemplarily described with reference to FIG. 24. Hereinafter, embodiments of the present invention related to the methods of forming the undercut region 77 and the structures of the three-dimensional semiconductor device will be described.

Meanwhile, the method of forming the undercut region 77 and the structure thereof, which will be described below, are not limited to the structure illustrated by way of example in FIG. 24, but the above-described three-dimensional semiconductor devices or modifications thereof are described. Can be applied to implement Nevertheless, one of ordinary skill in the art can easily apply the technical idea related to the undercut area 77 to be described below for an extended implementation of the embodiments described above. The description for such an extended implementation is omitted. In addition, each of the manufacturing methods to be described below may be applied in place of the steps of the manufacturing method described with reference to FIGS. 3 to 6 or 13 and 14, except for these steps. Subsequent steps (eg, steps described with reference to FIGS. 7-11 or 15-21) or variations thereof may be performed.

51 to 64 are cross-sectional views illustrating specific embodiments of forming the undercut area 77 described with reference to FIG. 24. More specifically, FIGS. 51 to 54 show a first embodiment of forming the undercut region 77, FIGS. 55 and 56 show a second embodiment of forming the undercut region 77, 57 to 62 show a third embodiment of forming the undercut region 77, and FIGS. 63 and 64 show a fourth embodiment of forming the undercut region 77. For brevity of description, in the descriptions of the second to fourth embodiments, descriptions of technical features overlapping with the first embodiment may be omitted.

Referring to FIG. 51, a mold structure 100 including an insulating layer 121 and a sacrificial layer 131 is formed on a substrate 10, and passes through the mold structure 100 to form an upper portion of the substrate 10. After forming the opening 105 to expose the surface, the vertical film 150 and the first semiconductor film 160 are sequentially formed on the inner wall of the opening 105.

The mold structure 100 may be substantially the same as that of the embodiment described with reference to FIG. 1. In other words, the insulating layer 121 and the sacrificial layer 131 illustrated exemplarily show a portion of the mold structure 100, and the mold structure 100 may include more insulating layers and sacrificial layers as shown in FIG. 1. It may include.

The opening 105 may be shaped like a hole as shown in FIG. 2 or may include a cube-shaped portion as shown in FIG. 12. According to this embodiment, while forming the opening 105, the upper surface of the substrate 10 may be recessed to a predetermined depth. In this case, the bottom surface of the opening 105 may be lower than the top surface of the substrate 10 in contact with the bottom surface of the insulating layer 121. This recess of the substrate 10 may be the result of over-etching that may be required for the stable formation of the opening 105. In addition, such a recess of the substrate 10 may be intentionally implemented because it may contribute to improving the structural stability of the vertical pattern 155.

The vertical layer 150 and the first semiconductor layer 160 may be formed to substantially conformally cover the sidewalls and the bottom surface of the opening 105. As illustrated, the sum of the deposition thicknesses of the vertical layer 150 and the first semiconductor layer 160 may be less than half of the width of the opening 105. That is, the opening 105 may not be completely filled by the vertical film 150 and the first semiconductor film 160.

The vertical layer 150 and the first semiconductor layer 160 may be formed to form the vertical structure VS disclosed in any one of the embodiments described with reference to FIGS. 28 to 43. For example, the vertical layer 150 may include a capping layer CPL, a charge storage layer CL, and a tunnel insulating layer TIL, which are sequentially deposited as shown in FIG. 51, and each material or physical property thereof. May be substantially the same as in the embodiment described with reference to FIGS. 28-43. In addition, the first semiconductor film 160 may be a polycrystalline silicon film.

Referring to FIG. 52, a through groove for anisotropically etching the first semiconductor layer 160 and the vertical layer 150 to expose the top surface of the substrate 10 from the bottom of the opening 105. dent; PD). The forming of the through groove PD may be performed by a plasma dry etching method using the mold structure 100 as an etching mask, as described with reference to FIG. 4.

As a result of the anisotropic etching of the first semiconductor layer 160, a semiconductor spacer SP is formed to cover the inner wall of the vertical pattern 155. In addition, the through groove PD is formed to penetrate the vertical film 150 covering the bottom surface of the opening 105, and thus the vertical pattern having sidewalls exposed by the through groove PD. 155 is formed. That is, in the embodiment having the thin film structure described with reference to FIG. 51, the capping film CPL, the charge storage film CL, and the tunnel insulating film TIL pass through the bottom of the opening 105. It has sidewalls exposed by the groove PD.

Referring to FIG. 53, the exposed charge storage layer CL is isotropically etched to form a first undercut region UC1. The first undercut region UC1 may be a gap region extending from the through groove PD, and is formed to partially expose the surfaces of the capping layer CPL and the tunnel insulating layer TIL.

In example embodiments, the charge storage layer CL may be a silicon nitride layer. In this case, the first undercut region UC1 may be formed through a wet etching process using an etchant including phosphoric acid. However, according to other embodiments, the first undercut UC1 may be formed through the method of isotropic dry etching.

Referring to FIG. 54, a second undercut region is formed by isotropically etching the capping layer CPL and the tunnel insulating layer TIL exposed by the first undercut region UC1. The second undercut region may be partially covered by the capping film CPL and the tunnel insulating film TIL, and may be formed on the surface of the substrate 10 defining the opening 105 and the semiconductor spacer SP. The lower region and the bottom surface of the outer wall may be exposed to form an undercut region 77 together with the first undercut region UC1.

The forming of the second undercut region may be performed using at least one of wet etching or isotropic dry etching. In the case of the wet etching method, an etching solution containing hydrofluoric acid or sulfuric acid may be used.

Subsequently, a second semiconductor film 170 connecting the substrate 10 and the semiconductor spacer SP is formed in the undercut region 77. The second semiconductor film 170 may be a semiconductor material (eg, polycrystalline silicon) formed using one of the deposition techniques. In this case, as shown, the second semiconductor film 170 may extend from the undercut region 77 to cover the inner wall of the semiconductor spacer SP. In addition, as a result of this deposition process, the second semiconductor film 170 may have a seam 88 in the undercut region 77.

According to the second embodiment of forming the undercut region 77, the forming of the first undercut region UC1 described with reference to FIG. 53 may be performed by the capping layer CPL and the substrate as illustrated in FIG. 55. And isotropically etching the tunnel insulating film TIL. The capping layer CPL and the tunnel insulating layer TIL may be implemented using at least one of a wet etching method or an isotropic dry method. In the case of the wet etching method, an etching solution containing hydrofluoric acid or sulfuric acid may be used.

In this case, as shown in FIG. 56, the bottom surface of the charge storage film CL is further from the bottom surface of the opening 105 than the bottom surface of at least one of the capping film CPL and the tunnel insulating film TIL. Can be spaced away. In contrast, when the charge storage layer CL is first etched as shown in FIG. 53, the bottom surface of at least one of the capping layer CPL and the tunnel insulation layer TIL is stored as shown in FIG. 54. It may be spaced farther from the bottom surface of the opening 105 than the bottom surface of the film CL.

According to the third embodiment of forming the undercut region 77, as shown in FIG. 57, after forming the first semiconductor layer 160, the protective layer spacer PS is formed in the opening 105. Steps may be further performed. The passivation layer spacer PS may be formed of a material having an etch selectivity with respect to the first semiconductor layer 160. In example embodiments, the passivation layer spacer PS may be a silicon oxide layer or a silicon nitride layer formed using an atomic layer deposition technique. In addition, the passivation layer spacer PS may be formed to have a thickness thinner than half of the difference between the half of the width of the opening 105 and the sum of the deposition thicknesses of the vertical layer 150 and the first semiconductor layer 160. Can be. That is, the opening 105 may not be completely filled even by the passivation layer spacer PS.

Thereafter, a through hole PD penetrating a part of the thin films constituting the vertical layer 150 is formed. For example, as illustrated in FIG. 58, the through groove PD may be formed so that the capping layer CPL remains below it. Subsequently, as shown in FIG. 59, the semiconductor spacer SP exposed by the through groove PD is isotropically etched to form an extended undercut region UC0, and as illustrated in FIGS. 61 and 62. The undercut region 77 is completed by isotropically etching the vertical layer 150 as shown. Although FIGS. 61 and 62 exemplarily illustrate an embodiment to which the method described with reference to FIG. 53 is applied, the undercut area 77 is the first and second implementations described with reference to FIGS. 51 to 56. It can be formed using manufacturing methods according to one of the examples. In addition, the passivation layer spacer PS may be removed during isotropic etching of the vertical layer 150. For example, when the passivation layer spacer PS is formed of a silicon nitride layer, the passivation layer PS may be removed by etching the charge storage layer CL described with reference to FIG. 53. Alternatively, when the passivation layer spacer PS is formed of a silicon oxide layer, the passivation layer TIL and the capping layer CPL described with reference to FIG. 54 may be removed.

On the other hand, the height difference between the bottom surface of the vertical pattern 155 and the semiconductor spacer SP by the extended undercut region UC0 is the first and second described with reference to FIGS. 54 and 56. It can be reduced than that of the embodiments. That is, as shown in FIG. 62, the undercut area 77 can be expanded than that of the first and second embodiments described with reference to FIGS. 54 and 56. Such expansion of the undercut region 77 may make it easier for the second semiconductor film 170 to conformally cover the inner wall of the undercut region 77. In addition, due to such expansion of the undercut region 77, voids 89 not completely filled by the second semiconductor film 170 may be formed in the undercut region 77.

In some embodiments, the undercut regions 77 may be formed to expose the upper surface of the substrate 10 through the vertical layer 150. In this case, as shown in FIG. 63, the upper surface of the substrate 10 exposed by the through groove PD is etched together while forming the extended undercut region UC0, thereby forming the vertical pattern 155. An extended through groove PDe may be formed under the). Similar to the third embodiment described above, the void 89 may be formed in the second semiconductor film 170, and the void 89 is formed in the undercut region 77. ) And a lower gap 89b formed in the extended through groove PDe. According to modified embodiments, the void 89 may be completely or partially filled with an insulating material (eg, silicon oxide film).

According to the modified embodiments, after the second semiconductor film 170 is formed, a recrystallization process may be further performed on the semiconductor spacer SP and the second semiconductor film 170. The density of crystal defects in the semiconductor spacer SP and the second semiconductor film 170 may be reduced by the recrystallization process. For example, when the semiconductor spacer SP and the second semiconductor film 170 are formed of polycrystalline silicon, the recrystallization process may increase their grain size or single crystallize their crystal structure. . The recrystallization process may be carried out using at least one of heat treatment techniques, laser annealing techniques and epitaxial techniques. Nevertheless, when the substrate 10 is a single crystal wafer, on the average, the substrate 10 may have fewer crystal defects than the semiconductor spacer SP and the second semiconductor film 170.

65 and 66 are cross-sectional views for comparing and explaining three-dimensional semiconductor devices according to example embodiments. More specifically, FIGS. 65 and 66 show current paths in the three-dimensional semiconductor device described with reference to FIGS. 1 through 21 and the three-dimensional semiconductor device described with reference to FIGS. 51 through 64.

As shown in FIG. 65, in the case of the three-dimensional semiconductor device described with reference to FIGS. 1 through 21, because of the existence of the vertical pattern 155 inserted into the upper surface of the substrate 10 to a predetermined depth, the The current path P1 via the impurity region 240 becomes long. In addition, although the inversion region is required to be generated in the substrate 10 to complete the current path P1, the vertical pattern 155 prevents the generation of the inversion region. In particular, since the inversion region is formed by the voltage applied to the bottom conductive line 230, the resistance of the inversion region increases exponentially as the linear distance from the bottom conductive line 230 increases. According to the inventors' simulation, the resistance increased by 1010 times when the depth of the vertical pattern 155 inserted into the substrate 10 increased from 0 nm to 70 nm.

On the other hand, as shown in FIG. 66, since the second semiconductor film 170 or the semiconductor body portion 175 may be formed adjacent to the lowermost conductive line 230 by the undercut region 77, The current path P2 may be implemented adjacent to the lower conductive line 230 compared to the current path P1 shown in FIG. 65. Accordingly, according to this embodiment, the length of the current path as in the current path P1 and the exponential increase in the electrical resistance can be prevented.

67 is a block diagram schematically illustrating an example of a memory card 1200 including a flash memory device according to the present invention. Referring to FIG. 67, a memory card 1200 for supporting a high capacity of data storage capability includes a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 includes a data exchange protocol of a host that is connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs various control operations for exchanging data of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

According to the flash memory device and the memory card or the memory system of the present invention, it is possible to provide a highly reliable memory system through the flash memory device 1210 with improved erase characteristics of the dummy cells. In particular, the flash memory device of the present invention may be provided in a memory system such as a solid state disk (SSD) device which is actively progressed recently. In this case, a reliable memory system can be implemented by blocking a read error caused by the dummy cell.

68 is a block diagram schematically illustrating an information processing system 1300 incorporating a flash memory system 1310 according to the present invention. Referring to FIG. 68, the flash memory system 1310 of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. The information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 electrically connected to a system bus 1360, respectively. It includes. The flash memory system 1310 may be configured substantially the same as the above-described memory system or flash memory system. The flash memory system 1310 stores data processed by the CPU 1330 or data externally input. In this case, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store a large amount of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention may be further provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. Self-explanatory to those who have learned.

In addition, the flash memory device or the memory system according to the present invention may be mounted in various types of packages. For example, a flash memory device or a memory system according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline ( SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer- It can be packaged and mounted in the same manner as Level Processed Stack Package (WSP).

100 mold structure 105/106 opening
120 insulating film 130 sacrificial film
155 Vertical Patterns 165 Semiconductor Spacers
175 semiconductor body 185 buried pattern
200 trench 220 horizontal patterns
230 conductive pattern 240 impurity region
BIL1 / 2 Blocking Insulation CPL Capping Film
CL charge storage film HS horizontal structure
SP semiconductor pattern TIL tunnel insulating film
VS Vertical Structure 255 Metal Pattern

Claims (10)

Forming a mold structure on the substrate;
Forming an opening penetrating the mold structure to recess the upper surface of the substrate to a predetermined depth;
Sequentially forming a vertical film and a first semiconductor film covering the inner wall of the opening;
Forming a through hole through the first semiconductor layer and the vertical layer at the bottom of the opening to expose the upper surface of the substrate again;
Isotropically etching the vertical film exposed through the through groove to form an undercut region exposing sidewalls of the substrate recessed by the opening; And
And forming a second semiconductor film connecting the substrate and the first semiconductor film in the undercut region. The method according to claim 1,
The vertical film and the first semiconductor film, in turn, are formed to cover a substantially conformal thickness of the inner wall of the opening, and the sum of the deposition thicknesses of the vertical film and the first semiconductor film is less than half the width of the opening. Small,
Forming the through grooves
Anisotropically etching the first semiconductor layer to form a semiconductor spacer exposing an upper surface of the vertical layer at the bottom of the opening; And
Anisotropically etching the vertical film exposed by the semiconductor spacer. The method according to claim 2,
The forming of the through groove further includes forming a passivation layer spacer exposing a bottom surface of the first semiconductor layer on an inner sidewall of the first semiconductor layer before anisotropically etching the first semiconductor layer.
The passivation layer spacer is formed of a material having an etching selectivity with respect to the first semiconductor layer, and is formed to a thickness thinner than half of the difference between the half of the opening width and the sum of the deposition thicknesses of the vertical layer and the first semiconductor layer. The manufacturing method of a three-dimensional semiconductor device. The method according to claim 3,
And isotropically etching the first semiconductor film using the passivation layer spacer as an etch mask before forming the undercut region. The method according to claim 3,
And the protective film spacer is removed during the forming of the undercut region. The method according to claim 1,
The vertical layer may include a capping layer, a charge storage layer, and a tunnel layer that sequentially cover an inner wall of the opening.
Forming the undercut region is
Isotropically etching the charge storage film exposed by the through groove to form a first undercut region exposing the capping film and the tunnel film; And
Isotropically etching the capping film and the tunnel film exposed by the first undercut region to form a second undercut region. The method according to claim 1,
The vertical layer may include a capping layer, a charge storage layer, and a tunnel layer that sequentially cover an inner wall of the opening.
Forming the undercut region is
Isotropically etching the tunnel film and the capping film exposed by the through groove to form a first undercut region exposing the charge storage film; And
Isotropically etching the charge storage layer exposed by the first undercut region to form a second undercut region. A conductive structure disposed on the substrate, including conductive patterns stacked in turn;
A semiconductor pattern penetrating the conductive structure and inserted into an upper surface of the substrate; And
An insulating film structure interposed between the semiconductor pattern and the conductive structure,
And the semiconductor pattern extends horizontally below the insulating film structure to directly contact the sidewall of the substrate. The method according to claim 8,
And the substrate comprises a semiconductor material having fewer crystal defects than the semiconductor pattern. The method according to claim 8,
The semiconductor pattern includes a semiconductor spacer covering an inner wall of the insulating film structure and a semiconductor body portion covering an inner wall of the semiconductor spacer,
The bottom surface of the semiconductor spacer is inserted deeper into the substrate than the bottom surface of the insulating film structure, the semiconductor body portion extends horizontally below the insulating film structure to directly contact the sidewall of the substrate.

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