KR20110100840A - Organic light emitting diode display device - Google Patents

Organic light emitting diode display device Download PDF

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KR20110100840A
KR20110100840A KR1020100019880A KR20100019880A KR20110100840A KR 20110100840 A KR20110100840 A KR 20110100840A KR 1020100019880 A KR1020100019880 A KR 1020100019880A KR 20100019880 A KR20100019880 A KR 20100019880A KR 20110100840 A KR20110100840 A KR 20110100840A
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data
light emitting
line
driver
lines
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KR1020100019880A
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Korean (ko)
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KR101642995B1 (en
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김중철
이지노
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엘지디스플레이 주식회사
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Abstract

The present invention relates to an organic light emitting diode display device, comprising: a display panel including data lines and gate lines intersecting a plurality of light emitting cells; A data driver converting digital video data into a data voltage to be supplied to the data ladle; A gate driver configured to output scan pulses to be sequentially supplied to the gate lines; A data distribution unit connected between the data driver and the data lines to time-divisionally supply data voltages output from the data driver to a plurality of data lines; And a timing controller configured to generate control signals for controlling operation timing of the data driver, the gate driver, and the data distributor, and to supply the digital video data to the data driver. The pulse width of the scan pulse is wider than that of the control signal of the data distributor.

Description

Organic light emitting diode display device {ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE}

The present invention relates to an organic light emitting diode display.

Various flat panel displays (FPDs) are being developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs") and electric fields. Light emitting devices; and the like.

Electroluminescent devices are classified into inorganic electroluminescent devices and organic light emitting diode devices (OLEDs) according to the material of the light emitting layer, and emit light by themselves. Viewing angle has a big advantage.

The organic light emitting diode display may be driven by a driving method such as voltage driving, voltage compensation, current driving, digital driving, or external compensation, and in recent years, a voltage compensation driving method is most frequently selected. The organic light emitting diode display is being developed as an active matrix to realize large area high resolution.

The organic light emitting diode display of the active matrix type is driving the OLED by using a plurality of TFTs (Thin (Thin Film Transistor, hereinafter referred to as "TFT")) which serves as a switching element and a driving element for driving the OLED. In the active matrix type organic light emitting diode display device, since the electrical characteristics of the TFTs are not uniform, the threshold voltages of the TFTs (hereinafter referred to as "drive TFTs") used as driving elements are compensated. The threshold voltage of the driving TFT should be accurately detected by storing it in a storage capacitor for a sufficient time, but the higher the resolution and the higher the driving frequency of the active matrix organic light emitting diode display, the shorter the horizontal period is, the lower the threshold of the driving TFT. It is difficult to secure time for sensing voltage.

The present invention provides an organic light emitting diode display device capable of sufficiently securing time for detecting a threshold voltage of a driving TFT even if the display panel has a higher resolution and a higher driving frequency.

An organic light emitting diode display according to an embodiment of the present invention comprises: a display panel in which data lines and gate lines intersect each other and include a plurality of light emitting cells; A data driver converting digital video data into a data voltage to be supplied to the data ladle; A gate driver configured to output scan pulses to be sequentially supplied to the gate lines; A data distribution unit connected between the data driver and the data lines to time-divisionally supply data voltages output from the data driver to a plurality of data lines; And a timing controller configured to generate control signals for controlling operation timing of the data driver, the gate driver, and the data distributor, and to supply the digital video data to the data driver.

The pulse width of the scan pulse is wider than that of the control signal of the data distributor.

According to the present invention, a data distribution unit is disposed between the data driver and the display panel of the organic light emitting diode display, and the pulse width of the scan pulse is controlled to be wider than that of the control signal of the data distribution unit. As a result, the present invention can secure the detection time of the driving TFT sufficiently even when the resolution of the organic light emitting diode display device is increased or the driving frequency is increased, thereby accurately compensating the threshold voltage deviation of the driving TFT.

1 is a block diagram illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating a light emitting cell of the display panel shown in FIG. 1.
3 is a waveform diagram illustrating output waveforms of the gate driver illustrated in FIG. 1.
4 is a waveform diagram showing one horizontal period depending on resolution and driving frequency.
5 is a circuit diagram illustrating a first embodiment of a data distributor and a display panel.
FIG. 6 is a waveform diagram illustrating control signals and scan pulses of the data distributor of FIG. 5.
7 is a circuit diagram illustrating a second embodiment of a data distributor and a display panel.
FIG. 8 is a waveform diagram illustrating a control signal and a scan pulse of the data distributor of FIG. 7.
9 is a waveform diagram illustrating a threshold voltage detection period of a driving TFT in a conventional organic light emitting diode display.
FIG. 10 is a waveform diagram illustrating an extended threshold voltage detection period of a driving TFT in an organic light emitting diode display including a data distribution unit and a display panel as shown in FIGS. 5 and 6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The names of the components used in the following description are selected in consideration of the ease of preparation of the specification, and may be different from the names of the actual products.

1 and 2, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 100, a timing controller 110, a data driver 120, a data distributor 130, and a gate driver ( 140) and the like.

In the display panel 100, the data lines 101 and the gate lines 102 cross each other, and the light emitting cells 10 as illustrated in FIG. 2 are arranged in a matrix form.

The timing controller 110 supplies digital video data RGB to the data driver 120. The timing controller 101 uses the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync, the data enable signal Data Enable (DE), the dot clock CLK, and the like to input the data driver 120, Timing control signals DCS, M1 to Mn, and GCS for controlling the operation timing of the data distributor 130 and the gate driver 140 are generated.

The data driver 120 converts the digital video data RGB into a gamma compensation voltage under the control of the timing controller 101 and supplies it to the data lines 101. The gate driver 140 sequentially supplies the initialization pulse INT, the scan pulse SCAN, and the emission control pulse EM to the gate lines 102 under the control of the timing controller 101.

The data distributor 130 time-divisionally supplies each of the data voltages output from the data driver 120 to two or more data lines 101 under the control of the timing controller 101. The data distributor 130 includes a plurality of demultiplexers (DMUX) as shown in FIGS. 5 and 7. Each of the demultiplexers DMUX connects one data driver output terminal for outputting a data voltage to N data lines 101 (N is an integer of 2 or more and 6 or less), and a control signal from the timing controller 110. It is turned on in response to (M1-Mn). FIG. 5 illustrates a demultiplexer (DMUX) for distributing one data voltage input to two data lines 101, and FIG. 5 illustrates a demultiplexer for distributing one data voltage input to three data lines 101. Illustrates (DMUX), but the demultiplexer of the present invention receives one data voltage input and divides it into two to six data lines.

Each of the light emitting cells 10 is commonly supplied with a high potential power voltage VDD, a ground voltage (or a low potential power voltage GND), a reference voltage Vref, and the like. In addition, each of the light emitting cells 10 is supplied with an initialization pulse INT, a scan pulse SCAN, and a light emission control pulse EM through the gate lines 102.

The high potential power voltage VDD may be set to a voltage of approximately 15-20V. The reference voltage Vref is less than the threshold voltage of the organic light emitting diode OLED so that the difference between the reference voltage Vref and the ground voltage GND is less than the threshold voltage of the organic light emitting diode OLED. Can be set. In addition, the reference voltage Vref may be set to a negative voltage so that a reverse bias can be applied to the organic light emitting diode OLED when the driving device connected to the organic light emitting diode OLED is initialized.

The light emitting cell 10 includes an OLED, a storage capacitor Cstg, a plurality of switch TFTs S1 to S5, and a driving TFT D-TFT.

The first switch TFT S1 is turned on in response to the initialization pulse input through the first gate line 102 to supply the reference voltage Vref to the fourth node n4 to supply the reference voltage Vref to the fourth node n4. Initialize the voltage to the reference voltage (Vref). The source electrode of the first switch TFT S1 is connected to the fourth node n4, and the drain electrode thereof is connected to the reference voltage source Vref via the fifth node n5. The gate electrode of the first switch TFT S1 is connected to the first gate line 102 to which the initialization pulse INI is supplied.

The second switch TFT S2 is turned on in response to the scan pulse SCAN input through the second gate line 102 to supply the data voltage Data to the first node n1. The drain electrode of the second switch TFT S2 is connected to the first node n1 and its source electrode is connected to the data line 101. The gate electrode of the second switch TFT S2 is connected to the second gate line 102 to which the scan pulse SCAN is supplied.

The third switch TFT S3 is turned on in response to the scan pulse SCAN input through the second gate line 102 to form a current path between the second node n2 and the third node n3. Thus, the driving TFT (D-TFT) is operated as a diode. The source electrode of the third switch TFT S3 is connected to the third node n3, and the drain electrode thereof is connected to the second node n2. The gate electrode of the third switch TFT S3 is connected to the second gate line 102 to which the scan pulse SCAN is supplied.

The fourth switch TFT S4 is turned off in response to the emission control pulse SCAN input through the third gate line 102 to divide the current path between the first node n1 and the fifth node n5. Block it. The source electrode of the fourth switch TFT S4 is connected to the first node n1, and the drain electrode thereof is connected to the fifth node n5. The gate electrode of the fourth switch TFT S4 is connected to the third gate line 102 to which the emission control pulse EM is supplied.

The fifth switch TFT S5 is turned off in response to the emission control pulse SCAN input through the third gate line 102 to divide the current path between the third node n3 and the fourth node n4. Block it. The source electrode of the fifth switch TFT S5 is connected to the third node n3, and the drain electrode thereof is connected to the fourth node n4. The gate electrode of the fifth switch TFT S5 is connected to the third gate line 102 to which the emission control pulse EM is supplied.

The driving TFT (D-TFT) supplies the current from the high potential power supply voltage source VDD to the OLED, and controls the current to the gate-source voltage. The source electrode of the driving TFT (D-TFT) is connected to the high potential power supply voltage source VDD, and the drain electrode thereof is connected to the third node n3. The gate electrode of the driving TFT (D-TFT) is connected to the second node n2.

The switch TFTs S1 to S5 and the driving TFT D-TFT may be implemented as p-type MOSFETs (metal-oxide-semiconductor field-effect transistors).

The storage capacitor Cstg is connected between the first node n1 and the second node n2 to charge the electric charge flowing like an arrow while the second and third switch TFTs S2 and S3 are turned on. The threshold voltage of the driving TFT (D-TFT) is stored to detect the threshold voltage. The storage capacitor Cstg is connected between the first node n1 and the second node n2.

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL). The OLED emits light in accordance with the current supplied through the driving TFT DTFT1. The anode electrode of the OLED is connected to the fourth node n4, and the cathode electrode thereof is connected to the ground voltage source GND.

The operation of the light emitting cell 10 will be described step by step in conjunction with FIGS. 2 and 3.

The gate driver 14 supplies the initialization logic INI of the low logic voltage to the first gate line 102 during the first to third periods t1 to t3, and the second and third periods t1 to t2. The scan logic SCAN of the low logic voltage is supplied to the second gate line 102. The gate driver 14 supplies a light emission control pulse EM having a high logic voltage to the third gate line 102 during the third period t3. The data driver 120 supplies a data voltage synchronized with the scan pulse SCAN to the data lines 101.

The first switch TFT S1 is turned on in response to the initialization pulse INT of the low logic voltage supplied through the first gate line 102 during the first to third periods t1 to t3. The first switch TFT S1 is turned off when the voltage of the first gate line 102 is a high logic voltage. The anode voltage of the OLED is initialized to the reference voltage Vref applied through the first switch TFT S1 for the first to third periods t1 to t3.

The second and third switch TFTs S2 and S3 are turned on in response to the scan pulse SCAN of the low logic voltage supplied through the second gate line 102 during the second and third periods t2 to t3. Is on. The second and third switch TFTs S2 and S3 are turned off when the voltage of the second gate line 102 is a high logic voltage. During the second and third periods t2 to t3, the storage capacitor Cstg detects the threshold voltage of the driving TFT D-TFT by charging the difference voltage between the first node n1 and the second node n1. do. In order to compensate for the threshold voltage deviation of the driving TFT (D-TFT), the second and third periods t2 to t3 should be sufficiently long.

The fourth and fifth switch TFTs S4 and S5 are turned off in response to the scan pulse SCAN of the high logic voltage supplied through the third gate line 102 during the third period t3 to emit light of the OLED. To block. The fourth and fifth switch TFTs S4 and S5 are turned on when the voltage of the third gate line 103 is a low logic voltage. The OLED emits light after the third period t3.

The switch TFTs S1 to S5 and the driving TFT D-TFT may be implemented with n-type MOSFETs. In this case, the phases of the drive waveforms shown in FIG. 3 are inverted.

In order to compensate for the threshold voltage deviation of the driving TFT, the scan period of one scan line, that is, the second and third periods t2 to t3 at which the threshold voltage of the driving TFT is detected within one horizontal period should be sufficiently long. Here, one scan line includes one row (line) of light emitting cells 10 selected by an initialization pulse INT, a scan pulse SCAN, and an emission control pulse EM. One horizontal period becomes shorter as the driving frequency increases or the number of scan lines increases, as shown in FIG. The number of scan lines increases as the resolution increases. Therefore, when the resolution or driving frequency of the organic light emitting diode display device is increased, one horizontal period is shortened, so that the threshold voltage detection time of the driving TFT (D-TFT) is insufficient. According to the present invention, by extending the one horizontal period by using the data distributor 130, the threshold voltage detection time of the driving TFT (D-TFT) in each of the light emitting cells 10 may be sufficiently secured. This will be described in detail with reference to FIGS. 5 to 10.

5 and 6 are diagrams illustrating a first exemplary embodiment of the display panel 10 of the data distributor 130.

5 and 6, the data distributor 130 includes a plurality of demultiplexers DMUX.

Each demultiplexer (DMUX) includes one input terminal and two output terminals. The input terminal of the demultiplexer DMUX is connected to the output terminal of the data driver, and the output terminals of the demultiplexer DMUX are connected to the odd-numbered data line 101 and the even-numbered data line 101. The demultiplexer DMUX includes first and second switch TFTs T1 and T2. The first switch TFT T1 supplies the data voltage to the odd data line 101 in response to the first control signal M1. The first control signal M1 is supplied from the timing controller 110 to the gate electrode of the first switch TFT T1. The drain electrode of the first switch TFT T1 is connected to the output terminal of the data driver 120, and the source electrode thereof is connected to the odd data line 101. The second switch TFT T2 supplies the data voltage to the even-numbered data line 101 in response to the second control signal M2. The second control signal M2 is supplied from the timing controller 110 to the gate electrode of the second switch TFT T2. The drain electrode of the second switch TFT (T2) is connected to the output terminal of the data driver 120, and its source electrode is connected to the even-numbered data line 101. The first control signal M1 and the second control signal M2 are generated out of phase as shown in FIG. 6.

When the pulse widths of the control signals M1 and M2 are one horizontal period 1H, the scan pulses SCAN1 to SCAN6 have an extended horizontal period EH longer than one horizontal period 1H as shown in FIG. Can be generated. The extended horizontal period EH may be set to one horizontal period 1H or more, for example, two horizontal periods. n (n is a positive integer) th scan pulses (SCANn) overlap with the back of the n-1 th scan pulse (SCANn-1), and overlap with the front part of the n + 1 th scan pulse (SCANn + 1) do.

The light emitting cells 10 disposed in the radix-th display lines LINE # 1, LINE # 3, and LINE # 5 of the display panel 10 are connected to the radix-th data line 101. The light emitting cells 10 disposed in the even-numbered display lines LINE # 2, LINE # 4, and LINE # 6 of the display panel 10 are connected to the even-numbered data line 101. The light emitting cells 10 of the odd-numbered display lines LINE # 1, LINE # 3, and LINE # 5 have a threshold voltage of the driving TFT D-TFT in response to the extended scan pulses SCAN1, SCAN3, and SCAN5. Is sensed and the data voltage is input through the first switch TFT T1 of the demultiplexer DMUX and the odd-numbered data lines 101. The light emitting cells 10 of the even-numbered display lines LINE # 2, LINE # 4, and LINE # 6 have a threshold voltage of the driving TFT D-TFT in response to the extended scan pulses SCAN2, SCAN4, and SCAN6. Is sensed and the data voltage is input through the second switch TFT T2 of the demultiplexer DMUX and the even-numbered data lines 101.

7 and 8 illustrate a second exemplary embodiment of the display panel 10 of the data distributor 130.

7 and 8, each of the demultiplexer DMUX of the data distributor 130 includes one input terminal and three output terminals. The input terminal of the demultiplexer DMUX is connected to the output terminal of the data driver 120, and the output terminal of the demultiplexer DMUX is 3i (i is a positive integer) + 1st data line 101, 3i + 2nd data. Line 101 and the 3i + 3 th data line 101. The demultiplexer DMUX includes first to third switch TFTs T1 to T3. The first switch TFT T1 supplies the data voltage input through the output terminal of the data driver 120 to the 3i + 1th data line 101 in response to the first control signal M1. The first control signal M1 is supplied from the timing controller 110 to the gate electrode of the first switch TFT T1. The drain electrode of the first switch TFT (T1) is connected to the output terminal of the data driver 120, and its source electrode is connected to the 3i + 1th data line 101. The second switch TFT T2 supplies the data voltage to the 3i + 2th data line 101 in response to the second control signal M2. The second control signal M2 is supplied from the timing controller 110 to the gate electrode of the second switch TFT T2. The drain electrode of the second switch TFT (T2) is connected to the output terminal of the data driver 120, and the source electrode thereof is connected to the 3i + 2th data line 101. The third switch TFT T3 supplies the data voltage to the 3i + 3 th data line 101 in response to the third control signal M3. The third control signal M3 is supplied from the timing controller 110 to the gate electrode of the third switch TFT T3. The drain electrode of the third switch TFT T3 is connected to the output terminal of the data driver 120, and the source electrode thereof is connected to the 3i + 3th data line 101. The timing controller 110 generates the first to third control signals M1 to M3 as pulses whose phases are sequentially delayed as shown in FIG. 8.

When the pulse widths of the control signals M1 to M3 are one horizontal period 1H, the scan pulses SCAN1 to SCAN6 have an extended horizontal period EH longer than one horizontal period 1H as shown in FIG. Can be generated. The extended horizontal period EH may be set longer than, for example, three horizontal periods than the first embodiment described above. The n th scan pulses SCANn overlap with the rear part of the n-2 th and n-1 th scan pulses SCANn-2 and SCANn-1, and the n + 1 th and n + 2 th scan pulses SCANn. +1, overlapping with the front part of SCANn + 2).

The light emitting cells 10 disposed on the 3i + 1th display lines LINE # 1 and LINE # 4 of the display panel 10 are connected to the 3i + 1 data line 101. The light emitting cells 10 disposed on the 3i + 2th display lines LINE # 2 and LINE # 5 of the display panel 10 are connected to the 3i + 2 data line 101. The light emitting cells 10 disposed on the 3i + 3th display lines LINE # 3 and LINE # 6 of the display panel 10 are connected to the 3i + 3 data line 101. The light emitting cells 10 of the 3i + 1th display lines LINE # 1 and LINE # 4 detect the threshold voltage of the driving TFT D-TFT in response to the extended scan pulses SCAN1 and SCAN4 and demultiplexer. The data voltage is received through the first switch TFT T1 of the DMUX and the 3i + 1th data lines 101. The light emitting cells 10 of the 3i + 1th display lines LINE # 2 and LINE # 5 detect the threshold voltage of the driving TFT D-TFT in response to the extended scan pulses SCAN2 and SCAN5 and demultiplexer. The data voltage is received through the second switch TFT T2 of the DMUX and the 3i + 2 th data lines 101. The light emitting cells 10 of the 3i + 3th display lines LINE # 3 and LINE # 6 detect the threshold voltage of the driving TFT D-TFT in response to the extended scan pulses SCAN3 and SCAN6 and demultiplexer. The data voltage is input through the third switch TFT T4 of the DMUX and the 3i + 3 th data lines 101.

The data distributor 130 is not limited to FIGS. 5 to 7. For example, although not shown, the demultiplexer DMUX of the data distributor 130 may be implemented as a 1: 4, 1: 5, or 1: 6 demultiplexer.

For example, the 1: 4 demultiplexer DMUX includes first to fourth switch TFTs to time-division supply the data voltage into four data lines. The first switch TFT supplies the data voltage to the 4i + 1th data line 101 in response to the first control signal M1. The second switch TFT supplies the data voltage to the 4i + 2th data line 101 in response to the second control signal M2. The third switch TFT supplies the data voltage to the 4i + 3th data line 101 in response to the third control signal M3. The fourth switch TFT supplies the data voltage to the 4i + 4th data line 101 in response to the fourth control signal M4. The timing controller 110 generates the first to fourth control signals M1 to M4 as pulses whose phases are sequentially delayed. When the pulse widths of the control signals M1 to M4 are one horizontal period 1H, the scan pulses SCAN1 to SCAN6 may be set to be longer than, for example, four horizontal periods. have. The n th scan pulses SCANn overlap with the rear part of the n-3 th to n-1 th scan pulses SCANn-1 to SCANn-3, and the n + 1 th to n + 3 th scan pulses SCANn. Overlap +1 ~ SCANn + 3). When the data distribution unit 13 is implemented as a 1: 4 demultiplexer, the light emitting cells 10 disposed on the 4i + 1th display lines LINE # 1 and LINE # 5 may have a 4i + 1 data line 101. ) Is connected. The light emitting cells 10 disposed on the 4i + 2th display lines LINE # 2 and LINE # 6 are connected to the 4i + 2 data line 101. The light emitting cells 10 arranged on the 4i + 3th display lines LINE # 3 and LINE # 7 are connected to the 4i + 3 data line 101. The light emitting cells 10 arranged on the 4i + 4th display lines LINE # 4 and LINE # 8 are connected to the 4i + 4 data line 101.

The 1: 5 demultiplexer DMUX includes first to fifth switch TFTs to time-division supply the data voltage to five data lines. The first switch TFT supplies the data voltage to the 5i + 1th data line 101 in response to the first control signal M1. The second switch TFT supplies the data voltage to the 5i + 2th data line 101 in response to the second control signal M2. The third switch TFT supplies the data voltage to the 5i + 3th data line 101 in response to the third control signal M3. The fourth switch TFT supplies the data voltage to the 5i + 4th data line 101 in response to the fourth control signal M4. The fifth switch TFT supplies the data voltage to the 5i + 5th data line 101 in response to the fifth control signal M5. The timing controller 110 generates the first to fifth control signals M1 to M5 as pulses whose phases are sequentially delayed. When the pulse widths of the control signals M1 to M5 are one horizontal period 1H, the scan pulses SCAN1 to SCAN6 may be set to longer than, for example, five horizontal periods. have. The n th scan pulses SCANn overlap with the rear part of the n-4 th to n-1 th scan pulses SCANn-1 to SCANn-4, and the n + 1 th to n + 4 th scan pulses SCANn. It overlaps with the front part of +1 ~ SCANn + 4). When the data distribution unit 13 is implemented as a 1: 5 demultiplexer, the light emitting cells 10 disposed on the 5i + 1th display lines LINE # 1 and LINE # 6 are 5i + 1 data lines 101. ) Is connected. The light emitting cells 10 disposed on the 5i + 2th display lines LINE # 2 and LINE # 7 are connected to the 5i + 2 data line 101. The light emitting cells 10 arranged on the 5i + 3th display lines LINE # 3 and LINE # 8 are connected to the 5i + 3 data line 101. The light emitting cells 10 disposed on the 5i + 4th display lines LINE # 4 and LINE # 9 are connected to the 5i + 4 data line 101. The light emitting cells 10 disposed on the 5i + 5th display lines LINE # 5 and LINE # 10 are connected to the 5i + 5 data line 101.

The 1: 6 demultiplexer DMUX includes first to sixth switch TFTs to time-division supply the data voltage into six data lines. The first switch TFT supplies the data voltage to the 6i + 1th data line 101 in response to the first control signal M1. The second switch TFT supplies the data voltage to the 6i + 2th data line 101 in response to the second control signal M2. The third switch TFT supplies the data voltage to the 6i + 3th data line 101 in response to the third control signal M3. The fourth switch TFT supplies the data voltage to the 6i + 4th data line 101 in response to the fourth control signal M4. The fifth switch TFT supplies the data voltage to the 6i + 5th data line 101 in response to the fifth control signal M5. The sixth switch TFT supplies the data voltage to the 6i + 6th data line 101 in response to the sixth control signal M6. The timing controller 110 generates the first to sixth control signals M1 to M6 as pulses whose phases are sequentially delayed. When the pulse widths of the control signals M1 to M6 are one horizontal period 1H, the scan pulses SCAN1 to SCAN6 may be set to longer than, for example, six horizontal periods. have. The n th scan pulses SCANn overlap with the rear part of the n-5 th to n-1 th scan pulses SCANn-1 to SCANn-5, and the n + 1 th to n + 5 th scan pulses SCANn. It overlaps with the front part of +1 ~ SCANn + 4). When the data distribution unit 13 is implemented as a 1: 6 demultiplexer, the light emitting cells 10 disposed on the 5i + 1th display lines LINE # 1 and LINE # 7 are 6i + 1 data lines 101. ) Is connected. The light emitting cells 10 disposed on the 6i + 2th display lines LINE # 2 and LINE # 8 are connected to the 6i + 2 data line 101. The light emitting cells 10 disposed on the 6i + 3th display lines LINE # 3 and LINE # 9 are connected to the 6i + 3 data line 101. The light emitting cells 10 disposed on the 6i + 4th display lines LINE # 4 and LINE # 10 are connected to the 6i + 4 data line 101. The light emitting cells 10 disposed on the 6i + 5th display lines LINE # 5 and LINE # 11 are connected to the 6i + 5 data line 101. The light emitting cells 10 disposed on the 6i + 6th display lines LINE # 6 and LINE # 12 are connected to the 6i + 6 data line 101.

9 and 10 are waveform diagrams showing waveforms measured in an experiment comparing scan times of a conventional organic light emitting diode display and an organic light emitting diode display of the present invention. 9 is a waveform diagram illustrating a detection period of a threshold voltage of a driving TFT in a conventional organic light emitting diode display, and FIG. 10 is driven in an organic light emitting diode display including a data distribution unit and a display panel as shown in FIGS. 5 and 6. The waveform diagram shows the extended threshold voltage detection period of the TFT.

9 and 10, the data distributing unit 130 is disposed between the data driver 120 and the display panel 10, and the pulse width of the scan pulse is controlled by the data distributing unit 130. It's wider than that. Therefore, the present invention can sufficiently compensate for the detection time of the driving TFT even when the resolution of the organic light emitting diode display device is increased or the driving frequency is increased, thereby accurately compensating the threshold voltage deviation of the driving TFT.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: light emitting cell 100: display panel
110: timing controller 120: data driver
130: data distribution unit 140: gate driver

Claims (6)

A display panel intersecting the data lines and the gate lines and including a plurality of light emitting cells;
A data driver converting digital video data into a data voltage to be supplied to the data ladle;
A gate driver configured to output scan pulses to be sequentially supplied to the gate lines;
A data distribution unit connected between the data driver and the data lines to time-divisionally supply data voltages output from the data driver to a plurality of data lines; And
A timing controller configured to generate control signals for controlling operation timing of the data driver, the gate driver, and the data distributor, and to supply the digital video data to the data driver;
And the pulse width of the scan pulse is wider than that of the control signal of the data distribution unit. The method of claim 1,
The data distribution unit,
Includes a number of demultiplexers,
Each of the demultiplexers includes one input terminal connected to one output terminal of the data driver, and N output terminals 1: 1 connected to N data lines (N is an integer of 2 to 6). An organic light emitting diode display device comprising: The method of claim 2,
The demultiplexer,
A first switch TFT for supplying the data voltage input from an output terminal of the data driver to a first data line; And
A second switch TFT configured to supply the data voltage input from an output terminal of the data driver to a second data line,
And the timing controller generates a first control signal for controlling the first switch TFT and a second control signal for controlling the second switch TFT in reverse phase. The method of claim 3, wherein
The light emitting cells arranged on the odd display line of the display panel are connected to the odd data lines.
And light emitting cells arranged on even-numbered display lines of the display panel are connected to even-numbered data lines. The method of claim 2,
The demultiplexer,
A first switch TFT for supplying the data voltage input from an output terminal of the data driver to a first data line;
A second switch TFT for supplying the data voltage input from an output terminal of the data driver to a second data line;
A third switch TFT for supplying the data voltage input from an output terminal of the data driver to a third data line;
The timing controller sequentially generates a first control signal for controlling the first switch TFT, a second control signal for controlling the second switch TFT, and a third control signal for controlling the third switch TFT. An organic light emitting diode display, characterized in that. The method of claim 5, wherein
The light emitting cells arranged on 3i + i th display line of the display panel are connected to 3i + 1 th data lines,
The light emitting cells arranged on the 3i + 2th display line of the display panel are connected to the 32 + 1th data lines.
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