KR101642995B1 - Organic light emitting diode display device - Google Patents

Organic light emitting diode display device Download PDF

Info

Publication number
KR101642995B1
KR101642995B1 KR1020100019880A KR20100019880A KR101642995B1 KR 101642995 B1 KR101642995 B1 KR 101642995B1 KR 1020100019880 A KR1020100019880 A KR 1020100019880A KR 20100019880 A KR20100019880 A KR 20100019880A KR 101642995 B1 KR101642995 B1 KR 101642995B1
Authority
KR
South Korea
Prior art keywords
data
node
light emitting
line
gate
Prior art date
Application number
KR1020100019880A
Other languages
Korean (ko)
Other versions
KR20110100840A (en
Inventor
김중철
이지노
Original Assignee
엘지디스플레이 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지디스플레이 주식회사 filed Critical 엘지디스플레이 주식회사
Priority to KR1020100019880A priority Critical patent/KR101642995B1/en
Publication of KR20110100840A publication Critical patent/KR20110100840A/en
Application granted granted Critical
Publication of KR101642995B1 publication Critical patent/KR101642995B1/en

Links

Images

Abstract

The present invention relates to an organic light emitting diode display. The display device includes a display panel in which data lines and gate lines are crossed and includes a plurality of light emitting cells, a data driver for converting digital video data into data voltages to be supplied to the data lines, After supplying a reset pulse of a first voltage level to the first gate line during the third period and supplying a scan pulse of the first voltage level to the second gate line during the second and third periods, A gate driver for supplying a light emission control pulse of a voltage level to a third gate line, a data distributor connected between the data driver and the data lines for supplying the data voltage output from the data driver to the plurality of data lines in a time- And control signals for controlling the operation timings of the data driver, the gate driver, and the data distributor And a timing controller for supplying the digital video data to the data driver. The pulse width of the scan pulse is wider than that of the control signal of the data distributor.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display.

Various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (CRTs). Such a flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) And a light emitting device (Electroluminescence Device).

An electroluminescent device is a self-luminous device which is divided into an inorganic electroluminescent device and an organic light emitting diode (OLED) according to the material of the light emitting layer and emits self-luminous elements. The electroluminescent device has a high response speed, There is an advantage of a large viewing angle.

The organic light emitting diode display device can be driven by driving methods such as voltage driving, voltage compensation, current driving, digital driving, and external compensation, and in recent years, voltage compensation driving methods have been selected the most. An organic light emitting diode (OLED) display device is being developed as an active matrix in order to realize a large-area high resolution.

An active matrix type organic light emitting diode display device drives an OLED using a plurality of TFTs (Thin Film Transistors, hereinafter referred to as "TFTs ") serving as switching elements and driving elements for driving OLEDs. In the active matrix type organic light emitting diode display device, since the electrical characteristics of the TFTs are not uniform, the threshold voltage of a TFT used as a driving device (hereinafter referred to as a "driving TFT") is compensated. The threshold voltage of the driving TFT must be precisely detected by storing the threshold voltage of the driving TFT in the storage capacitor for a sufficient period of time. However, as the resolution of the active matrix type organic light emitting diode display device is increased and the driving frequency is increased, It is difficult to secure a time for detecting the voltage.

The present invention provides an organic light emitting diode display device capable of sufficiently securing a time for sensing a threshold voltage of a driving TFT even if the resolution of the display panel is increased and the driving frequency is increased.

The organic light emitting diode display device of the present invention includes a display panel in which data lines and gate lines intersect and includes a plurality of light emitting cells, a data driver for converting digital video data into data voltages to be supplied to the data lines, Supplying a reset pulse of a first voltage level to the first gate line during the first to third periods and supplying a scan pulse of the first voltage level to the second gate line during the second and third periods, A gate driver for supplying a light emission control pulse of a second voltage level to the third gate line during a period of three to three periods, a gate driver connected between the data driver and the data lines to time-division the data voltage output from the data driver into a plurality of data lines And a timing controller for controlling the timing of operation of the data driver, the gate driver, and the data distributor, Generate control signals to, and a timing controller which supplies the digital video data to the data driver.
Wherein each of the light emitting cells includes an organic light emitting diode element, a driving TFT, a plurality of switch TFTs, and a capacitor, a threshold voltage of the driver TFT is sensed during the second and third periods, 1 voltage level, and is turned off in response to the second voltage level.

The pulse width of the scan pulse is wider than that of the control signal of the data distributor.

A data distributor is disposed between a data driver and a display panel of an organic light emitting diode display device and controls the pulse width of the scan pulse to be wider than that of the control signal of the data distributor. As a result, since the detection time of the driving TFT can be sufficiently secured even when the resolution of the organic light emitting diode display device is increased or the driving frequency is increased, the threshold voltage deviation of the driving TFT can be precisely compensated.

1 is a block diagram showing an organic light emitting diode display device according to an embodiment of the present invention.
2 is a circuit diagram showing a light emitting cell of the display panel shown in Fig.
3 is a waveform diagram showing output waveforms of the gate driver shown in FIG.
4 is a waveform diagram showing one horizontal period depending on the resolution and the driving frequency.
5 is a circuit diagram showing a first embodiment of a data distribution unit and a display panel.
6 is a waveform diagram showing a control signal and a scan pulse of the data distributor shown in FIG.
7 is a circuit diagram showing a second embodiment of the data distribution unit and the display panel.
8 is a waveform diagram showing a control signal and a scan pulse of the data distributor shown in FIG.
9 is a waveform diagram showing a threshold voltage sensing period of a driving TFT in a conventional organic light emitting diode display device.
FIG. 10 is a waveform diagram showing an extended threshold voltage sensing period of a driving TFT in an organic light emitting diode display device including a data distribution unit and a display panel as shown in FIGS. 5 and 6. FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

1 and 2, an OLED display according to an exemplary embodiment of the present invention includes a display panel 100, a timing controller 110, a data driver 120, a data distributor 130, a gate driver 130, 140, and the like.

The data lines 101 and the gate lines 102 are intersected with each other in the display panel 100 and the light emitting cells 10 as shown in FIG. 2 are arranged in a matrix form.

The timing controller 110 supplies digital video data (RGB) to the data driver 120. The timing controller 101 is connected to the data driver 120, the data driver 120 and the data driver 120 using a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a dot clock CLK, (DCS, M1 to Mn, and GCS) for controlling the operation timings of the data driver 130, the data distributor 130, and the gate driver 140.

The data driver 120 converts the digital video data RGB into a gamma compensation voltage under the control of the timing controller 101 and supplies the gamma compensation voltage to the data lines 101. The gate driver 140 sequentially supplies the initialization pulse INT, the scan pulse SCAN and the emission control pulse EM to the gate lines 102 as shown in FIG. 3 under the control of the timing controller 101.

The data distributor 130 time-divides each of the data voltages output from the data driver 120 into two or more data lines 101 under the control of the timing controller 101. The data distribution unit 130 includes a plurality of demultiplexers (DMUX) as shown in FIG. 5 and FIG. Each of the demultiplexers DMUX connects one data driver output terminal to which data voltages are output to N (where N is an integer of 2 or more and 6 or less) data lines 101, and receives a control signal from the timing controller 110 (M1 to Mn). FIG. 5 illustrates a demultiplexer (DMUX) for distributing one data voltage input to two data lines 101, and FIG. 5 illustrates a demultiplexer (DMUX) for distributing one data voltage input to three data lines 101. FIG. (DMUX), the demultiplexer of the present invention receives one data voltage input and distributes it to two to six data lines.

As shown in FIG. 2, each of the light emitting cells 10 is commonly supplied with a high-potential power supply voltage VDD, a ground voltage (or low-potential power supply voltage, GND), and a reference voltage Vref. The initialization pulse INT, the scan pulse SCAN, and the emission control pulse EM are supplied to the light emitting cells 10 through the gate lines 102, respectively.

The high-potential power supply voltage VDD can be set to a voltage of approximately 15 to 20V. The reference voltage Vref is lower than the threshold voltage of the organic light emitting diode OLED so that the difference between the reference voltage Vref and the ground voltage GND becomes lower than the threshold voltage of the organic light emitting diode OLED. Lt; / RTI > The reference voltage Vref may be set to a negative voltage so as to apply a reverse bias to the organic light emitting diode OLED at the time of initialization of the driving element connected to the organic light emitting diode OLED.

The light emitting cell 10 includes an OLED, a storage capacitor Cstg, a plurality of switch TFTs S1 to S5, and a drive TFT (D-TFT).

The first switch TFT S1 is turned on in response to the initialization pulse input through the first gate line 102 to supply the reference voltage Vref to the fourth node n4, The voltage is initialized to the reference voltage Vref. The source electrode of the first switch TFT S1 is connected to the fourth node n4, and the drain electrode thereof is connected to the reference voltage source Vref via the fifth node n5. The gate electrode of the first switch TFT S1 is connected to the first gate line 102 to which the initialization pulse INI is supplied.

The second switch TFT S2 is turned on in response to a scan pulse SCAN input through the second gate line 102 to supply the data voltage Data to the first node n1. The drain electrode of the second switch TFT (S2) is connected to the first node (n1), and its source electrode is connected to the data line (101). And the gate electrode of the second switch TFT S2 is connected to the second gate line 102 to which the scan pulse SCAN is supplied.

The third switch TFT S3 is turned on in response to the scan pulse SCAN input through the second gate line 102 to form a current path between the second node n2 and the third node n3 Thereby operating the driving TFT (D-TFT) as a diode. The source electrode of the third switch TFT (S3) is connected to the third node (n3), and the drain electrode thereof is connected to the second node (n2). The gate electrode of the third switch TFT (S3) is connected to the second gate line 102 to which the scan pulse (SCAN) is supplied.

The fourth switch TFT S4 is turned off in response to the light emission control pulse SCAN input through the third gate line 102 to supply a current path between the first node n1 and the fifth node n5 . The source electrode of the fourth switch TFT (S4) is connected to the first node (n1), and the drain electrode thereof is connected to the fifth node (n5). The gate electrode of the fourth switch TFT (S4) is connected to the third gate line 102 to which the emission control pulse EM is supplied.

The fifth switch TFT S5 is turned off in response to the light emission control pulse SCAN input through the third gate line 102 to supply a current path between the third node n3 and the fourth node n4 . The source electrode of the fifth switch TFT (S5) is connected to the third node (n3), and the drain electrode thereof is connected to the fourth node (n4). The gate electrode of the fifth switch TFT (S5) is connected to the third gate line 102 to which the emission control pulse EM is supplied.

The driving TFT (D-TFT) supplies a current from the high potential power source voltage source (VDD) to the OLED, and controls the current to the gate-source voltage. The source electrode of the driving TFT (D-TFT) is connected to the high potential power source voltage source (VDD), and the drain electrode thereof is connected to the third node (n3). And the gate electrode of the driving TFT (D-TFT) is connected to the second node (n2).

The switch TFTs S1 to S5 and the driver TFT (D-TFT) may be implemented as a p-type MOSFET (metal-oxide-semiconductor field-effect transistor).

The storage capacitor Cstg is connected between the first node n1 and the second node n2 to charge the electric charge flowing in the direction of the arrow while the second and third switch TFTs S2 and S3 are turned on And stores the threshold voltage of the driving TFT (D-TFT) to sense the threshold voltage. The storage capacitor Cstg is connected between the first node n1 and the second node n2.

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). The OLED emits light in accordance with the current supplied through the driving TFT (DTFT1). The anode electrode of the OLED is connected to the fourth node (n4), and the cathode electrode thereof is connected to the ground voltage source (GND).

The operation of the light emitting cell 10 will be described step by step with reference to FIGS. 2 and 3. FIG.

The gate driver 14 supplies the initialization pulse INI of the low logic voltage to the first gate line 102 during the first to third periods t1 to t3 and supplies the initialization pulse INI to the first gate line 102 during the second and third periods t1 to t2, While supplying a scan pulse SCAN of a low logic voltage to the second gate line 102. [ The gate driver 14 supplies the emission control pulse EM of the high logic voltage to the third gate line 102 during the third period t3. The data driver 120 supplies the data lines 101 with a data voltage synchronized with the scan pulse SCAN.

The first switch TFT S1 is turned on in response to the initialization pulse INT of the low logic voltage supplied through the first gate line 102 during the first to third periods t1 to t3. The first switch TFT (S1) is turned off when the voltage of the first gate line (102) is a high logic voltage. The anode voltage of the OLED is initialized to the reference voltage Vref applied through the first switch TFT S1 during the first to third periods t1 to t3.

The second and third switch TFTs S2 and S3 are turned on in response to the scan pulse SCAN of the low logic voltage supplied through the second gate line 102 during the second and third periods t2 to t3. Is turned on. The second and third switch TFTs S2 and S3 are turned off when the voltage of the second gate line 102 is a high logic voltage. During the second and third periods t2 to t3, the storage capacitor Cstg charges the difference voltage between the first node n1 and the second node n1 to sense the threshold voltage of the driving TFT D-TFT do. In order to compensate the threshold voltage deviation of the driving TFT (D-TFT), the second and third periods (t2 to t3) must be sufficiently long.

The fourth and fifth switch TFTs S4 and S5 are turned off in response to the scan pulse SCAN of the high logic voltage supplied through the third gate line 102 during the third period t3, . The fourth and fifth switch TFTs S4 and S5 are turned on when the voltage of the third gate line 103 is a low logic voltage. The OLED emits after the third period t3.

The switch TFTs S1 to S5 and the drive TFT (D-TFT) may be implemented as n-type MOSFETs. In this case, the phases of the drive waveforms shown in Fig. 3 are inverted.

In order to compensate the threshold voltage deviation of the driving TFT, the second and third periods (t2 to t3) in which the threshold voltage of the driving TFT is sensed within a one-scan period, that is, one horizontal period, must be sufficiently long. Here, one scan line includes one row (line) of light emitting cells 10 selected by the initialization pulse INT, the scan pulse SCAN and the emission control pulse EM. One horizontal period becomes shorter as the driving frequency becomes higher or the number of scan lines increases as shown in FIG. The number of scan lines increases with increasing resolution. Therefore, when the resolution or the driving frequency of the organic light emitting diode display device is increased, one horizontal period becomes shorter, so that the threshold voltage sensing time of the driving TFT (D-TFT) becomes insufficient. The present invention can sufficiently secure the threshold voltage sensing time of the driving TFT (D-TFT) in each of the light emitting cells 10 by extending one horizontal period by using the data distributor 130. [ This will be described in detail with reference to FIGS. 5 to 10. FIG.

FIGS. 5 and 6 are views showing a first embodiment of the display panel 10 of the data distribution unit 130. FIG.

Referring to FIGS. 5 and 6, the data distribution unit 130 includes a plurality of demultiplexers (DMUX).

Each of the demultiplexers DMUX includes one input terminal and two output terminals. The input terminal of the demultiplexer DMUX is connected to the output terminal of the data driver, and the output terminals of the demultiplexer DMUX are connected to the odd-numbered data line 101 and the even-numbered data line 101. The demultiplexer DMUX includes first and second switch TFTs T1 and T2. The first switch TFT (T1) supplies the data voltage to the odd-numbered data line (101) in response to the first control signal (M1). A first control signal (M1) is supplied from the timing controller (110) to the gate electrode of the first switch TFT (T1). The drain electrode of the first switch TFT (T1) is connected to the output terminal of the data driver (120), and the source electrode thereof is connected to the odd-numbered data line (101). The second switch TFT T2 supplies the data voltage to the even data line 101 in response to the second control signal M2. A second control signal (M2) is supplied from the timing controller (110) to the gate electrode of the second switch TFT (T2). The drain electrode of the second switch TFT (T2) is connected to the output terminal of the data driver (120), and the source electrode thereof is connected to the even data line (101). The first control signal M1 and the second control signal M2 are generated in opposite phases as shown in Fig.

When the pulse width of the control signals M1 and M2 is one horizontal period 1H, the scan pulses SCAN1 to SCAN6 have an extended horizontal period EH longer than one horizontal period 1H, Lt; / RTI > The extended horizontal period (EH) may be set to one horizontal period (1H) or more, for example, two horizontal periods. th scan pulse SCANn is superimposed on the back portion of the (n-1) th scan pulse SCANn-1 and overlaps with the leading portion of the (n + 1) th scan pulse SCANn + do.

The light emitting cells 10 disposed in the odd-numbered display lines LINE # 1, LINE # 3, and LINE # 5 of the display panel 10 are connected to the odd-numbered data lines 101. The light emitting cells 10 arranged in the even-numbered display lines LINE # 2, LINE # 4 and LINE # 6 of the display panel 10 are connected to the odd-numbered data lines 101. The light emitting cells 10 of the odd-numbered display lines LINE # 1, LINE # 3, and LINE # 5 respond to the extended scan pulses SCAN1, SCAN3 and SCAN5, And receives the data voltage through the first switch TFT (T1) and the odd-numbered data lines (101) of the demultiplexer (DMUX). The light emitting cells 10 of the even-numbered display lines LINE # 2, LINE # 4 and LINE # 6 respond to the extended scan pulses SCAN2, SCAN4 and SCAN6, And receives the data voltage through the second switch TFT (T2) of the demultiplexer (DMUX) and the even data lines (101).

Figs. 7 and 8 are views showing a second embodiment of the display panel 10 of the data distribution unit 130. Fig.

Referring to FIG. 7 and FIG. 8, each of the demultiplexers (DMUX) of the data distribution unit 130 includes one input terminal and three output terminals. The input terminal of the demultiplexer DMUX is connected to the output terminal of the data driver 120. The output terminals of the demultiplexer DMUX are connected to 3i (i is a positive integer) +1 data line 101, Line 101 and the (3i + 3) th data line 101, respectively. The demultiplexer DMUX includes first to third switch TFTs T1 to T3. The first switch TFT T1 supplies the data voltage input through the output terminal of the data driver 120 to the (3i + 1) th data line 101 in response to the first control signal M1. A first control signal (M1) is supplied from the timing controller (110) to the gate electrode of the first switch TFT (T1). The drain electrode of the first switch TFT T1 is connected to the output terminal of the data driver 120 and its source electrode is connected to the (3i + 1) th data line 101. The second switch TFT T2 supplies the data voltage to the (3i + 2) th data line 101 in response to the second control signal M2. A second control signal (M2) is supplied from the timing controller (110) to the gate electrode of the second switch TFT (T2). The drain electrode of the second switch TFT T2 is connected to the output terminal of the data driver 120, and the source electrode thereof is connected to the (3i + 2) th data line 101. The third switch TFT T3 supplies the data voltage to the (3i + 3) th data line 101 in response to the third control signal M3. The third control signal M3 is supplied from the timing controller 110 to the gate electrode of the third switch TFT T3. The drain electrode of the third switch TFT (T3) is connected to the output terminal of the data driver 120, and the source electrode of the third switch TFT (T3) is connected to the (3i + 3) th data line 101. The timing controller 110 sequentially generates the first to third control signals M1 to M3 as pulses whose phases are delayed as shown in FIG.

When the pulse width of the control signals M1 to M3 is one horizontal period 1H, the scan pulses SCAN1 to SCAN6 are supplied to the extended horizontal period EH, which is longer than one horizontal period 1H, Lt; / RTI > The extended horizontal period EH can be set to, for example, three horizontal periods longer than the first embodiment described above. The nth scan pulses SCANn are overlapped with the rear portions of the (n-2) th and (n-1) th scan pulses SCANn-2 and SCANn- +1, SCANn + 2).

The light emitting cells 10 arranged in the (3i + 1) th display lines LINE # 1 and LINE # 4 of the display panel 10 are connected to the (3i + 1) The light emitting cells 10 arranged in the (3i + 2) th display lines LINE # 2 and LINE # 5 of the display panel 10 are connected to the (3i + 2) The light emitting cells 10 arranged in the (3i + 3) th display lines LINE # 3 and LINE # 6 of the display panel 10 are connected to the (3i + 3) The light emitting cells 10 of the (3i + 1) th display lines LINE # 1 and LINE # 4 sense the threshold voltage of the driving TFT D-TFT in response to the extended scan pulses SCAN1 and SCAN4, And receives the data voltage through the first switch TFT (T1) and the (3i + 1) th data lines 101 of the data driver DMUX. The light emitting cells 10 of the (3i + 1) th display lines LINE # 2 and LINE # 5 sense the threshold voltage of the driving TFT D-TFT in response to the extended scan pulses SCAN2 and SCAN5, And receives the data voltage through the second switch TFT (T2) and the (3i + 2) th data lines (101) of the data driver (DMUX). The light emitting cells 10 of the (3i + 3) th display lines LINE # 3 and LINE # 6 sense the threshold voltage of the driving TFT D-TFT in response to the extended scan pulses SCAN3 and SCAN6, The third switch TFT T4 and the (3i + 3) th data lines 101 of the first data line DMUX.

The data distribution unit 130 is not limited to those shown in Figs. For example, the demultiplexer (DMUX) of the data distribution unit 130 may be implemented with a 1: 4, 1: 5, or 1: 6 demultiplexer (not shown).

For example, the 1: 4 demultiplexer (DMUX) includes first to fourth switch TFTs for time-divisionally supplying a data voltage to four data lines. The first switch TFT supplies the data voltage to the (4i + 1) th data line 101 in response to the first control signal M1. The second switch TFT supplies the data voltage to the (4i + 2) th data line 101 in response to the second control signal M2. The third switch TFT supplies the data voltage to the (4i + 3) th data line 101 in response to the third control signal M3. The fourth switch TFT supplies the data voltage to the (4i + 4) th data line 101 in response to the fourth control signal M4. The timing controller 110 sequentially generates the first to fourth control signals M1 to M4 as pulses whose phases are delayed. When the pulse widths of the control signals M1 to M4 are one horizontal period (1H), the scan pulses SCAN1 to SCAN6 can be set to, for example, four horizontal periods longer than those in the above embodiments have. The nth scan pulses SCANn are superimposed on the subsequent portions of the (n-3) th to (n-1) th scan pulses SCANn-1 to SCANn-3, +1 to SCANn + 3). The light emitting cells 10 arranged in the (4i + 1) th display lines LINE # 1 and LINE # 5 are connected to the (4i + 1) th data line 101 . The light emitting cells 10 arranged in the (4i + 2) th display lines LINE # 2 and LINE # 6 are connected to the (4i + 2) And the light emitting cells 10 arranged in the (4i + 3) th display lines LINE # 3 and LINE # 7 are connected to the (4i + 3) And the light emitting cells 10 arranged in the (4i + 4) th display lines LINE # 4 and LINE # 8 are connected to the (4i + 4)

The 1: 5 demultiplexer (DMUX) includes first to fifth switch TFTs to supply the data voltage to the five data lines in a time-division manner. The first switch TFT supplies the data voltage to the (5i + 1) -th data line 101 in response to the first control signal M1. The second switch TFT supplies the data voltage to the (5i + 2) th data line 101 in response to the second control signal M2. The third switch TFT supplies the data voltage to the (5i + 3) th data line 101 in response to the third control signal M3. The fourth switch TFT supplies the data voltage to the (5i + 4) th data line 101 in response to the fourth control signal M4. The fifth switch TFT supplies the data voltage to the (5i + 5) th data line 101 in response to the fifth control signal M5. The timing controller 110 sequentially generates the first to fifth control signals M1 to M5 as pulses whose phases are delayed. When the pulse widths of the control signals M1 to M5 are one horizontal period (1H), the scan pulses SCAN1 to SCAN6 can be set to, for example, five horizontal periods longer than those of the above embodiments have. The nth scan pulses SCANn are superimposed on the (n + 4) th to (n-4) th scan pulses SCANn-1 to SCANn- +1 to SCANn + 4). The light emitting cells 10 arranged in the (5i + 1) th display lines LINE # 1 and LINE # 6 are connected to the (5i + 1) -th data line 101 . The light emitting cells 10 arranged in the (5i + 2) th display lines LINE # 2 and LINE # 7 are connected to the (5i + 2) The light emitting cells 10 arranged in the (5i + 3) th display lines LINE # 3 and LINE # 8 are connected to the (5i + 3) data line 101. The light emitting cells 10 arranged in the (5i + 4) th display lines LINE # 4 and LINE # 9 are connected to the (5i + 4) The light emitting cells 10 arranged in the (5i + 5) th display lines LINE # 5 and LINE # 10 are connected to the (5i + 5)

The 1: 6 demultiplexer DMUX includes first to sixth switch TFTs for time-divisionally supplying the data voltage to six data lines. The first switch TFT supplies the data voltage to the (6i + 1) -th data line 101 in response to the first control signal M1. The second switch TFT supplies the data voltage to the (6i + 2) th data line 101 in response to the second control signal M2. The third switch TFT supplies the data voltage to the (6i + 3) th data line 101 in response to the third control signal M3. The fourth switch TFT supplies the data voltage to the 6i + 4th data line 101 in response to the fourth control signal M4. The fifth switch TFT supplies the data voltage to the (6i + 5) th data line 101 in response to the fifth control signal M5. The sixth switch TFT supplies the data voltage to the 6i + 6th data line 101 in response to the sixth control signal M6. The timing controller 110 sequentially generates the first to sixth control signals M1 to M6 as pulses whose phases are delayed. When the pulse widths of the control signals M1 to M6 are one horizontal period (1H), the scan pulses SCAN1 to SCAN6 can be set to, for example, six horizontal periods longer than those in the above embodiments have. The nth scan pulses SCANn are superimposed on the subsequent portions of the (n-5) th to (n-1) th scan pulses SCANn-1 to SCANn-5, +1 to SCANn + 4). The light emitting cells 10 arranged in the (5i + 1) th display lines LINE # 1 and LINE # 7 are connected to the (6i + 1) -th data line 101 . And the light emitting cells 10 arranged in the (6i + 2) th display lines LINE # 2 and LINE # 8 are connected to the 6i + 2 data line 101. And the light emitting cells 10 arranged in the (6i + 3) th display lines LINE # 3 and LINE # 9 are connected to the (6i + 3) data line 101. The light emitting cells 10 arranged in the (6i + 4) th display lines LINE # 4 and LINE # 10 are connected to the 6i + 4 data line 101. The light emitting cells 10 arranged in the (6i + 5) th display lines LINE # 5 and LINE # 11 are connected to the (6i + 5) The light emitting cells 10 arranged in the (6i + 6) th display lines LINE # 6 and LINE # 12 are connected to the (6i + 6)

FIG. 9 and FIG. 10 are waveform diagrams showing waveforms measured in an experiment in which the scan time of the conventional organic light emitting diode display device and the organic light emitting diode display device of the present invention are compared. FIG. 9 is a waveform diagram showing a threshold voltage sensing period of a driving TFT in a conventional organic light emitting diode display device, and FIG. 10 is a waveform diagram of an OLED display device including a data distributor and a display panel as shown in FIG. 5 and FIG. FIG. 5 is a waveform diagram showing an extended threshold voltage sensing period of the TFT.

9 and 10, the data distributor 130 is disposed between the data driver 120 and the display panel 10 and the pulse width of the scan pulse is controlled by the control signal of the data distributor 130 The control is made to be wider than that of FIG. Therefore, even when the resolution of the organic light emitting diode display device is increased or the driving frequency is increased, the present invention can sufficiently secure the sensing time of the driving TFT, so that the threshold voltage deviation of the driving TFT can be precisely compensated.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: light emitting cell 100: display panel
110: timing controller 120: data driver
130: Data distributor 140: Gate driver

Claims (8)

A display panel in which data lines and gate lines are crossed and includes a plurality of light emitting cells;
A data driver for converting the digital video data into a data voltage to be supplied to the data lines;
An initialization pulse of a first voltage level is supplied to the first gate line during the first to third periods within one horizontal period and a scan pulse of a first voltage level is supplied to the second gate line during the second and third periods A gate driver for supplying an emission control pulse of a second voltage level to the third gate line during the third period;
A data distributor connected between the data driver and the data lines to supply the data voltages output from the data driver to the plurality of data lines in a time division manner; And
And a timing controller for generating control signals for controlling operation timings of the data driver, the gate driver, and the data distributor and supplying the digital video data to the data driver,
Wherein each of the light emitting cells includes an organic light emitting diode element, a driving TFT, a plurality of switch TFTs, and a capacitor, a threshold voltage of the driver TFT is sensed during the second and third periods, 1 < / RTI > voltage level and is turned off in response to the second voltage level,
Wherein the pulse width of the scan pulse is wider than that of the control signal of the data distribution unit. The method according to claim 1,
Wherein the data distributor comprises:
Comprising a plurality of demultiplexers,
Each of the demultiplexers has one input terminal connected to one output terminal of the data driver and N output terminals connected to N (N is an integer of 2 or more and 6 or less) data lines at a ratio of 1: 1 The organic light emitting diode display device comprising: 3. The method of claim 2,
The demultiplexer includes:
A first switch TFT for supplying the data voltage inputted from the output terminal of the data driver to the first data line; And
And a second switch TFT for supplying the data voltage inputted from the output terminal of the data driver to the second data line,
Wherein the timing controller generates a first control signal for controlling the first switch TFT and a second control signal for controlling the second switch TFT in opposite phases. The method of claim 3,
The light emitting cells arranged on the odd-numbered display lines of the display panel are connected to the odd-numbered data lines,
And the light emitting cells arranged on the even-numbered display lines of the display panel are connected to odd-numbered data lines. 3. The method of claim 2,
The demultiplexer includes:
A first switch TFT for supplying the data voltage inputted from the output terminal of the data driver to the first data line;
A second switch TFT for supplying the data voltage inputted from the output terminal of the data driver to the second data line,
And a third switch TFT for supplying the data voltage inputted from the output terminal of the data driver to the third data line,
The timing controller sequentially generates a first control signal for controlling the first switch TFT, a second control signal for controlling the second switch TFT, and a third control signal for controlling the third switch TFT The organic light emitting diode display device comprising: 6. The method of claim 5,
The light emitting cells arranged on the (i + 1) -th display line of the display panel are connected to the (3i + 1) -th data lines,
The light emitting cells arranged on the (3i + 2) -th display line of the display panel are connected to the (3i + 2) -th data lines,
And the light emitting cells arranged on the (3i + 3) -th display line of the display panel are connected to the (3i + 3) -th data line. The method according to claim 1,
The switch TFTs,
A first switch TFT which is turned on in response to the initialization pulse and supplies a predetermined reference voltage supplied through a fifth node to a fourth node;
A second switch TFT which is turned on in response to the scan pulse and supplies the data voltage to the first node;
A third switch TFT which is turned on in response to the scan pulse to form a current path between the second node and the third node;
A fourth switch TFT which is turned off in response to the light emission control pulse to cut off the current path between the first node and the fifth node; And
And a fifth switch TFT which is turned off in response to the light emission control pulse to cut off a current path between the third node and the fourth node,
Wherein the driving TFT supplies a current from a high potential power source voltage source to the organic light emitting diode device and adjusts a current of the organic light emitting diode device to a gate-source voltage. 8. The method of claim 7,
The first switch TFT includes a source connected to the fourth node, a drain connected to the fifth node, and a gate connected to the first gate line,
The second switch TFT includes a drain connected to the first node, a source connected to the data line, and a gate connected to the second gate line,
The third switch TFT includes a source connected to the third node, a drain connected to the second node, and a gate connected to the second gate line,
The fourth switch TFT includes a source connected to the first node, a drain connected to the fifth node, and a gate connected to the third gate line,
The fifth switch TFT includes a source connected to the third node, a drain connected to the fourth node, and a gate connected to the third gate line,
Wherein the driving TFT includes a source connected to the high potential power supply voltage source, a drain connected to the third node, and a gate connected to the second node,
And the capacitor is connected between the first node and the second node.

KR1020100019880A 2010-03-05 2010-03-05 Organic light emitting diode display device KR101642995B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100019880A KR101642995B1 (en) 2010-03-05 2010-03-05 Organic light emitting diode display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100019880A KR101642995B1 (en) 2010-03-05 2010-03-05 Organic light emitting diode display device

Publications (2)

Publication Number Publication Date
KR20110100840A KR20110100840A (en) 2011-09-15
KR101642995B1 true KR101642995B1 (en) 2016-08-10

Family

ID=44953111

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100019880A KR101642995B1 (en) 2010-03-05 2010-03-05 Organic light emitting diode display device

Country Status (1)

Country Link
KR (1) KR101642995B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11657761B2 (en) 2019-10-18 2023-05-23 Samsung Display Co., Ltd. Display panel of an organic light emitting diode display device, and organic light emitting diode display device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102356992B1 (en) 2017-08-03 2022-02-03 삼성디스플레이 주식회사 Organic light emitting display device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100806814B1 (en) * 2006-06-23 2008-02-25 엘지.필립스 엘시디 주식회사 Apparatus for Driving Organic Elctro Luminescence Display
KR101419237B1 (en) * 2007-12-27 2014-08-13 엘지디스플레이 주식회사 Luminescence dispaly
KR101064466B1 (en) * 2009-07-29 2011-09-16 삼성모바일디스플레이주식회사 Organic Light Emitting Display Device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11657761B2 (en) 2019-10-18 2023-05-23 Samsung Display Co., Ltd. Display panel of an organic light emitting diode display device, and organic light emitting diode display device

Also Published As

Publication number Publication date
KR20110100840A (en) 2011-09-15

Similar Documents

Publication Publication Date Title
US10748492B2 (en) Gate shift register and organic light emitting display apparatus including the same
EP2833351B1 (en) Organic light emitting display
KR102102251B1 (en) Organic light emitting display device
US9105236B2 (en) Light emitting display device
KR101760090B1 (en) Pixel and Organic Light Emitting Display Device Using the same
KR100986915B1 (en) Organic Light Emitting Display and Driving Method Thereof
KR100739334B1 (en) Pixel, organic light emitting display device and driving method thereof
KR100768047B1 (en) OLED display apparatus and drive method thereof
KR100592646B1 (en) Light Emitting Display and Driving Method Thereof
KR20190018982A (en) Gate driving circuit and display device using the same
KR20190020549A (en) Gate driving circuit, display device and method of driving the display device using the gate driving circuit
KR20100115062A (en) Pixel and organic light emitting display using the pixel
US9318052B2 (en) Compensating organic light emitting diode display device and method for driving the same using two adjacent gate lines per pixel
KR20160057596A (en) Organic Light Emitting Diode
KR100707624B1 (en) Pixel and Driving Method of Light Emitting Display Using the Same
KR102118926B1 (en) Organic light emitting display device
KR20190040849A (en) Organic light emitting display device and driving method of the same
KR102519364B1 (en) Gate driver, display apparatus including the same, method of driving display panel using the same
KR101950819B1 (en) Light emitting display device
KR101862603B1 (en) Light emitting display device
KR100858613B1 (en) Organic Light Emitting Display Device
KR101978781B1 (en) Display device
KR101642995B1 (en) Organic light emitting diode display device
KR100805608B1 (en) Pixel and organic light emitting display device using the pixel
KR101977607B1 (en) Gate drive integrated circuit and organic light emitting display apparatus using the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20190617

Year of fee payment: 4