KR20110091498A - Mos varactor - Google Patents

Abstract

PURPOSE: An MOS varactor is provided to use a plurality of gates and gate contact on a gate, thereby reducing series resistance. CONSTITUTION: An island shape gate insulating layer is arranged at an interval like an n by m matrix where n and m are integers higher than one and etc in a well region of a substrate. A gate electrode(14) with a first height is placed on an upper part of the gate insulating layer. A gate contact(30) is touched with the gate electrode. A first metal wiring with a second height is electrically connected to the gate contact. A source and drain contact(70) are touched with a doped region which excludes a lower part of the gate insulating layer by being arranged at interval of a n+1 by m+1 matrix in order to form vertices of a square in which the gate electrode is located on the center of the square. A third height of a second metal wiring is electrically connected to a source and drain contact. The first height is smaller than the second height and the third height is higher than the second height.

Description

MOS varactor

The present invention relates to a MOS varactor. More specifically, the present invention relates to a MOS varactor for millimeter-wave band circuits and devices, and includes a plurality of gates and gates mounted in an island shape in a well region of a substrate. The above-described gate contact relates to a MOS varactor that has reduced series resistance and improved Q-factor.

In line with the recent trend of informatization, high-speed and high-frequency efforts have been continued in the wireless communication field for high-quality broadband communication services.In response, the Complementary Metal-Oxide Semiconductor (CMOS) process base for RFIC (Radio Frequency Integrated Circuit) High integration, high frequency and low noise characteristics of semiconductor devices have emerged as major challenges.

In the past, CMOS process-based semiconductor devices can be on-chip and show excellent advantages in terms of production cost and power consumption, and are recognized as a core technology for RFIC implementation in the millimeter wave (30 GHz to 300 GHz) band. In recent years, the application of RFIC has increased in the 60 GHz and 77 GHz range, adding importance.

On the other hand, as the operating frequency of RFIC using CMOS process-based semiconductor devices increases, inductors, varactors, capacitors, and active elements such as transistors in semiconductor devices are increased. The performance of the same passive element is a factor in determining overall operating characteristics.

For example, a voltage-controlled oscillator that generates the carrier frequency of a millimeter wave band transceiver is the most important characteristic of phase noise, which includes an LC tank consisting of inductors and varactors. The Q-factor of the LC tank is a key contributor. In this case, in the relatively low frequency band of several GHz, the performance decrease due to the inductor is mainly a problem as the Q-factor of the inductor determines the Q-factor of the entire LC tank, but the Q factor of the inductor is relatively improved with increasing operating frequency. On the other hand, the varactor's Q-factor tends to decrease dramatically, so in the millimeter wave band, the varactor's Q-factor acts as a major factor in the overall performance of the LC tank and VCO.

Accordingly, until recently, a so-called multifinger structure of MOS varactors, in which stripe-shaped gate electrodes were alternately connected, has been mainly used. However, the structure has increased parasitic capacitance to reduce tuning range. In addition, destabilization of the device is accompanied by a fatal disadvantage of increasing the device size.

The present invention has been made to solve the above problems, and an object thereof is to provide a MOS varactor having more improved characteristics. That is, an object of the present invention is to provide a MOS varactor for a circuit and a device having a millimeter wave band, which has a lower series resistance and improved Q-factor as compared to a multifinger MOS varactor.

To this end, the present invention reduces the series resistance according to the channel resistance and the contact resistance by using a plurality of gates seated in an island shape in the well region of the substrate and a gate contact on the gate. We want to provide an improved MOS varactor.

In order to achieve the above object, the present invention provides an island-type gate insulating film and the gate insulating film arranged in equal intervals in a matrix of (n × m) in the well region of the substrate, where n and m are integers greater than 1, respectively. A gate electrode having a first height t1 disposed thereon; A gate contact in contact with the gate electrode; A first metal wire having a second height t2, wherein t1 <t2, which is electrically connected to the gate contact; Source and drain contacts that are arranged at equal intervals in a matrix of (n + 1) × (m + 1) so as to form a square vertex centered on the gate electrode, and are in contact with the doped region except for the lower end of the gate insulating film; And a second metal wire having a third height t3 (wherein t2 <t3) electrically connected to the source and drain contacts.

In this case, the gate electrode is a polygon or a circle including a square, characterized in that made of one of polysilicon, silicided polysilicon, metal.

The semiconductor device may further include a first insulating layer interposed between the substrate and the first metal wiring to provide a first contact hole connected to the gate electrode and a second contact hole connected to the doped region to cover the gate insulating film and the gate electrode. And the gate contact is in contact with the gate electrode through the first contact hole, and between the first insulating layer and the second metal wiring to provide a third contact hole respectively connected to the second contact hole. The semiconductor device may further include an intervening second insulating layer, wherein the source and drain contacts may be in contact with the source and drain regions through the second and third contact holes, respectively. And a plug having a second height t2 interposed between the three contact holes to connect the upper and lower source and drain contacts.

In addition, the first metal wiring and the plug is made of the same material, it is interposed between the first insulating layer and the second insulating layer to provide a first damascene hole for the first metal wiring and the plug. It characterized in that it further comprises an interlayer insulating layer, wherein the first metal wiring and the plug is characterized in that the copper (Cu).

The method may further include a third insulating layer covering the second insulating layer to provide a second damascene hole for the second metal wiring, wherein the second metal wiring is copper (Cu). do.

The MOS varactor according to the present invention reduces the channel resistance through the gate electrode seated in an island shape in the well region of the substrate, while reducing the contact resistance through the gate contact on the gate electrode, thereby reducing the series resistance and improving the Q factor.

That is, in the MOS varactor according to the present invention, the varactor exhibits a characteristic in which the series resistance is small and Q application is improved compared to the varactor of the conventional multi-finger structure in the entire frequency band of 1 to 100 GHz. Therefore, there is an advantage suitable for circuits and devices in the millimeter wave band.

1 is a schematic plan view of a MOS varactor according to the present invention.
2 is a schematic cross-sectional view of a MOS varactor according to the present invention.
3 to 11 is a cross-sectional schematic diagram of the manufacturing process of the MOS varactor according to the present invention.
12 is a schematic sectional view showing a modification of the MOS varactor according to the present invention.
Figure 13 is a graph comparing the Q factor of the MOS varactor and the general MOS varactor according to the present invention.
14 is a graph comparing the series resistance of the MOS varactor and the general MOS varactor according to the present invention.

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail with reference to drawings.

Prior to the full description, the drawings and description referred to in the present specification are intended to examine the main technical idea of the present invention, and the gist of the present invention with respect to known structures and known technologies that can be variously applied based on general contents. It should be as brief as possible because it may be cloudy. However, various known contents applicable to the present invention will be easily understood or expected by those skilled in the art through the following description.

FIG. 1 is a schematic plan view of the MOS varactor according to the present invention, and FIG. 2 is a schematic cross-sectional view of the II-II line of FIG. 1.

As can be seen, in the MOS varactor according to the present invention, at least one gate electrode 14 is uniformly disposed along the well region of the substrate 2 and connected to the first metal wiring 40 through the gate contact 30. The source and drain contacts 70 serving as the source and drain electrodes substantially acting on the arbitrary gate electrodes 14 may be uniformly arranged along the doped regions on the substrate 2 and connected to the second metal wires 80.

In this case, in particular, the gate electrode 14 is an island shape arranged at equal intervals so as to form a matrix of (n × m) in the well region of the substrate 2 (where n and m are each an integer greater than 1). The drain contacts 70 are arranged at equal intervals so as to form a matrix of (n + 1) × (m + 1) in the doping region of the substrate 2 except for the lower end of the gate insulating film 12, respectively. This corresponds to the position of the four vertices of the square centered on).

The details are as follows.

First, the substrate 2 of the MOS varactor according to the present invention is a silicon (Si) wafer, and provides a separate space electrically separated from other devices by the device isolation film 4.

In this case, the second conductive doped region B is formed to a predetermined depth on one surface of the substrate 2 except for the lower end of the gate insulating layer 12 while the corresponding space forms the well region A of the first conductive type. . For reference, when the first conductivity type is N type and the second conductivity type is N + type, the MOS varactor according to the present invention becomes an accumulation mode, and in the opposite case, a depletion mode or an inversion mode. )

In the well region A of the substrate 2, at least one gate insulating film 12 and a gate electrode 14 thereon are disposed in an island shape.

At this time, the gate insulating film 12 and the gate electrode 14 are polygonal shapes having the same circular shape or square shape, and the matrix of (n × m) in the well region A on the substrate 2 (where n, m Are each an integer greater than 1). 1 and 2 are examples of the case where the gate insulating film 12 and the gate electrode 14 form a matrix of (2 × 2), respectively. Preferably, the gate insulating film 12 and the gate electrode are preferred. Reference numeral 14 denotes square shapes and arranged at equal intervals along the matrix direction.

The gate contact 30 is connected to the gate electrode 14, respectively, and the gate contact 30 is electrically connected to the first metal wiring 40 at a position higher than the gate electrode 14.

That is, when the height of the gate electrode 14 is t1, the height of the first metal wiring 40 is t2 (where t1 <t2). For this purpose, the gate between the substrate 2 and the first metal wiring 40 is used. The first insulating layer 20 covering the insulating film 12 and the gate electrode 14 is interposed. Accordingly, the first insulating layer 20 may serve as an underlayer supporting the first metal wire 40, and may also be used for the first contact hole 22 for the gate contact 30 and the source and drain contacts 70 to be described later. The second contact hole 24 is provided, wherein the first contact hole 22 is filled with the gate contact 30, and the second contact hole 24 is provided with a first source and a part of the source and drain contact 70. Drain contact 72 is filled.

In addition, a first metal wire 40 is disposed on the first insulating layer 20 to electrically connect the gate contact 30. A plug 42 made of the same material as the first metal wire 40 is formed at the same height. Is present and electrically connected to the first source and drain contacts 72.

The source and drain contacts 70 are in contact with the doped region B of the substrate 2.

At this time, the source and drain contacts 70 are in contact with the doped region B through the second contact hole 24 of the first insulating layer 20, respectively, and have a matrix of (n + 1) × (m + 1). It is arranged at equal intervals to achieve a point corresponding to the vertex of the square centered on each gate electrode 12. 1 and 2 are examples of the case where the source and drain contacts 70 form a matrix of (3 × 3), respectively, and as shown in the figure, four of the arbitrary gate electrodes 14 are shown. The source and drain contacts 70 are placed at positions corresponding to the vertices of the square centering the corresponding gate electrode 14, respectively.

And the source and drain contacts 70 are electrically connected through a second metal wire 80 at a height of t3 (t3> t2).

For the structure, a second insulating layer 60 covering the first metal wiring 40 is interposed between the first insulating layer 20 and the second metal wiring 80 to support the second metal wiring 80. In addition to serving as an underlayer, a third contact hole 62 for the source and drain contacts 70 is provided. Accordingly, the second source and drain contacts 74, which are the remainder of the source and drain contacts 70, are filled in the third contact hole 62, respectively, and are connected to the first source and drain contacts 72 through the plug 42. The second metal wire 80 is disposed on the second insulating layer 60 to electrically connect the source and drain contacts 70.

Meanwhile, in the above description, sidewalls made of an insulating material may be enclosed along the outer surfaces of the gate insulating film 12 and the gate electrode 14, and the source and the source of the doped region B of the substrate 2 may be surrounded. A separate metal silicide may be present at the position where the drain contact 70 is in contact.

This may be easily understood by those skilled in the art without a separate drawing.

In addition, the first metal wire 40 and the second metal wire 80 of the MOS varactor according to the present invention are preferably made of different materials. For example, the first metal wire 40 is made of copper (Cu). In the case where the second metal wiring 80 is aluminum (Al), when the first metal wiring 40 is aluminum (Al), the second metal wiring 80 may be copper.

In this case, in the former case, as shown in FIG. 2, a separate interlayer insulating layer 50 is interposed between the first and second insulating layers 20 and 60 so that the first metal wiring 40 and the plug 42 may be formed. The first damascene hole 52 is provided, and in the latter case, as shown in FIG. 12, a separate third insulating layer 90 is positioned above the second insulating layer 60 so that the second metal wiring 80 is positioned. The second damascene hole 92 may be provided.

That is, Figure 12 is a cross-sectional schematic diagram showing a MOS varactor according to a modification of the present invention, as is well known, copper is difficult to find a volatile material, it is impossible to pattern by conventional methods.

Therefore, when copper is used as the first metal wire 40, the interlayer insulating layer 50 is interposed between the first insulating layer 20 and the second insulating layer 60 as shown in FIG. ) And the first damascene hole 52 for the plug 42, and in the case where copper is used as the second metal wiring 80, the third insulating layer 90 is disposed over the second insulating layer 60. Added to provide a second damascene hole 92 for the second metallization 80.

This may be easily understood by those skilled in the art without further explanation.

As a result, the MOS varactor according to the present invention reduces the channel resistance through the gate electrode 14 seated in an island shape in the well region A of the substrate 2, while reducing the gate contact 30 on the gate electrode 14. This reduces contact resistance, reducing series resistance and improving Q factor.

Hereinafter, a manufacturing process of the MOS varactor according to the present invention will be described.

3 to 11 are cross-sectional schematic views of manufacturing processes of the MOS varactor according to the present invention, respectively, referring to FIGS. 1, 2, and 12.

In order to manufacture the MOS varactor according to the present invention, first, the substrate 2 is prepared as shown in FIG. 3, and then the well region A is formed by annealing with an ion implant of a first conductivity type on one surface of the substrate 2. In addition, the device isolation layer 4 is provided to define a separate area electrically separated from other devices.

For reference, the device isolation layer may be obtained by etching a portion of the substrate 2 to form a trench and filling a dielectric of an oxide, and subsequent densification and planarization.

Next, as shown in FIG. 4, the plurality of gate insulating films 12 and upper portions thereof are formed in the well region A of the substrate 2 to form a matrix of (n × m), where n and m are integers greater than 1, respectively. The gate electrodes 14 are implemented in the form of islands at equal intervals.

In this case, in order to obtain the gate insulating film 12 and the gate electrode 14, an insulating material for the gate insulating film 12 and a predetermined material for the gate electrode 14, such as polysilicon and silicide, are formed on one surface of the substrate 2. A thin film deposition of one selected from polysilicon or a metal material is sequentially performed, followed by a process of etching followed by photolithography, thereby forming a polygonal or circular gate insulating film 12 including a square. And a gate electrode 14 thereon is obtained.

For reference, photolithography refers to a series of processes for patterning a thin film. A photoresist, which is a photosensitive material, is applied onto a desired thin film, and then exposed with a mask and a developer solution. developer) to obtain a photoresist pattern (develop) to selectively expose a portion of the thin film. Therefore, when the etching is performed after photolithography, the thin film may be patterned in a form by removing a part of the exposed thin film. In the present specification, a strip and a clean may be used to remove the residual photoresist pattern after etching. Was used. This has the same meaning consistently herein.

Next, as shown in FIG. 5, the doping region B is formed by performing annealing with the second implant type ion implant on the entire surface of the substrate 2 on which the gate insulating film 12 and the gate electrode 14 are formed. As a result, one surface of the substrate 2 except for the lower end of the gate insulating film 12 becomes a doped region of a predetermined depth. (For convenience, the well region A and the doped region B are not separately shown in the following drawings.)

Next, as shown in FIG. 6, the first insulating layer 20 is deposited on the entire surface of the substrate 2 to cover the gate insulating layer 12 and the gate electrode 14, and the gate electrode 12 is etched following photolithography. The first contact hole 22 connected to the second contact hole 22 is arranged at equal intervals to form a matrix of (n + 1) × (m + 1) corresponding to a square vertex centered on an arbitrary gate electrode 12 In to form a second contact hole 24 connected to the doped region (B), respectively.

Next, as shown in FIG. 7, a metal material such as tungsten is deposited on the entire surface of the substrate 2 on which the first insulating layer 20 exists, followed by chemical mechanical polishing (CMP). Residual material other than the inside of the second contact holes 22 and 24 is removed.

Accordingly, the first contact hole 22 is filled with the gate contact 30 to be connected to the gate electrode 14, and the second contact hole 24 is filled with the first source and drain contact 72 to form the doped region B. FIG. ).

Next, as shown in FIG. 8, the first damascene hole 52 exposing the gate contact 30 and the first source and drain contacts 72 through photolithography followed by etching after the interlayer insulating layer 50 is deposited. Through).

Next, as shown in FIG. 9, copper is deposited on one surface of the substrate 2 on which the interlayer insulating layer 50 is formed and chemical mechanical polishing is performed to implement the first metal wiring 40 and the plug 42.

As a result, the gate electrode 14 is electrically connected to the first metal wire 40 through the gate pattern 30.

For reference, FIGS. 8 and 9 are examples in which copper is used as the first metal wires 40 and plugs 42. In contrast, in the case of using aluminum, instead of omitting the interlayer insulating layer 50, the components are after FIG. 7. The first metal wiring 40 and the plug 42 may be formed by depositing aluminum on the first insulating layer 20 and etching the photolithography followed by etching. This has already been described above and can be easily understood with reference to FIG. 12.

Next, as shown in FIG. 10, the second insulating layer 60 is deposited and then formed through the third contact hole 62 connected to the plug 42 through etching following the photolithography.

Next, as a result of depositing a metal material such as tungsten and chemical mechanical polishing as shown in FIG. 11, a second source and drain contact 74 filled in the third contact hole 62 may be obtained.

Finally, by depositing a metal material such as aluminum on the second insulating layer 60 and then performing etching followed by photolithography, a second metal wiring 80 connecting the source and drain contacts 70 can be obtained. The MOS varactor according to the present invention as described in FIGS. 1 and 2 is completed.

For reference, in the case of using copper as the second metal wiring 80 as shown in FIG. 12, after the source and drain contacts 70 are implemented through the process of FIG. 11, the third insulation is over the second insulating layer 60. A layer 90 is deposited and formed through the second damascene hole 92 that is connected to the source and drain contacts 70 via photolithography followed by etching. Subsequently, copper is deposited on the third insulating layer 90 to perform chemical mechanical polishing, thereby completing the second metal wiring 80.

13 and 14 are graphs comparing the characteristics of the MOS varactor according to the present invention with a varactor having a general multi-finger structure. FIG. 13 is a series resistance and FIG. 14 is a result of the Q factor.

At this time, the value indicated by ▼ on the graph indicates a case in which the gate insulating film 12 and the gate electrode 14 have a square shape as the MOS varactor according to the present invention, and the values indicated by Δ, □, ○ are each a general multi-finger structure In the MOS varactor according to the present invention, it can be seen that the series resistance is small and Q application is improved in the entire frequency band of 1 to 100 GHz.

The above is only a description of one preferred embodiment of the present invention, and does not limit the present invention. Therefore, the present invention may have a variety of modifications in a specific configuration, etc., if these modifications are within the technical idea of the present invention It should be belong to the scope of the invention, the scope of the invention will be clearly understood through the following claims.

2: substrate 4: device isolation film
12 gate insulating film 14 gate electrode
20: first insulating layer 22, 24: first and second contact holes
30: gate contact 40: first metal wiring
42 plug 50 interlayer insulation layer
52: first damascene hole 60: second insulating layer
62: third contact hole 70: source and drain contact
80: second metal wiring 90: third insulating layer
92: second damascene hall A: well area
B: doping area

Claims (1)

An island-shaped gate insulating film arranged at equal intervals in a (n × m) matrix (where n and m are integers greater than 1) in the well region of the substrate, and a gate electrode having a first height t1 disposed above the gate insulating film ;
A gate contact in contact with the gate electrode;
A first metal wire having a second height t2, wherein t1 <t2, which is electrically connected to the gate contact;
Source and drain contacts that are arranged at equal intervals in a matrix of (n + 1) × (m + 1) so as to form a square vertex centered on the gate electrode, and are in contact with the doped region except for the lower end of the gate insulating film; And
And a second metal wire having a third height (t3, where t2 < t3) is electrically connected to the source and drain contacts.

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