KR20110078068A - Method for fabricating gate of flash memory device and structure thereof - Google Patents

Abstract

PURPOSE: A method and structure for forming a gate of a flash memory device is provided to prevent a voltage drop due to the resistance of a floating gate poly by removing an ONO dielectric layer on a select gate forming area. CONSTITUTION: A tunnel oxide layer(302) is formed on a semiconductor substrate(300). A first poly silicon layer(304) for a floating gate is formed on the upper side of the tunnel oxide layer. A gate insulation layer(306) is formed on the upper side of the first poly silicon layer. A second poly silicon layer(310) for a control gate is formed on the upper side of the first poly silicon layer. A select gate(314) and a control gate(316) are formed by etching the tunnel oxide layer and the first poly silicon layer for the floating gate.

Description

Gate forming method and structure of flash memory device {METHOD FOR FABRICATING GATE OF FLASH MEMORY DEVICE AND STRUCTURE THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to remove an ONO (Oxide-Nitride-Oxide) dielectric film of a select gate formation region when forming a select gate of a flash memory. The electrical connection is connected through a salicide poly rather than floating gate to improve voltage drop and control gate poly for select gate contact. A method and structure for forming a gate of a flash memory device to omit a cutting process of the).

In general, a flash memory device is a nonvolatile memory device capable of not only maintaining information stored in a memory cell but also electrically programming and erasing data even when power is not supplied.

Flash memory technology has been continuously developed while improving the cell structure in various forms, and these various cell types include stacked gate cells, split gate cells, and source side injection cells. There are many cells of source side injection cell and other structures.

The stack gate cell is formed by sequentially stacking a floating gate and a control gate. The stack gate cell is programmed by injecting electrons into the floating gate using channel hot electron injection. and information is erased by drawing out electrons that have been injected into the floating gate. Such a stack gate cell is widely used as a unit cell of a flash memory device because of its small size.

The flash memory device as described above forms an active area → well implantation → cell Vt adjust implant → tunnel oxide formation → floating gate formation → ONO deposition → removal of ONO / Poly in the logic domain → control gate poly deposition → control gate formation → source / drain implantation → salicide → PMD formation → metal / IMD formation

FIG. 1 is a schematic cross-sectional view of a control gate CG and a select gate SG formed on a semiconductor substrate in a cross-sectional schematic diagram of a conventional flash memory device according to a process sequence. FIG. 2 is a cross-sectional view of a select gate of a select gate. will be. In order to form such a select gate, conventionally, the control gate poly is formed by cutting the control gate poly in the logic control gate forming process of the flash memory device manufacturing process described above, and the electrical signal of the select gate is formed through the floating gate. Will be delivered.

However, in the conventional select gate forming method as described above, there is a problem in that a voltage drop occurs in the select gate due to the resistance of the floating gate poly, not the salicide state, when the electricity is applied to the floating gate, and also the control gate for forming the select gate. When the gate polykey is not cut sufficiently in the cutting process of the poly, a malfunction of the flash memory device may occur.

Accordingly, the present invention improves the voltage drop by removing the ONO film of the select gate formation region when forming the select gate of the flash memory so that the electrical connection of the select gate is connected through the salicide poly instead of the floating gate. The present invention provides a method and structure for forming a gate of a flash memory device, which can omit the cutting process of the control gate poly for the contact.

According to the present invention, a method of forming a gate of a flash memory device includes: forming a tunnel oxide film on a semiconductor substrate, forming a first polysilicon film for a floating gate on the tunnel oxide film, and forming the first polysilicon layer; Forming a gate insulating film over the film, removing the gate insulating film in the select gate formation region on the semiconductor substrate, forming a second poly silicon film for the control gate over the first poly silicon film; Etching the first and second polysilicon layers in order to form a select gate and a control gate on the semiconductor substrate.

The removing of the gate insulating layer may include applying a photoresist layer on the gate insulating layer, patterning the photoresist layer through a photolithography process to open the select gate formation region, and removing the patterned photoresist layer. And removing the gate insulating film of the select gate formation region as a mask.

The present invention also provides a gate structure of a flash memory device, comprising: a tunnel oxide film formed in a select gate and a control gate region on a semiconductor substrate, a first polysilicon film for floating gate formed on the tunnel oxide film, and the first poly A gate insulating film formed only in the control gate region of the upper part of the silicon film, and a second poly silicon film for control gate formed on the first poly silicon film.

The present invention relates to a method of forming a gate of a flash memory device, wherein when the select gate of the flash memory is formed, the ONO dielectric layer of the select gate forming region is removed so that the electrical connection of the select gate is not a floating gate but a salicide (not a floating gate). It is advantageous to improve the voltage drop due to the resistance of the floating gate poly by connecting through a poly (salicide) state. In addition, the control gate pull does not need to be cut for select gate contact when forming the logic control gate, eliminating device malfunction due to underetch and overlay miss alignment of the control gate pull. There is an advantage that can be prevented.

Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the present invention. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

3A to 3G are cross-sectional views illustrating a method of forming a gate of a flash memory according to an exemplary embodiment of the present invention. Hereinafter, a gate forming process of the flash memory device of the present invention will be described in detail with reference to FIGS. 3A to 3G.

First, as shown in FIG. 3A, a tunnel oxide layer 302 is formed on a semiconductor substrate 300, and thereafter, a first poly-silicon layer for floating gate ( 304 and the gate insulating film 306 are formed in this order. In this case, the gate insulating layer 306 is formed of an ONO dielectric film composed of an oxide-nitride-oxide (Oxide-Nitride-Oxide). In this case, the first polysilicon film 304 may be formed to a thickness of 900 to 1000 kPa.

Subsequently, as shown in FIG. 3B, a photoresist layer is applied to the entire upper surface of the gate insulating layer 306, and then a photo is applied to the select gate formation region on the region of the semiconductor substrate 300. The photoresist layer is patterned through a photo-lithography process to form a photoresist mask 308.

Subsequently, as shown in FIG. 3C, the gate insulating layer 306 deposited in the select gate formation region on the region of the semiconductor substrate 300 is etched and removed using the patterned photoresist mask 308. As in 3d, the photoresist mask 308 is ashed to obtain a gate insulating film pattern in which the gate insulating film 306 is removed only in the select gate formation region.

Thereafter, as shown in FIG. 3E, the second polysilicon film 310 for the control gate is formed on the entire upper surface of the gate insulating film 306. In this case, the second polysilicon film may be formed to a thickness of 2000 to 2100 kPa.

Subsequently, as shown in FIG. 3F, after the photoresist film is coated on the entire upper surface of the second polysilicon film 310 for the control gate, a select gate forming region and a control gate on the region of the semiconductor substrate 300 are formed. A photoresist mask 312 is formed by patterning a photoresist film coated in addition to the) forming area through a photolithography process.

Next, as shown in FIG. 3G, the second poly for control gate deposited in a region other than the select gate forming region and the control gate forming region on the semiconductor substrate 300 using the patterned photoresist mask 312. The silicon film 310, the gate insulating film 306 having an ONO dielectric film structure, the first polysilicon film 304 for floating gates, and the tunnel oxide film 302 are sequentially etched to control the select gate 314 and the control. The gate 316 is formed.

As described above, after the select gate 314 and the control gate 316 of the flash memory device are formed, a lightly doped drain (LDD) forming process and a spacer nitride process may be performed in a subsequent process. A flash memory device is formed by performing a source / drain implantation process, a salicide, and a pre-metal dielectric (PMD) forming process.

4 illustrates a cross-sectional schematic diagram of a flash memory device that has been subjected to the PMD process. In the case of the select gate 314, the second poly in the salicide state is formed through the salicide layer 400 instead of the floating gate. The electrical connection by the silicon film reduces the effect of voltage drop due to the resistance of the floating gate poly.

It also eliminates the need to cut the control gate poly for select gate contact when forming a logic control gate, eliminating the underetch and overlay miss align of the control gate poly. Problems can be prevented.

As described above, in the present invention, as a gate forming method of a flash memory device, when the select gate of the flash memory is formed, the ONO dielectric film of the select gate forming region is removed, so that the electrical connection of the select gate is not connected to the floating gate. Improves the voltage drop caused by the resistance of the floating gate poly by connecting through it, and also eliminates underetch and overlay miss of the control gate poly by eliminating the need to cut the control gate poly for select gate contact when forming a logic control gate. It is possible to prevent the device from malfunctioning due to an overlay miss align.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should not be limited by the described embodiments but should be defined by the appended claims.

1 is a schematic cross-sectional view of a gate formation of a conventional flash memory device;

2 is an exemplary SEM photograph of a select gate contact of a conventional flash memory device;

3A to 3G are flowcharts illustrating a gate forming process of a flash memory device according to an embodiment of the present invention;

4 is a schematic cross-sectional view of a gate of a flash memory device according to an embodiment of the present invention.

<Brief description of the major symbols in the drawings>

302 Tunnel oxide film 304 First polysilicon film

306: gate insulating film 310: second polysilicon film

Claims (9)

A method of forming a gate of a flash memory device, Forming a tunnel oxide film on the semiconductor substrate; Forming a first polysilicon film for a floating gate on the tunnel oxide film; Forming a gate insulating film on the first polysilicon film; Removing a gate insulating film of a select gate formation region on the semiconductor substrate; Forming a second polysilicon film for a control gate on the first polysilicon film; Etching the first and second polysilicon layers sequentially to form a select gate and a control gate on the semiconductor substrate Gate forming method of a flash memory device comprising a. The method of claim 1, The gate insulating film removing step, Applying a photoresist film on the gate insulating film; Patterning the photoresist film through a photolithography process to open the select gate formation region; Removing the gate insulating film of the select gate formation region using the patterned photoresist film as a mask; Gate forming method of a flash memory device comprising a. The method of claim 1, The gate insulating film, A method of forming a gate of a flash memory device, characterized in that it is formed of an ONO dielectric film. The method of claim 1, The first polysilicon film, A gate forming method of a flash memory device, characterized in that formed in a thickness of 900 ~ 1000∼. The method of claim 1, The second polysilicon film, A gate forming method of a flash memory device, characterized in that formed at a thickness of 2000 to 2100 microseconds. As a gate structure of a flash memory device, A tunnel oxide film formed in the select gate and control gate regions on the semiconductor substrate; A first polysilicon film for floating gate formed on the tunnel oxide film; A gate insulating layer formed only in the control gate region of the first polysilicon layer; The second polysilicon film for the control gate formed on the first polysilicon film Gate structure of the flash memory device comprising a. The method of claim 6, The gate insulating film, A gate structure of a flash memory device, characterized in that formed from an ONO dielectric film. The method of claim 6, The first polysilicon film, A gate structure of a flash memory device, characterized in that formed to a thickness of 900 ~ 1000∼. The method of claim 6, The second polysilicon film, The gate structure of a flash memory device, characterized in that formed to a thickness of 2000 ~ 21002.

Images