KR20110077952A - Semiconductor package and manufacturing method for the same - Google Patents

Semiconductor package and manufacturing method for the same Download PDF

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KR20110077952A
KR20110077952A KR1020090134653A KR20090134653A KR20110077952A KR 20110077952 A KR20110077952 A KR 20110077952A KR 1020090134653 A KR1020090134653 A KR 1020090134653A KR 20090134653 A KR20090134653 A KR 20090134653A KR 20110077952 A KR20110077952 A KR 20110077952A
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semiconductor chip
encapsulant
emc
substrate
layer
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KR1020090134653A
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Korean (ko)
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최재경
류지형
이만진
반재승
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주식회사 하이닉스반도체
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Publication of KR20110077952A publication Critical patent/KR20110077952A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A semiconductor package and a manufacturing method thereof are provided to decrease the thickness of the semiconductor package by not requiring a gap for moving EMC(Epoxy Molding Compound) between a semiconductor chip and the ceiling of a mold. CONSTITUTION: A die sawed semiconductor chip(300) is mounted on a substrate(100). A semiconductor chip is attached to the substrate using a first adhesive layer(210). A bonding wire(250) is electrically connected to the pad of the substrate and the semiconductor chip. A first encapsulant film(400) is attached to the upper side of the semiconductor chip. A first encapsulant film includes an EMC layer(430) made of EMC components and a second adhesive layer(410).

Description

반도체 패키지 및 제조방법{Semiconductor package and manufacturing method for the same}Semiconductor package and manufacturing method for the same

본 발명은 반도체 패키지에 관한 것으로, 특히, 얇은 두께를 가지는 반도체 패키지 및 제조방법에 관한 것이다. The present invention relates to a semiconductor package, and more particularly, to a semiconductor package and a manufacturing method having a thin thickness.

반도체 패키지는 반도체 칩을 보호하고, 반도체 칩이 기판에 실장될 수 있도록 만들어 주는 공정이다. 반도체 칩을 보호하기 위해서 에폭시몰딩컴파운드(EMC)와 같은 봉지재를 충진하고 있다. 봉지재는 반도체 칩을 감싸게 몰딩되어, 외부 환경으로부터 반도체 칩을 보호한다. 봉지재를 충진할 때, 금형(mold)과 반도체 칩 사이에 어느 정도의 간극을 유지해야 봉지재의 유동성을 확보할 수 있다. 이러한 간극이 유지되지 못할 경우, 봉지재의 유동 한계에 의해 충진되지 못하는 불량이 유발될 수 있다. 따라서, 반도체 패키지는 반도체 칩 두께보다는 상당히 큰 두께로 제작되고 있다. A semiconductor package is a process that protects a semiconductor chip and makes it possible to mount the semiconductor chip on a substrate. In order to protect a semiconductor chip, an encapsulant such as an epoxy molding compound (EMC) is filled. The encapsulant is molded to enclose the semiconductor chip, thereby protecting the semiconductor chip from the external environment. When filling the encapsulant, it is necessary to maintain a certain gap between the mold and the semiconductor chip to ensure the fluidity of the encapsulant. If this gap is not maintained, a defect that cannot be filled by the flow limit of the encapsulant may be caused. Therefore, the semiconductor package is manufactured to be considerably larger than the semiconductor chip thickness.

휴대용 전자 제품의 제품 크기 및 두께가 점점 감소되고 있어, 시장에서 요구되는 반도체 패키지의 크기 및 두께도 점차 작고 얇아지고 있다. 더욱 작고 얇은 반도체 패키지 제품에 대한 요구가 증대되고 있다. 그런데, 패키지 금형 몰딩시 금 형 내에서의 봉지재의 유동성을 확보하여 흐름을 방해하지 않아야 되므로, 반도체 패키지 크기 및 두께 감소는 제한적이게 된다. 즉, 봉지재의 유동 흐름을 고려할 때, 반도체 칩과 금형 천정과 상당한 간극을 두어야 하므로, 패키지의 두께는 일정 두께 이상으로 유지되게 된다. As the size and thickness of portable electronic products are decreasing, the size and thickness of semiconductor packages required in the market are also becoming smaller and thinner. There is an increasing demand for smaller and thinner semiconductor package products. However, since package fluid molding does not impede the flow by securing the fluidity of the encapsulant in the mold, the semiconductor package size and thickness reduction is limited. That is, considering the flow flow of the encapsulant, the gap between the semiconductor chip and the mold ceiling should be a significant gap, so that the thickness of the package is maintained above a certain thickness.

이와 같이 몰딩되는 봉지재의 두께를 줄이기 어려우므로, 반도체 패키지의 두께를 줄이기 위해서, 반도체 칩 뒷면을 연마하여 반도체 칩의 두께를 보다 더 얇게 줄여, 금형과 칩 간의 공간을 확보하는 방안이 고려될 수 있다. 그런데, 이러한 경우 칩 뒷면 연마 비용의 상승이 수반되고, 또한 반도체 칩 두께 감소에 따른 칩 손상 또는 파괴가 손쉽게 발생되는 문제가 유발될 수 있다. 한편, 봉지재를 가루 형태로 제작하고, 이를 열 압착하여 패키지를 형성하는 방법이 고려될 수 있다. 그러나, 이러한 봉지재는 패키지 몰딩 장비를 교체해야 성형이 가능하고, 또한, 봉지재 자체의 가격이 비싸 제조 빙용 증가를 수반한다. Since it is difficult to reduce the thickness of the molded encapsulant as described above, in order to reduce the thickness of the semiconductor package, a method of securing a space between the mold and the chip may be considered by reducing the thickness of the semiconductor chip by making the back side of the semiconductor chip thinner. . In this case, however, the cost of polishing the back surface of the chip may be accompanied, and the problem of chip damage or destruction caused by the reduction of the thickness of the semiconductor chip may easily occur. Meanwhile, a method of manufacturing the encapsulant in powder form and thermally compressing the encapsulant may be considered. However, such encapsulant can be molded only by replacing the package molding equipment, and the encapsulant itself is expensive and entails an increase in manufacturing ice.

본 발명은 봉지재 충진 시 충진 불량을 억제하며 반도체 패키지의 두께를 줄일 수 있는 반도체 패키지 구조 및 제조방법을 제시하고자 한다. The present invention is to propose a semiconductor package structure and a manufacturing method that can suppress the filling defects when filling the encapsulant and reduce the thickness of the semiconductor package.

본 발명의 일 관점은, 기판 상에 반도체 칩을 실장하는 단계; 상기 반도체 칩 상에 제1봉지재 필름(film)을 부착하는 단계; 및 상기 반도체 칩 및 상기 봉지재 필름 측부에 제2봉지재를 충진하는 몰딩(molding) 단계를 포함하는 반도체 패키지 제조방법을 제시한다. One aspect of the invention, the step of mounting a semiconductor chip on a substrate; Attaching a first encapsulant film on the semiconductor chip; And a molding step of filling a second encapsulant into the semiconductor chip and the encapsulant film side.

상기 반도체 칩과 상기 기판을 전기적으로 연결하는 본딩 와이어(bonding wire)를 연결하는 단계를 더 포함할 수 있다. The method may further include connecting a bonding wire electrically connecting the semiconductor chip and the substrate.

상기 제1봉지재 필름은 상기 본딩 와이어가 퍼네트레이션(penetration)되며 상기 반도체 칩 상에 부착되는 접착층; 및 상기 접착층 상의 제1봉지재층을 포함할 수 있다. The first encapsulant film may include an adhesive layer on which the bonding wires are connected and attached to the semiconductor chip; And a first encapsulant layer on the adhesive layer.

본 발명의 다른 일 관점은, 기판 상에 실장된 반도체 칩; 상기 반도체 칩 상에 부착된 제1봉지재 필름(film); 및 상기 반도체 칩 및 상기 봉지재 필름 측부에 몰딩(molding)으로 충진된 제2봉지재를 포함하는 반도체 패키지를 제시한다. Another aspect of the invention, the semiconductor chip mounted on the substrate; A first encapsulant film attached to the semiconductor chip; And a second encapsulation material filled in the semiconductor chip and the encapsulant film side by molding.

본 발명의 실시예는 봉지재 충진 시 충진 불량을 억제하며 반도체 패키지의 두께를 줄일 수 있는 반도체 패키지 구조 및 제조방법을 제시할 수 있다. Embodiments of the present invention can provide a semiconductor package structure and a manufacturing method that can suppress the filling defects when filling the encapsulant and reduce the thickness of the semiconductor package.

본 발명의 실시예는 반도체 칩 상면에 봉지재의 물성을 가진 얇은 박막 필름, 즉, 봉지재 필름을 미리 붙이고, 연후에 봉지재 충진을 위한 몰딩, 예컨대 EMC 몰딩을 수행한다. 반도체 칩 상면과 충진 금형 사이에 봉지재 필름이 이미 부착된 상태이므로, EMC 봉지재는 봉지재 필름 주변만을 충진하게 된다. 따라서, 금형 천정과 반도체 칩 상면 간의 간극이 불필요하며, 반도체 칩 상면에 EMC 충진이 불필요하다. 따라서, 이러한 반도체 칩 상면에 EMC 봉지재의 불완전 충진이 발생하는 것을 유효하게 방지할 수 있다. 박막 패키지 EMC 봉지재 충진 시 칩 상면과 충진 금형 사이의 공간적인 제약을 극복할 수 있다. 봉지재 박막은 일반 EMC 봉지재의 경화 후 색과 유사한 색 및 물성을 지니므로, 일반 EMC 봉지재를 사용하여 충진하는 경우와 대등한 외관을 가질 수 있다. According to an embodiment of the present invention, a thin thin film having a physical property of an encapsulant, that is, an encapsulant film is previously attached to an upper surface of a semiconductor chip, and then molding for encapsulant filling, for example, EMC molding is performed. Since the encapsulant film is already attached between the upper surface of the semiconductor chip and the filling mold, the EMC encapsulant fills only the encapsulant film periphery. Therefore, the gap between the mold ceiling and the upper surface of the semiconductor chip is unnecessary, and EMC filling is unnecessary on the upper surface of the semiconductor chip. Therefore, incomplete filling of the EMC encapsulant on the upper surface of such semiconductor chips can be effectively prevented. When filling thin film packaged EMC encapsulants, the spatial constraints between the top of the chip and the filling die can be overcome. Since the encapsulant thin film has a color and physical properties similar to the color after curing of the general EMC encapsulation material, the encapsulant thin film may have a appearance that is comparable to that of filling using the general EMC encapsulant.

도 1 내지 도 3은 본 발명의 실시예에 따른 반도체 패키지 및 제조방법을 보여주는 도면들이다.  1 to 3 are diagrams illustrating a semiconductor package and a manufacturing method according to an embodiment of the present invention.

도 1을 참조하면, 인쇄회로기판(PCB: 100) 상에 반도체 칩(300)을 실장한다. 기판(100)은 배선 및 솔더 볼(solder ball: 150)을 구비하는 볼그리드어레이(BGA) 형태의 기판으로 도입될 수 있지만, 이에 한정되지 않고 다양한 형태의 패키지 기판이 이용될 수 있다. 기판(100) 상에 다이 소잉(die sawing)된 반도체 칩(300)을 제1접착층(210)을 이용하여 부착한다. 반도체 칩(300)의 하면에 제1접착층(250)이 접착된 상태로 기판(100) 상으로 이송되고, 기판(100) 상에 반도체 칩(300)이 실장되어 제1접착층(210)에 의해 접착 고정된다. Referring to FIG. 1, a semiconductor chip 300 is mounted on a printed circuit board (PCB) 100. The substrate 100 may be introduced as a ball grid array (BGA) type substrate including wiring and solder balls 150, but various types of package substrates may be used. The die sawing semiconductor chip 300 is attached onto the substrate 100 using the first adhesive layer 210. The first adhesive layer 250 is adhered to the lower surface of the semiconductor chip 300, and is transferred onto the substrate 100, and the semiconductor chip 300 is mounted on the substrate 100 to be bonded by the first adhesive layer 210. Adhesive is fixed.

반도체 칩(300)이 실장된 이후에, 기판(100)과 반도체 칩(300)의 패드(pad)를 전기적으로 연결하는 본딩 와이어(bonding wire: 250)를 연결하는 와이어 본딩 과정을 수행한다. After the semiconductor chip 300 is mounted, a wire bonding process is performed to connect a bonding wire 250 that electrically connects the substrate 100 and a pad of the semiconductor chip 300.

반도체 칩(300)을 실장한 후, 반도체 칩(300)의 상면에 제1봉지재 필름(400)을 부착한다. 제1봉지재 필름(400)은 EMC 성분의 EMC층(430)과 하부의 제2접착층(410)을 포함하게 구성될 수 있다. 또는 EMC층(430) 단독으로 구성될 수도 있다. EMC층(430)은 EMC 봉지재와 대등한 성분으로 박막화된 층으로서, 충진제가 함유된 열가소성 수지 또는 열경화성 수지의 층을 포함하여 박막으로 제조될 수 있다. After mounting the semiconductor chip 300, the first encapsulant film 400 is attached to an upper surface of the semiconductor chip 300. The first encapsulant film 400 may include an EMC layer 430 of the EMC component and a lower second adhesive layer 410. Alternatively, the EMC layer 430 may be configured alone. The EMC layer 430 is a thin layer made of a component equivalent to an EMC encapsulant, and may be made of a thin film including a layer of a thermoplastic resin or a thermosetting resin containing a filler.

제2접착층(410)은 EMC층(430)과 반도체 칩(300)을 접착시키는 역할을 하고, 또한, 본딩 와이어(250)가 연결된 경우, 이러한 본딩 와이어(250)가 제2접착층(410) 내로 퍼네트레이션(penetration)되게 유동성을 가지는 층으로 구성된다. 제2접착층(410) 내로 본딩 와이어(250)가 퍼네트레이션됨에 따라, 본딩 와이어(250)는 제2접착층(410)에 함몰되어 고정되게 되며, 상부의 EMC층(430)과 부딪혀 손상되는 것이 억제된다. 본딩 와이어(250)가 아닌 범프(bump) 형태로 반도체 칩(300)과 기판(100)이 전기적으로 연결될 경우에는, 제2접착층(410)이 생략되고, EMC층(410)만으로 제1봉지재 필름(400)이 구성될 수 있다. 이러한 제1봉지재 필름(400)은 반도체 칩(300)에 부착되며, 공정 상 여러 개의 반도체 칩(300)들에 한꺼번에 부착되는 형태로 적용될 수 있다. The second adhesive layer 410 serves to bond the EMC layer 430 and the semiconductor chip 300. In addition, when the bonding wire 250 is connected, the bonding wire 250 is introduced into the second adhesive layer 410. It is composed of layers which are fluidized to be penetrated. As the bonding wire 250 is networked into the second adhesive layer 410, the bonding wire 250 is recessed and fixed to the second adhesive layer 410 and is damaged by being bumped with the upper EMC layer 430. Suppressed. When the semiconductor chip 300 and the substrate 100 are electrically connected to each other in a bump form instead of the bonding wire 250, the second adhesive layer 410 is omitted, and the first encapsulant only by the EMC layer 410. Film 400 may be constructed. The first encapsulant film 400 may be attached to the semiconductor chip 300, and may be applied in the form of being attached to a plurality of semiconductor chips 300 at a time.

도 2를 참조하면, 반도체 칩(300)이 실장된 기판(100)을 금형(500) 내에 장착한다. 이때, 금형(500)의 천정(501)이 제1봉지재 필름(400)에 맞닿게 장착한다. 즉, 금형(500)과 제1봉지재 필름(400) 간에 간극을 확보할 필요가 없다. 이에 따라, 제1봉지재 필름(400)의 두께를 얇게 도입하는 만큼 전체 패키지의 두께 감소를 구현할 수 있어, 보다 얇은 반도체 패키지를 구현할 수 있다. Referring to FIG. 2, the substrate 100 on which the semiconductor chip 300 is mounted is mounted in the mold 500. At this time, the ceiling 501 of the mold 500 is mounted to abut the first encapsulant film 400. That is, it is not necessary to secure a gap between the mold 500 and the first encapsulant film 400. Accordingly, as the thickness of the first encapsulant film 400 is introduced to be thin, the thickness of the entire package may be reduced, and a thinner semiconductor package may be realized.

제2봉지재로 EMC를 주입하여 금형(500) 내를 충진시키는 몰딩 과정을 수행한다. 이때, EMC는 반도체 칩(300) 및 제1봉지재 필름(400)의 측부에 확보된 공간(502)에 충진된다. 이에 따라, 도 3에 제시된 바와 같이, 반도체 칩 상면은 부착된 제1봉지재 필름(400)에 의해 보호되고, 반도체 칩 측면은 EMC 몰딩된 제2봉지재층(600)으로 보호되는 반도체 패키지가 구현된다. 반도체 패키지의 전체 두께는 기판(100), 반도체 칩(300) 및 제1봉지재 필름(400)의 두께 등에 의존하므로, 제1봉지재 필름(400)을 얇게 도입함으로써 반도체 패키지 전체 두께를 보다 얇게 구현할 수 있다. 또한, 제2봉지재가 EMC 주입될 때, 반도체 칩(300) 상면 부분으로 주입될 필요가 없고, 실질적으로 제1봉지재 필름(400)과 금형(500)의 천정(501)이 맞닿아 있으므로, 이들 사이로 EMC 주입이 일어나지 않게 된다. 따라서, 반도체 칩(300)과 금형(500) 천정(501) 사이에 EMC 유동을 위한 간극을 확보할 필요가 없으므로, 전체 반도체 패키지의 두께는 보다 더 얇게 구현될 수 있다. Injecting the EMC into the second encapsulant to perform a molding process for filling the mold 500. At this time, the EMC is filled in the space 502 secured to the sides of the semiconductor chip 300 and the first encapsulant film 400. Accordingly, as shown in FIG. 3, the semiconductor package having the upper surface of the semiconductor chip protected by the first encapsulant film 400 attached thereto and the side surface of the semiconductor chip protected by the EMC encapsulated second encapsulant layer 600 is implemented. do. Since the overall thickness of the semiconductor package depends on the thicknesses of the substrate 100, the semiconductor chip 300, and the first encapsulant film 400, the thickness of the first encapsulant film 400 is reduced to make the entire semiconductor package thinner. Can be implemented. In addition, when the second encapsulation material is EMC-injected, the second encapsulation material does not need to be injected into the upper surface portion of the semiconductor chip 300, and the first encapsulant film 400 and the ceiling 501 of the mold 500 are in contact with each other. There is no EMC injection between them. Therefore, since there is no need to secure a gap for the EMC flow between the semiconductor chip 300 and the ceiling of the mold 500, the thickness of the entire semiconductor package may be made thinner.

도 1 내지 도 3은 본 발명의 실시예에 따른 반도체 패키지 및 제조방법을 보여주는 도면들이다. 1 to 3 are diagrams illustrating a semiconductor package and a manufacturing method according to an embodiment of the present invention.

Claims (11)

기판 상에 반도체 칩을 실장하는 단계;Mounting a semiconductor chip on a substrate; 상기 반도체 칩 상에 제1봉지재 필름(film)을 부착하는 단계; 및Attaching a first encapsulant film on the semiconductor chip; And 상기 반도체 칩 및 상기 봉지재 필름 측부에 제2봉지재를 충진하는 몰딩(molding) 단계를 포함하는 반도체 패키지 제조방법. And a molding step of filling a second encapsulant into the semiconductor chip and the encapsulant film side. 제1항에 있어서,The method of claim 1, 상기 반도체 칩과 상기 기판을 전기적으로 연결하는 본딩 와이어(bonding wire)를 연결하는 단계를 더 포함하는 반도체 패키지 제조방법. And connecting a bonding wire electrically connecting the semiconductor chip and the substrate. 제2항에 있어서,The method of claim 2, 상기 제1봉지재 필름은 The first encapsulant film is 상기 본딩 와이어가 퍼네트레이션(penetration)되며 상기 반도체 칩 상에 부착되는 접착층; 및An adhesive layer on which the bonding wires are connected and attached to the semiconductor chip; And 상기 접착층 상의 제1봉지재층을 포함하는 반도체 패키지 제조방법. A semiconductor package manufacturing method comprising a first encapsulant layer on the adhesive layer. 제1항에 있어서,The method of claim 1, 상기 제1봉지재 필름은 The first encapsulant film is 상기 제2봉지재와 대등한 에폭시몰딩컴파운드(EMC)의 층을 포함하는 반도체 패키지 제조방법. A semiconductor package manufacturing method comprising a layer of epoxy molding compound (EMC) equivalent to the second encapsulant. 제1항에 있어서,The method of claim 1, 상기 제1봉지재 필름은 The first encapsulant film is 충진제가 함유된 열가소성 수지 또는 열경화성 수지의 층을 포함하는 반도체 패키지 제조방법. A semiconductor package manufacturing method comprising a layer of a thermoplastic resin or thermosetting resin containing a filler. 제1항에 있어서,The method of claim 1, 상기 몰딩 단계는The molding step 상기 반도체 칩이 실장된 상기 기판을 금형 내에 상기 제1봉지재 필름이 상기 금형의 천정에 맞닿게 장착하는 단계; 및Mounting the substrate on which the semiconductor chip is mounted so that the first encapsulant film abuts on the ceiling of the mold in a mold; And 상기 금형 내에 상기 제2봉지재로서 에폭시몰딩컴파운드(EMC)를 충진시키는 단계를 포함하는 반도체 패키지 제조방법. And filling an epoxy molding compound (EMC) into the mold as the second encapsulant. 기판 상에 실장된 반도체 칩; A semiconductor chip mounted on a substrate; 상기 반도체 칩 상에 부착된 제1봉지재 필름(film); 및A first encapsulant film attached to the semiconductor chip; And 상기 반도체 칩 및 상기 봉지재 필름 측부에 몰딩(molding)으로 충진된 제2봉지재를 포함하는 반도체 패키지. And a second encapsulation material filled in the semiconductor chip and the encapsulant film side by molding. 제7항에 있어서,The method of claim 7, wherein 상기 반도체 칩과 상기 기판을 전기적으로 연결하는 본딩 와이어(bonding wire)를 더 포함하는 반도체 패키지. And a bonding wire electrically connecting the semiconductor chip and the substrate. 제8항에 있어서,The method of claim 8, 상기 제1봉지재 필름은 The first encapsulant film is 상기 본딩 와이어가 퍼네트레이션(penetration)되며 상기 반도체 칩 상에 부착되는 접착층; 및An adhesive layer on which the bonding wires are connected and attached to the semiconductor chip; And 상기 접착층 상의 제1봉지재층을 포함하는 반도체 패키지. A semiconductor package comprising a first encapsulant layer on the adhesive layer. 제7항에 있어서,The method of claim 7, wherein 상기 제1봉지재 필름은 The first encapsulant film is 상기 제2봉지재와 대등한 에폭시몰딩컴파운드(EMC)의 층을 포함하는 반도체 패키지. A semiconductor package comprising a layer of epoxy molding compound (EMC) equivalent to the second encapsulant. 제7항에 있어서,The method of claim 7, wherein 상기 제1봉지재 필름은 The first encapsulant film is 충진제가 함유된 열가소성 수지 또는 열경화성 수지의 층을 포함하는 반도체 패키지. A semiconductor package comprising a layer of thermoplastic or thermoset resin containing filler.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10770311B2 (en) 2017-09-21 2020-09-08 Samsung Electronics Co., Ltd. Stack package and methods of manufacturing the same
US11804474B2 (en) 2021-03-09 2023-10-31 SK Hynix Inc. Stack packages and methods of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10770311B2 (en) 2017-09-21 2020-09-08 Samsung Electronics Co., Ltd. Stack package and methods of manufacturing the same
US11651975B2 (en) 2017-09-21 2023-05-16 Samsung Electronics Co., Ltd. Stack package and methods of manufacturing the same
US11929262B2 (en) 2017-09-21 2024-03-12 Samsung Electronics Co., Ltd. Stack package and methods of manufacturing the same
US11804474B2 (en) 2021-03-09 2023-10-31 SK Hynix Inc. Stack packages and methods of manufacturing the same

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