KR20100109042A - Semiconductor package and method for fabricating thereof - Google Patents

Semiconductor package and method for fabricating thereof Download PDF

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KR20100109042A
KR20100109042A KR1020090027424A KR20090027424A KR20100109042A KR 20100109042 A KR20100109042 A KR 20100109042A KR 1020090027424 A KR1020090027424 A KR 1020090027424A KR 20090027424 A KR20090027424 A KR 20090027424A KR 20100109042 A KR20100109042 A KR 20100109042A
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substrate
semiconductor chip
semiconductor package
semiconductor
stress
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KR1020090027424A
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Korean (ko)
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조철호
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주식회사 하이닉스반도체
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Publication of KR20100109042A publication Critical patent/KR20100109042A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE: A semiconductor package and a method for fabricating thereof are provided to improve the reliability of solder joint by forming a stress release layer on a semiconductor substrate. CONSTITUTION: A semiconductor package comprises a substrate(110), a semiconductor chip(150), a stress release layer(170), and an encapsulant(190). The semiconductor chip is laminated on one side of the substrate. The stress release layer covers one side of the substrate and the semiconductor chip. The stress release layer is formed with an elastic body and silicon. The encapsulant is formed on the stress release layer in order to cover one side of the substrate including the semiconductor chip. The stress release layer and the encpasulant are combined with each other through an adhesive.

Description

반도체 패키지 및 이의 제조방법{Semiconductor Package and method for fabricating thereof}Semiconductor package and method for manufacturing same

본 발명은 반도체 패키지에 관한 것으로, 보다 구체적으로는 솔더 조인트에 의한 접착 신뢰성을 향상시킬 수 있는 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of improving adhesion reliability by a solder joint.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전해 왔다. 예컨대, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장 작업의 효율성 및 실장 후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성이 부각되고 있다.In the semiconductor industry, packaging technology for integrated circuits has continually evolved to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technology for packages that are close to chip size, and the demand for mounting reliability is highlighted by the importance of packaging technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. It is becoming.

그러나, 반도체 패키지는 주기적으로 온도가 변화하는 환경에 노출될 경우, 기판과 반도체 칩, 보다 구체적으로는 기판과 봉지제 간의 열팽창 계수의 차이로 인하여 접착 불량이 발생하고 있다. 나아가, 반도체 패키지를 모듈 상에 실장할 경우, 패키지와 모듈 간의 열팽창 계수의 차이로 인하여 솔더 조인트 불량을 유발하는 문제가 있다.However, when a semiconductor package is exposed to an environment where temperature changes periodically, adhesion failure occurs due to a difference in thermal expansion coefficient between the substrate and the semiconductor chip, more specifically, the substrate and the encapsulant. Furthermore, when the semiconductor package is mounted on a module, there is a problem of causing solder joint defects due to a difference in thermal expansion coefficient between the package and the module.

즉, 반도체 패키지의 제작후 신뢰성 테스트(thermal cycle test)를 실시하면 접착 불량이 빈번하게 발생하고 있다. 이러한 접착 불량 원인은 기판과 봉지제 간의 열팽창 계수 차이에 의해 기판에 응력이 가해지는 데 기인한 것이다.That is, poor adhesion occurs frequently when a thermal cycle test is performed after fabrication of a semiconductor package. This poor adhesion cause is due to the stress applied to the substrate by the difference in thermal expansion coefficient between the substrate and the encapsulant.

특히, 반도체 패키지의 부품 중 기판은 모듈과 열팽창 계수가 유사하나 반도체 패키지를 외부의 투습이나 충격으로부터 보호하는 봉지제(epoxy :EMC)의 경우 기판과의 열팽창 계수의 편차가 심할 뿐만 아니라, 반도체 패키지에서 차지하는 부피가 큰 관계로 솔더 조인트 불량의 주요인이 되고 있다.In particular, among the components of the semiconductor package, the substrate has a similar coefficient of thermal expansion to the module, but in the case of an encapsulant (epoxy: EMC) that protects the semiconductor package from external moisture permeation or impact, the thermal expansion coefficient with the substrate is not only severe. Due to the large volume occupied by, it is a major cause of solder joint failure.

이러한 솔더 조인트 불량은 제품이 최종적으로 완성되고 난 후에 발생한다는 측면에서 그 대책이 시급한 상황이다.Such a solder joint defect is urgently needed in that it occurs after the product is finally finished.

본 발명의 실시예는 기판과 봉지제 간의 열팽창 계수 차이에 따른 접착 불량을 개선할 수 있는 반도체 패키지를 제공한다.An embodiment of the present invention provides a semiconductor package that can improve the adhesion failure due to the difference in thermal expansion coefficient between the substrate and the encapsulant.

본 발명의 실시예에 따른 반도체 패키지는 기판; 상기 기판의 일면 상에 적어도 하나 이상이 스택된 반도체 칩; 상기 반도체 칩과 상기 기판의 일면을 덮는 스트레스 완화층; 및 상기 스트레스 완화층 상에 상기 반도체 칩을 포함한 기판의 일면을 덮도록 형성된 봉지제를 포함하는 것을 특징으로 한다.A semiconductor package according to an embodiment of the present invention includes a substrate; At least one semiconductor chip stacked on one surface of the substrate; A stress relaxation layer covering one surface of the semiconductor chip and the substrate; And an encapsulant formed on the stress relief layer to cover one surface of the substrate including the semiconductor chip.

상기 스트레스 완화층은 탄성체 또는 실리콘으로 이루어진 것을 특징으로 한다. 상기 스트레스 완화층과 봉지제는 접착제를 매개로 접착된 것을 특징으로 한다. 상기 스트레스 완화층은 외부로 노출되는 것을 특징으로 한다.The stress relieving layer is characterized in that the elastic body or made of silicon. The stress relief layer and the encapsulant are characterized in that the adhesive is bonded through a medium. The stress relief layer is characterized in that it is exposed to the outside.

상기 기판의 타면에 부착된 외부접속단자를 더 포함한다. 상기 반도체 칩과 상기 기판을 전기적으로 연결하는 연결부재를 더 포함하는 것을 특징으로 한다.It further includes an external connection terminal attached to the other surface of the substrate. And a connection member electrically connecting the semiconductor chip and the substrate.

상기 스트레스 완화층은 상기 반도체 칩을 포함하는 상기 기판의 일면 상에 스트레스 완화 물질층을 스프레이 방식에 따라 도포한 후, 이를 경화시켜 구성한 것을 특징으로 한다.The stress relieving layer is formed by applying a stress relieving material layer on one surface of the substrate including the semiconductor chip according to a spray method and curing the same.

본 발명은 솔더 조인트 불량에 따른 생산 수율의 저하 문제를 개선할 수 있는 효과가 있다.The present invention has the effect of improving the problem of lowering the production yield due to solder joint failure.

--- 실시예 ------ Example ---

이하, 첨부한 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1과 도 2는 본 발명에 따른 반도체 패키지를 각각 나타낸 단면도이다. 특히, 도 1은 에지 패드의 페이스 업 방식의 BGA 패키지를, 도 2는 센터 패드의 페이스 다운 방식의 BGA 패키지를 각각 나타낸 것이다.1 and 2 are cross-sectional views illustrating semiconductor packages according to the present invention, respectively. In particular, FIG. 1 illustrates a face up BGA package of an edge pad, and FIG. 2 illustrates a face down BGA package of a center pad.

도 1에 도시한 바와 같이, 본 발명에 따른 에지 패드(edge pad)의 페이스 업 방식의 BGA 패키지(105)는 기판(110)과, 상기 기판(110) 상에 적어도 하나 이상이 페이스 업(face-up) 방식으로 접착제(160)를 매개로 스택된 반도체 칩(150)을 포함한다. 또한, 상기 스택된 반도체 칩(150)과 기판(110)을 덮는 스트레스 완화층(170)과, 상기 스택된 반도체 칩(150)과 스트레스 완화층(170)을 포함하는 기판(110)을 몰딩하는 봉지제(190)를 더 포함한다.As shown in FIG. 1, the BGA package 105 of an edge pad face up method according to the present invention has a substrate 110 and at least one face up on the substrate 110. a semiconductor chip 150 stacked via the adhesive 160 in a -up) manner. In addition, molding the stress relief layer 170 covering the stacked semiconductor chip 150 and the substrate 110, and molding the substrate 110 including the stacked semiconductor chip 150 and the stress relaxation layer 170. It further includes an encapsulant 190.

상기 스택된 반도체 칩(150)은 본딩 와이어(116)들에 의해 기판(110)과 전기적으로 접속된다. 보다 구체적으로는, 상기 스택된 반도체 칩(150)의 상면에 위치하는 본딩 패드(미도시)들과 기판(110) 상의 회로패턴(미도시)들은 본딩 와이어(116)에 의해 개별적으로 연결된다. 또한, 상기 기판(110)의 하부 면에는 반도체 칩(150)의 신호를 외부로 입출력하는 솔더볼(144)들이 솔더볼랜드(142)에 대응하여 부착된다.The stacked semiconductor chip 150 is electrically connected to the substrate 110 by bonding wires 116. More specifically, the bonding pads (not shown) positioned on the top surface of the stacked semiconductor chip 150 and the circuit patterns (not shown) on the substrate 110 are individually connected by the bonding wires 116. In addition, solder balls 144 for inputting and outputting signals from the semiconductor chip 150 to the lower surface of the substrate 110 are attached to the solder ball lands 142.

또한, 도 2에 도시한 바와 같이, 본 발명에 따른 센터 패드(center pad)의 페이스 다운 방식의 BGA 패키지(205)는 기판(210)과, 상기 기판(210) 상에 적어도 하나 이상이 페이스 다운(face-down) 방식으로 접착제(260)를 매개로 스택된 반도체 칩(250)을 포함한다. 또한, 상기 스택된 반도체 칩(250)과 기판(210)을 덮는 스트레스 완화층(270)과, 상기 스택된 반도체 칩(250)과 스트레스 완화층(270)을 포함하는 기판(210)을 몰딩하는 봉지제(290)를 더 포함한다.In addition, as shown in Figure 2, the BGA package 205 of the center pad (center pad) face down method according to the present invention is the substrate 210, at least one or more face down on the substrate 210; and a semiconductor chip 250 stacked via the adhesive 260 in a face-down manner. In addition, molding the stress relief layer 270 covering the stacked semiconductor chip 250 and the substrate 210, and molding the substrate 210 including the stacked semiconductor chip 250 and the stress relaxation layer 270. An encapsulant 290 is further included.

상기 스택된 반도체 칩(250)과 기판(210)의 중앙부에 대응된 본딩 와이어(216)들은 반도체 칩(250)의 하부면에 위치하는 본딩 패드(미도시)들과, 기판(210)의 하부면에 위치하는 회로패턴(미도시)들을 전기적으로 연결한다. 상기 반도체 칩(250)의 하부 면에는 본딩 와이어(216)들을 보호하기 위해 수지물질로 몰딩된 절연부재(245)가 형성된다. 또한, 상기 기판(210)의 하부 면에는 반도체 칩(250)의 신호를 외부로 입출력하는 솔더볼(244)들이 솔더볼랜드(242)에 대응하여 부착된다.Bonding wires 216 corresponding to the central portion of the stacked semiconductor chip 250 and the substrate 210 are bonding pads (not shown) disposed on the lower surface of the semiconductor chip 250, and a lower portion of the substrate 210. The circuit patterns (not shown) located on the surface are electrically connected. An insulating member 245 molded with a resin material is formed on the lower surface of the semiconductor chip 250 to protect the bonding wires 216. In addition, solder balls 244 for inputting and outputting signals from the semiconductor chip 250 to the lower surface of the substrate 210 are attached to the solder ball lands 242.

도 1 및 도 2에서 설명한 반도체 패키지에 있어서, 상기 스트레스 완화층(170, 270)은 반도체 칩(150, 250)과 봉지제(190, 290), 그리고 기판(110, 210)과 봉지제(190, 290)가 직접적으로 접촉하는 것을 방지하는 기능을 한다.In the semiconductor package described with reference to FIGS. 1 and 2, the stress relaxation layers 170 and 270 may include the semiconductor chips 150 and 250, the encapsulants 190 and 290, and the substrates 110 and 210 and the encapsulant 190. , 290 to prevent direct contact.

상기 스트레스 완화층(170, 270)은 탄성체(elastomer)와 실리콘(silicon)을 포함하는 흡수물질 중 어느 하나를 스프레이 방식(spray type)으로 도포하고 경화하는 것에 의해 형성할 수 있다. 상기 스트레스 완화층(170, 270)은 반도체 칩(150, 250)의 외부, 즉 봉지제(190, 290)의 측 단면의 외측으로 노출되도록 형성된다.The stress relief layers 170 and 270 may be formed by applying and curing any one of an absorbent material including an elastomer and a silicon in a spray type. The stress relaxation layers 170 and 270 are formed to be exposed to the outside of the semiconductor chips 150 and 250, that is, to the outside of the side cross-sections of the encapsulants 190 and 290.

도면으로 상세히 제시하지는 않았지만, 상기 스트레스 완화층(170, 270)과 봉지제(190, 290) 간의 사이 공간으로 접착제(미도시)가 더 개재될 수 있다. 이러한 접착제는 스트레스 완화층(170, 270)과 봉지제(190, 290) 간의 접착 특성을 개선하는 기능을 한다.Although not shown in detail in the drawings, an adhesive (not shown) may be further interposed between the stress relief layers 170 and 270 and the encapsulant 190 and 290. This adhesive serves to improve the adhesive properties between the stress relief layers 170, 270 and the encapsulant 190, 290.

이 때, 상기 스트레스 완화층은 반도체 패키지를 모듈에 실장하는 공정을 완료한 후, 신뢰성 테스트를 진행할 경우 열팽창 계수의 편차에 기인하여 봉지제가 수축 및 팽창하며 기판에 가하던 응력을 흡수하는 역할을 하게 된다.At this time, the stress relief layer is to complete the process of mounting the semiconductor package to the module, when the reliability test proceeds due to the variation in the coefficient of thermal expansion so that the encapsulant shrinks and expands to absorb the stress applied to the substrate do.

따라서, 본 발명에서와 같이, 기판과 반도체 칩을 덮는 스트레스 완화층을 형성하는 것을 통해 반도체 패키지와 모듈 간의 계면 응력을 감소시킬 수 있고, 나아가 솔더 조인트의 신뢰성을 개선할 수 있는 효과가 있다. 그 결과, 솔더 조인트 불량에 따른 생산 수율의 저하 문제를 해결할 수 있다.Therefore, as in the present invention, by forming a stress relaxation layer covering the substrate and the semiconductor chip, it is possible to reduce the interfacial stress between the semiconductor package and the module, and further improve the reliability of the solder joint. As a result, it is possible to solve the problem of lowering the production yield due to the solder joint failure.

이하, 첨부한 도면을 참조하여 본 발명에 따른 반도체 패키지의 제조방법에 대해 설명하도록 한다Hereinafter, a method of manufacturing a semiconductor package according to the present invention will be described with reference to the accompanying drawings.

도 3a 내지 도 3d는 본 발명에 따른 반도체 패키지의 제조방법을 공정 순서에 따라 순차적으로 나타낸 공정 단면도이다. 상기 반도체 패키지는 에지 패드의 페이스 업 방식의 BGA 패키지를 일 예로 도시하였다.3A to 3D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to the present invention in order of process. The semiconductor package is an example of a face-up BGA package of an edge pad.

도 3a에 도시한 바와 같이, 기판(310) 상에 적어도 하나 이상이 페이스 업 방식으로 접착제(360)를 매개로 스택된 반도체 칩(350)을 부착한다. 다음으로, 상기 스택된 반도체 칩(350)과 기판(310)을 본딩 와이어(316)를 통해 전기적으로 연결하는 본딩공정을 진행한다.As shown in FIG. 3A, at least one or more semiconductor chips 350 are stacked on the substrate 310 via the adhesive 360 in a face-up manner. Next, a bonding process of electrically connecting the stacked semiconductor chip 350 and the substrate 310 through a bonding wire 316 is performed.

다음으로, 도 3b에 도시한 바와 같이, 상기 스택된 반도체 칩(350)과 기판(310)의 상부 전면으로 탄성체(elastomer)와 실리콘(silicon)을 포함하는 물질 중 어느 하나를 스프레이 방식(spray type)으로 도포하여 스트레스 완화 물질층(370a)을 형성한다. 이 때, 상기 탄성체는 외력을 가해서 잡아당기면 일정 길이로 늘어나고 외력을 제거하면 원래의 길이로 돌아가는 성질을 가지는 고분자 화합물로 탄성 고무로 일컬어지는 가황고무가 대표적이라 할 수 있다.Next, as shown in FIG. 3B, any one of materials including an elastomer and a silicon is sprayed onto the stacked front surface of the semiconductor chip 350 and the substrate 310. ) To form a stress relieving material layer 370a. In this case, the elastic body is a polymer compound having a property of stretching to a certain length when pulled by applying an external force and returning to its original length when the external force is removed.

도 3c에 도시한 바와 같이, 상기 스트레스 완화 물질층(도 3b의 370a)을 일정 온도로 경화하는 공정을 진행하여 스택된 반도체 칩(350)과 기판(310)을 덮는 스트레스 완화층(370)을 형성한다. 특히, 상기 스트레스 완화층(370)은 스택된 반도체 칩(350)과 기판(310)이 외부로 노출되는 것을 완전히 차단할 수 있도록 측벽 및 상면을 완벽하게 밀봉해 주는 것이 바람직하다.As shown in FIG. 3C, a process of curing the stress relaxation material layer (370a of FIG. 3B) at a predetermined temperature is performed to cover the stacked semiconductor chip 350 and the substrate 310. Form. In particular, the stress mitigating layer 370 may completely seal the sidewall and the top surface so as to completely prevent the stacked semiconductor chip 350 and the substrate 310 from being exposed to the outside.

도 3d에 도시한 바와 같이, 상기 스트레스 완화층(370)과 반도체 칩(350)을 포함하는 기판(310)을 에폭시 몰딩 화합물(epoxy molding compound: EMC)을 이용한 몰딩 공정으로 봉지제(390)를 형성한다. 다음으로, 상기 기판(310)의 하부 면으로 반도체 칩(350)의 신호를 외부로 입출력하는 솔더볼(344)들을 솔더볼랜드(342)에 대응하여 부착한다.As shown in FIG. 3D, the encapsulant 390 is formed by molding the substrate 310 including the stress relaxation layer 370 and the semiconductor chip 350 by a molding process using an epoxy molding compound (EMC). Form. Next, solder balls 344 for inputting and outputting signals from and to the outside of the semiconductor chip 350 to the lower surface of the substrate 310 are attached to the solder ball lands 342.

이상으로, 본 발명에 따른 반도체 패키지(305)를 제작할 수 있다.As described above, the semiconductor package 305 according to the present invention can be manufactured.

본 발명에서는 기판(310) 및 반도체 칩(350)의 상부 전면으로 스트레스 완화층(370)을 추가 형성하는 것을 통해 봉지제(390)가 기판(310) 및 반도체 칩(350)과 직접적으로 맞닿는 것을 방지할 수 있다.In the present invention, the encapsulant 390 directly contacts the substrate 310 and the semiconductor chip 350 by additionally forming a stress mitigating layer 370 on the upper surface of the substrate 310 and the semiconductor chip 350. It can prevent.

전술한 방식에 의해 제작되는 반도체 패키지(305)는 모듈(미도시) 상에 실장하여 최종 제품화한 상태로 출하하게 된다. 이 때, 본 발명에서는 반도체 패키지(305)와 모듈 간의 열 팽창 계수의 편차에 기인하여 봉지제(370)가 수축 및 팽창하며 기판(310)에 가하던 응력이 스트레스 완화층(390)에 의해 경감될 수 있다.The semiconductor package 305 manufactured by the above method is mounted on a module (not shown) and shipped in a final product state. At this time, in the present invention, the encapsulant 370 shrinks and expands due to the variation in the coefficient of thermal expansion between the semiconductor package 305 and the module, and the stress applied to the substrate 310 is reduced by the stress relaxation layer 390. Can be.

그 결과, 최종 제품화 상태에서 반도체 패키지와 모듈 간의 계면 응력을 스트레스 완화층을 통해 최소화시키는 것이 가능하므로 솔더 조인트 불량에 따른 생산 수율의 저하 문제를 개선할 수 있는 효과가 있다.As a result, since it is possible to minimize the interfacial stress between the semiconductor package and the module through the stress relief layer in the final product state, there is an effect that can improve the production yield degradation problem due to the solder joint failure.

지금까지, 본 발명에서는 에지 패드 및 센터 패드 방식의 반도체 패키지에 대해 일관되게 설명하였으나, 이는 일 예에 불과한 것으로 대부분의 반도체 패키지에 동일하게 적용할 수 있다.Up to now, the present invention has been described consistently for the semiconductor package of the edge pad and the center pad method, but this is only an example and can be equally applied to most semiconductor packages.

따라서, 본 발명은 상기 실시예에 한정되는 것은 아니며, 본 발명의 정신 및 분야를 이탈하지 않는 범위내에서 다양하게 변경 및 변형할 수 있다는 것은 당업자에게 있어 자명한 사실일 것이다.Therefore, the present invention is not limited to the above embodiments, and it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and the field of the present invention.

도 1은 에지 패드의 페이스 업 방식의 BGA 패키지를 나타낸 단면도.1 is a cross-sectional view showing a face-up BGA package of the edge pad.

도 2는 센터 패드의 페이스 다운 방식의 BGA 패키지를 나타낸 단면도.Figure 2 is a cross-sectional view showing a face-down BGA package of the center pad.

도 3a 내지 도 3d는 본 발명에 따른 반도체 패키지의 제조방법을 공정 순서에 따라 순차적으로 나타낸 공정 단면도.3A to 3D are cross-sectional views sequentially showing a method of manufacturing a semiconductor package according to the present invention in the order of processing.

Claims (7)

기판;Board; 상기 기판의 일면 상에 적어도 하나 이상이 스택된 반도체 칩;At least one semiconductor chip stacked on one surface of the substrate; 상기 반도체 칩과 상기 기판의 일면을 덮는 스트레스 완화층; 및A stress relaxation layer covering one surface of the semiconductor chip and the substrate; And 상기 스트레스 완화층 상에 상기 반도체 칩을 포함한 기판의 일면을 덮도록 형성된 봉지제;An encapsulant formed on the stress relief layer to cover one surface of the substrate including the semiconductor chip; 를 포함하는 반도체 패키지.Semiconductor package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 스트레스 완화층은 탄성체 또는 실리콘으로 이루어진 것을 특징으로 하는 반도체 패키지.The stress relief layer is a semiconductor package, characterized in that made of an elastomer or silicon. 제 1 항에 있어서,The method of claim 1, 상기 스트레스 완화층과 봉지제는 접착제를 매개로 접착된 것을 특징으로 하는 반도체 패키지.The stress relief layer and the encapsulation agent is a semiconductor package, characterized in that bonded through the adhesive. 제 1 항에 있어서,The method of claim 1, 상기 스트레스 완화층은 외부로 노출되는 것을 특징으로 하는 반도체 패키지.The stress relief layer is a semiconductor package, characterized in that exposed to the outside. 제 1 항에 있어서,The method of claim 1, 상기 기판의 타면에 부착된 외부접속단자를 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package further comprises an external connection terminal attached to the other surface of the substrate. 제 1 항에 있어서,The method of claim 1, 상기 반도체 칩과 상기 기판을 전기적으로 연결하는 연결부재를 더 포함하는 것을 특징으로 하는 반도체 패키지.And a connecting member electrically connecting the semiconductor chip and the substrate. 제 1 항에 있어서,The method of claim 1, 상기 스트레스 완화층은 상기 반도체 칩을 포함하는 상기 기판의 일면 상에 스트레스 완화 물질층을 스프레이 방식에 따라 도포한 후, 이를 경화시켜 구성한 것을 특징으로 하는 반도체 패키지.The stress relief layer is a semiconductor package, characterized in that configured to apply a stress relief material layer on one surface of the substrate including the semiconductor chip by spraying, then cured it.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018184572A1 (en) * 2017-04-07 2018-10-11 宁波舜宇光电信息有限公司 Molding technique-based semiconductor packaging method and semiconductor device
CN108695165A (en) * 2017-04-07 2018-10-23 宁波舜宇光电信息有限公司 Method for packaging semiconductor based on molding process and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018184572A1 (en) * 2017-04-07 2018-10-11 宁波舜宇光电信息有限公司 Molding technique-based semiconductor packaging method and semiconductor device
CN108695165A (en) * 2017-04-07 2018-10-23 宁波舜宇光电信息有限公司 Method for packaging semiconductor based on molding process and semiconductor device

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