KR20110077665A - Non-overlapping clock generator - Google Patents
Non-overlapping clock generator Download PDFInfo
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- KR20110077665A KR20110077665A KR1020090134303A KR20090134303A KR20110077665A KR 20110077665 A KR20110077665 A KR 20110077665A KR 1020090134303 A KR1020090134303 A KR 1020090134303A KR 20090134303 A KR20090134303 A KR 20090134303A KR 20110077665 A KR20110077665 A KR 20110077665A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The present invention relates to a non-overlapping clock generator.
In the present invention, the first clock S1 is applied to the clock terminal CLK, and the input terminal D is connected to the second output terminal Q 'and the first output terminal of the D flip-flop DFF and the D flip-flop. An output terminal of the NAND gate ND and the NAND gate ND configured with a second input terminal IN2 to which Q is connected to the first input terminal IN1 and to which the second clock S2 is applied. It provides a non-overlapping clock generator that is connected to the input terminal of INV).
Here, the second clock S2 has the same waveform as the signal output after the first clock S1 is delayed for a predetermined time, and the signal output from the first output terminal Q is referred to as the first phase signal P1. The signal output from the inverter output terminal is referred to as the second phase signal P2.
PMOS transistor, NMOS transistor, NAND gate, NOR gate, inverter
Description
The present invention relates to a non-overlap clock generator. More specifically, it relates to a non-overlap clock generator in which a constant non-overlap interval always occurs regardless of P.V.T variation.
In order to construct a circuit such as a switched capacitor or a pump, a repeating signal having a certain period such as a clock (CLK) is used. A non-overlapping clock signal is used to prevent interference of the signal in a circuit operation. Is generated and supplied to the circuit.
In general, the non-overlapping clock signal is generated by a signal controller having a certain period generated by an oscillator so that the phase of the waveform does not change at the same time by a clock controller.
1 is a circuit diagram illustrating a conventional non-overlapping clock generator.
As shown in FIG. 1, two Nand Gates ND1 and ND2, two NOR Gates NR1 and NR2, and six Inverters I1 to I6 are used. It is composed.
Referring to the operation of the conventional non-overlapping clock generator as follows.
When the input signal is applied, the output signal after passing through the first inverter I1 and the second inverter I2 and the output signal after passing through the third inverter I3 and the fourth inverter I4 are two NAND gates ND1. ND2 and two NOR gates NR1 and NR2. The first NOR gate NR1 performs a NOR operation on two input signals and outputs a first clock A through a fifth inverter I5, and the first NAND gate ND1 performs NAND operation of two input signals. After that, the second clock B is output. The second NOR gate NR2 performs a NOR operation on two input signals and outputs a third clock C. The second NAND gate ND2 performs a NAND operation of two input signals, and then performs a sixth inverter I6. The fourth clock D is outputted through.
In this way, a plurality of inverters (I1 to I4) are connected in series to obtain a delay effect, and then inputted to each NOR gate (NR1, NR2) and NAND gates (ND1, ND2) to perform an operation, and the output is the inverter (I5, I6). By selectively connecting to generate a final clock, the signal does not change at the same time between the first clock (A) and the second clock (B), between the third clock (C) and the fourth clock (D) so that each output is Generate a non-overlapping clock that does not overlap, and the output is used as the system frequency.
However, the conventional technique as described above has a problem that the nonoverlap period may be changed because it is vulnerable to the P.V.T (Process, Supply Voltage, Temperature) fluctuation because the delay effect is generated by using an inverter.
The present invention is invented to solve the above-described problems, and its object is to provide a constant non-overlap interval at all times regardless of P.V.T (Process, Supply Voltage, Temperature) fluctuations.
According to the present invention, the first clock S1 is applied to the clock terminal CLK, and the input terminal D is connected to the second output terminal Q 'and the first output of the D flip-flop DFF and the D flip-flop. The output terminal of the NAND gate ND and the NAND gate ND configured as the second input terminal IN2 to which the terminal Q is connected to the first input terminal IN1 and to which the second clock S2 is applied is an inverter. It provides a non-overlapping clock generator that is connected to the input terminal of (INV).
Here, the second clock signal S2 has the same waveform as the signal output after the first clock signal S1 is delayed for a predetermined time, and the signal output from the first output terminal Q is converted into the first phase signal P1. The signal output from the output terminal of the inverter INV is referred to as a second phase signal P2.
Meanwhile, N (N is a natural number greater than 1) in which the signal input to the first input terminal is inverted and output through the second output terminal, and the signal input to the second input terminal is inverted and output through the first output terminal. It is composed of two oscillators. Each oscillator has the first and second output terminals of one neighboring oscillator sequentially connected to the first and second input terminals of the other oscillators, but the Nth oscillator has the first output terminal first. A phase delay clock generator is connected to the second input terminal of the second oscillator, and the second output terminal is connected to each of the first input terminals (cross connection).
Here, the oscillator sequentially connects the first PMOS transistor PM1 and the first NMOS transistor NM1 between the power supply terminal and the ground terminal in series, and simultaneously the second PMOS transistor PM2 between the power supply terminal and the ground terminal. ) And the second NMOS transistor NM2 are sequentially connected, and the gate of the first PMOS transistor PM1 is connected to the drain common connection point of the second PMOS transistor PM2 and the second NMOS transistor NM2. The gate of the second PMOS transistor PM2 may be connected to the drain common connection point of the first PMOS transistor PM1 and the first NMOS transistor NM1. In addition, a first capacitor may be connected between the first output terminal and the ground terminal, and a second capacitor may be connected between the second output terminal and the ground terminal.
Meanwhile, the phase delay clock generator includes a first output terminal OUT1 of the first oscillator OSC1 connected to a first input terminal IN3 of a second oscillator OSC2, and a second output terminal OUT2 of the second oscillator OSC1. The first output terminal OUT3 of the second oscillator OSC2 is connected to the input terminal IN4, and the first output terminal IN5 of the third oscillator OSC3 is connected to the second output terminal OUT4. 2 is connected to the input terminal IN6, the first output terminal OUT5 of the third oscillator OSC3 is connected to the first input terminal IN7 of the fourth oscillator OSC4, and the second output terminal OUT6 is Although sequentially connected to the second input terminal IN8, the first output terminal OUT7 of the fourth oscillator OSC4 is connected to the second input terminal IN2 of the first oscillator OSC1, and the second output terminal OUT7 is connected to the second input terminal IN8. The output terminal OUT8 may be connected to the first input terminal IN1.
According to the present invention, in implementing the circuit of the non-overlapping clock generator, it is possible to always provide a constant non-overlap interval regardless of PVT fluctuations, and the eight output signals have the effect of generating a clock whose phase is regularly delayed. have.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.
2 is a circuit diagram of a non-overlapping clock generator of the present invention.
As shown in FIG. 2, the first clock S1 is applied to the clock terminal CLK, and the input terminal D is connected to the D flip-flop DFF connected to the second output terminal Q '. The NAND gate ND and the NAND gate including the second input terminal IN2 to which the first output terminal Q of the D flip-flop is connected to the first input terminal IN1 and to which the second clock S2 is applied. The output terminal of (ND) is connected to the input terminal of the inverter INV.
The operation and effect of the present invention configured as described above will be described in detail.
It's like
3 is a timing diagram illustrating an operation process of FIG. 2.
The first output terminal Q of the D flip-flop DFF shown in FIG. 2 is initialized to a low state, and the second output terminal Q 'is initialized to a high state. .
As shown in FIG. 3, when the first clock S1 is applied to the clock terminal CLK of the D flip-flop DFF, the input terminal D of the D flip-flop DFF is the second output terminal Q. Since the first clock S1 is changed from a low state to a high state because of the connection with the '), the first output P1 becomes a high state. On the other hand, when the first clock S1 is changed from the high state to the low state, the previous output state is maintained and thus the first output P1 is kept high. Subsequently, when the first clock S1 is changed from the low state to the high state again, since the low state signal is output from the second output terminal Q 'and applied to the input terminal, the first output P1 is low. Becomes On the other hand, since the second clock S2 exhibits the same waveform as the signal output after the first clock S1 is delayed for a predetermined time, the first output signal P1 is maintained in the period in which the second clock S2 is maintained in the high state. Will remain high.
On the other hand, the NAND gate ND outputs a low state signal when all of the input signals are high, and outputs a high state signal in other cases. Therefore, when both the first output P1 and the second clock S2 are in a high state, a signal in a low state is output and the output signal becomes a second output P2 signal through the inverter INV. (P2) goes high. On the other hand, when either signal of the first output P1 and the second clock S2 becomes low, the NAND gate ND outputs a high state signal, and the output signal passes through the inverter INV. 2 output P2 goes low. Accordingly, when the first output P1 and the second output P2 are compared, the signal does not change at the same time, and thus may be used as a non-overlapping clock.
Next, a clock generator for generating a signal having a mutually delayed phase such as the first clock S1 and the second clock S2 will be described.
4 is a phase delay clock generator according to an exemplary embodiment of the present invention, and FIG. 5 is a circuit diagram of each oscillator of FIG. 4.
As shown in FIG. 4, in the present invention, the first output terminal OUT1 of the first oscillator OSC1 is connected to the first input terminal IN3 of the second oscillator OSC2, and the second output terminal OUT2. ) Is connected to the second input terminal IN4, the first output terminal OUT3 of the second oscillator OSC2 is connected to the first input terminal IN5 of the third oscillator OSC3, and the second output terminal. OUT4 is connected to the second input terminal IN6, the first output terminal OUT5 of the third oscillator OSC3 is connected to the first input terminal IN7 of the fourth oscillator OSC4, and the second The output terminal OUT6 is connected to the second input terminal IN8, the first output terminal OUT7 of the fourth oscillator OSC4 is connected to the second input terminal IN2 of the first oscillator OSC1, The second output terminal OUT8 is connected to the first input terminal IN1.
Here, the phase delay clock generator according to the present invention may be composed of N oscillators (N is a natural number greater than 1), and each oscillator may be configured of an oscillator having different first and second output terminals of one neighboring oscillator. Although the first and second input terminals are sequentially connected to each other, the Nth oscillator is configured such that the first output terminal is connected to the second input terminal of the first oscillator and the second output terminal is connected to the first input terminal (cross connection), respectively. do.
Meanwhile, as shown in FIG. 5, the first to fourth oscillators sequentially connect the first PMOS transistor PM1 and the first NMOS transistor NM1 between the power supply terminal and the ground terminal, and simultaneously The second PMOS transistor PM2 and the second NMOS transistor NM2 are sequentially connected between the power supply terminal and the ground terminal, and the gate of the first PMOS transistor PM1 is the second PMOS transistor PM2. And the drain common connection point of the second NMOS transistor NM2, and at the same time, the gate of the second PMOS transistor PM2 is connected to the drain common connection point of the first PMOS transistor PM1 and the first NMOS transistor NM1. It can be configured in connection. Here, the gate terminal of the second NMOS transistor NM2 becomes the first input terminal to which the first input signal IN1 is applied, and the gate terminal of the first NMOS transistor NM1 is the second input signal IN2. Is a second input terminal to which is applied, the drain common connection point of the first PMOS transistor PM1 and the first NMOS transistor NM1 is connected to the first output terminal, and the second PMOS transistor PM2 is connected to the first input terminal. The drain common connection point of the 2 NMOS transistor NM2 is connected to the second output terminal. A first delay means is connected between the first output terminal and the ground terminal to delay the output signal, and a second delay means is connected between the second output terminal and the ground terminal. The delay means is configured using a capacitor. Can be.
Referring to the operation and effect of the present invention configured as described in detail as follows.
First, referring to the operating principle of the oscillator of FIG. 5, when the first input signal is high and the second input signal is low, the second NMOS transistor NM2 is turned on, so that the second output OUT2 is turned on. The first PMOS transistor PM1 is turned on, but the first NMOS transistor NM1 is turned off, so the first output OUT1 is turned high. On the other hand, when the first input signal is low and the second input signal is high, since the first NMOS transistor NM1 is turned on, the first output OUT1 is turned low, and the second PMOS transistor PM2 is Although turned on, since the second NMOS transistor NM2 is turned off, the second output OUT2 is turned high. Accordingly, the first output OUT1 outputs a signal in which the second input signal is inverted, and the second output OUT2 outputs a signal in which the first input signal is inverted. The oscillator may be used as a clock generator because the output of the oscillator may be used as a clock.
On the other hand, since the first output (OUT1) and the second output (OUT2) needs a charging time of the capacitor between the output terminal and the ground terminal, the output is made after a predetermined time delay.
Next, the operation principle of the phase delay clock generator of FIG. 4 will be described.
6 is a timing diagram illustrating an operation of FIG. 4.
As shown in FIG. 4, the second oscillator OSC2 is initially initialized such that a high state signal is input to the first input terminal IN3, and a low state signal is input to the second input terminal IN4. It is. When the phase delay clock generator starts to operate, the second oscillator OSC2 outputs a high signal S2 from the first output terminal OUT3 to the first input terminal IN5 of the third oscillator OSC3. The low voltage signal S6 is output from the second output terminal OUT4 and supplied to the second input terminal IN6 of the third oscillator OSC3. On the other hand, the third oscillator OSC3 outputs a high signal S3 from the first output terminal OUT5 and supplies it to the first input terminal IN7 of the fourth oscillator OSC4, and the second output terminal ( The output signal S7 of the low state is output from the OUT6 and supplied to the second input terminal IN8. The fourth oscillator OSC4 outputs the high signal S4 from the first output terminal OUT7 and supplies it to the second input terminal IN2 of the first oscillator OSC1, and the second output terminal OUT8. Outputs the low signal S8 to the first input terminal IN1. Thereafter, the first oscillator OSC1 outputs a low signal S1 from the first output terminal OUT1 and supplies the first signal to the first input terminal IN3 of the second oscillator OSC2, and the second output terminal OUT2. ) Outputs a high signal S5 to the second input terminal IN4. Initially, the S1 signal was initialized to the high state and the S5 signal to the low state. However, once the circuit is cycled, the S1 signal is converted to the low state and the S5 signal is converted to the high state so that the second oscillator (OSC2) Supplied to. Thereafter, the second oscillator OSC2 outputs a low signal S2 at the first output terminal OUT3 and a high signal S6 at the second output terminal OUT4 to the third oscillator OSC3. The third oscillator OSC3 outputs the low signal S3 at the first output terminal OUT5 and the high signal S7 at the second output terminal OUT6 to output the fourth oscillator OSC4. To feed. The fourth oscillator OSC4 outputs the low signal S4 from the first output terminal OUT7 and supplies it to the second input terminal IN2 of the first oscillator OSC1, and the second output terminal OUT8. Outputs the high signal S8 to the first input terminal IN1. Accordingly, the first oscillator OSC1 outputs the high signal S1 at the first output terminal OUT1, and the second oscillator OS2 outputs the low signal S5 at the second output terminal OUT2. OSC2). On the other hand, since each oscillator has a capacitor connected between the output terminal and the ground terminal, the output is delayed during the capacitor charging time. Therefore, after the signal is supplied to the front oscillator, the signal supplied to the rear stage is supplied after the capacitor charging time is delayed. When the circuit is driven in this way, if the S1 signal is changed from the high state to the low state, after a certain time, the S2 signal is changed from the high state to the low state, and after a certain time, the S3 signal is changed from the high state to the low state. After a certain period of time, the S4 signal transitions from high to low. Even when the S1 signal is converted from the low state to the high state, the S2, S3, and S4 signals converted as described above are delayed.
On the other hand, the outputs of the signals S5 to S8 are output in the same manner as that of the signals S1 to S4. However, the S5 signal is a signal in which the S1 signal is inverted, so when the S1 to S4 signals go from the high state to the low state, the S5 to S8 signals go from the low state to the high state. Is converted to a state. Referring to the signals S1 to S8 as a whole, as shown in FIG. 6, it can be seen that the signals S2 to S8 are output in a gradually delayed state for a predetermined time after the state of the S1 signal is converted.
The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.
1 is a circuit diagram illustrating a conventional non-overlapping clock generator.
2 is a circuit diagram of a non-overlapping clock generator of the present invention.
3 is a timing diagram illustrating an operation of FIG. 2.
4 is a phase delay clock generator according to an embodiment of the present invention.
5 is a circuit diagram illustrating each oscillator of FIG. 4.
6 is a timing diagram illustrating an operation of FIG. 4.
<Description of the symbols for the main parts of the drawings>
ND1, ND2: NAND gate NR1, NR2: NOR gate
IN1 ~ IN6: Inverter DFF: D Flip-flop
PM1, PM2: PMOS transistor NM1, NM2: NMOS transistor
C1, C2: Capacitor CLK: Clock
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090134303A KR20110077665A (en) | 2009-12-30 | 2009-12-30 | Non-overlapping clock generator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090134303A KR20110077665A (en) | 2009-12-30 | 2009-12-30 | Non-overlapping clock generator |
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| Publication Number | Publication Date |
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| KR20110077665A true KR20110077665A (en) | 2011-07-07 |
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| KR1020090134303A KR20110077665A (en) | 2009-12-30 | 2009-12-30 | Non-overlapping clock generator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9130550B2 (en) | 2013-06-14 | 2015-09-08 | Samsung Electronics Co., Ltd. | Semiconductor device and method for operating the same |
| CN106130540A (en) * | 2016-07-05 | 2016-11-16 | 中国科学院上海微系统与信息技术研究所 | Broad-adjustable disjoint signals circuit and system |
-
2009
- 2009-12-30 KR KR1020090134303A patent/KR20110077665A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9130550B2 (en) | 2013-06-14 | 2015-09-08 | Samsung Electronics Co., Ltd. | Semiconductor device and method for operating the same |
| US9537470B2 (en) | 2013-06-14 | 2017-01-03 | Samsung Electronics Co., Ltd. | Semiconductor device and method for operating the same |
| CN106130540A (en) * | 2016-07-05 | 2016-11-16 | 中国科学院上海微系统与信息技术研究所 | Broad-adjustable disjoint signals circuit and system |
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