JP2009055470A - Noise canceler circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a noise canceler circuit capable of obtaining stable operation in simple configuration. <P>SOLUTION: A noise canceler circuit comprises: a delay circuit DC1 to which an input signal 100 is imparted and delayed just by a first delay amount and which outputs a delay signal 101; a logic circuit AN1 to which the input signal 100 and the delay signal 101 are imparted and logically operated and which outputs a signal 102; a delay circuit DC2 to which the signal 102 is imparted and delayed just by a second delay amount and which outputs a delay signal 103; and a logic circuit OR1 to which the signal 102 and the delay signal 103 are imparted and logically operated and which outputs a signal 104, and is characterized in that the second delay amount is greater than the first delay amount. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a noise removal circuit, and more particularly to an input circuit having an external input that needs to prevent malfunction due to noise.

  When an external signal is input, the input level fluctuates before and after the operating threshold of the amplifier provided in the input circuit due to noise from the outside or the power supply. If pulsed noise occurs, malfunction occurs in the subsequent circuit. Occurs.

Therefore, conventionally, in the input circuit,
(1) using a Schmitt input circuit having two operating thresholds;
(2) The high frequency noise included in the input signal is removed by using a C / R filter including a capacitor C and a resistor R, or (3) the input signal is captured in synchronization with the clock by one or more stages of shift registers. , Remove noise below the clock frequency,
Measures such as were taken.

  However, in the measures according to the above (1) and (2), with the advancement of semiconductor technology, the operation noise is increased due to the chip shrink effect, but the improvement of the operation sensitivity is required, and the noise removal becomes difficult.

  Further, in the EMC (Electro-Magnetic Compatibility) test, there is a problem that a sufficient noise removal effect cannot be obtained by the countermeasures (1) and (2).

  Since the measure according to the above (3) requires a clock, it cannot be used when the clock is stopped, and a signal having a frequency higher than the clock frequency cannot be captured.

  Furthermore, for example, when the input circuit has a crystal oscillation circuit, an input amplifier, etc., when the input signal has a small amplitude, has a sine wave, or operates at a low frequency, external noise, power supply noise, ground noise, etc. Is amplified in the vicinity of the operating threshold of the input amplifier, there is a problem that the counter or the like miscounts and does not operate normally.

  As a countermeasure, conventionally, a technique has been employed in which noise is removed by taking the countermeasures (1) and (2) above the crystal oscillation circuit and the input amplifier. However, in this case as well, sufficient noise removal is difficult as described above. Furthermore, there has been a problem that the maximum operating frequency is limited by the frequency characteristics of the Schmitt circuit and CR filter used as a countermeasure.

The literature name which disclosed the conventional noise removal technique is described.
JP 2001-148622 A

  An object of the present invention is to provide a noise removal circuit that can obtain a stable operation with a simple configuration.

  A noise removal circuit according to one embodiment of the present invention is provided with an input signal, a first delay circuit that outputs a first delay signal after being delayed by a first delay amount, the input signal, and the first delay And a first logic circuit that performs a first logical operation and outputs a first signal, and receives the first signal and delays by a second delay amount to generate a second delay. A second delay circuit that outputs a signal, and a second logic circuit that receives the first signal and the second delay signal, performs a second logical operation, and outputs a second signal. And the second delay amount is larger than the first delay amount.

  According to the noise removal circuit of the present invention, a stable operation can be obtained with a simple configuration.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(1) Embodiment 1
FIG. 1 shows the configuration of a noise removal circuit according to Embodiment 1 of the present invention.

  One input terminal of an AND circuit AN1 having two input terminals is connected to the input terminal IN1 of the noise elimination circuit, and a delay circuit DC1 is connected in series between the input terminal IN1 and the other input terminal of the AND circuit AN1. ing. Further, the output terminal of the AND circuit AN1 is connected to one input terminal of the OR circuit OR1 having an input terminal, and the delay circuit DC2 is connected in series between the output terminal of the AND circuit AN1 and the other input terminal of the OR circuit OR1. It is connected to the.

  For example, as shown in FIG. 2 as an input circuit, such a noise removal circuit NR1 is used by being connected to an output terminal of an inverter INV1 as an input amplifier having an input terminal connected to the input terminal IN of the semiconductor integrated circuit. .

  Here, the delay circuits DC1 and DC2 have a configuration in which a plurality of inverters DINV1 to DINV4 are connected in series as shown in FIG. 3, for example.

  The operation of the noise removal circuit according to the first embodiment will be described.

  Consider a case where an input signal having a digital waveform is input to an input circuit having a threshold value Vth as shown in FIG. FIG. 4B shows an enlarged waveform of the input signal. If high-frequency noise is present when falling from the high level to the low level, as shown in FIG. 4C, when the output signal falls from the high level to the low level, Is generated at a high frequency.

  Alternatively, consider a case where an input signal having a sine wave is input to an input circuit having a threshold value Vth as shown in FIG. FIG. 5B shows an enlarged waveform of the input signal. If high-frequency noise is present when falling from the high level to the low level, as shown in FIG. 5C, when the output signal falls from the high level to the low level, Similarly, noise that repeats at a high frequency occurs.

  In the first embodiment, such noise can be removed even when output from an input circuit such as an input amplifier.

  In FIGS. 6A to 6D, when high level noise occurs immediately after changing from high level to low level, or when low level noise occurs immediately before changing from high level to low level, When high-level noise occurs immediately before changing from low level to high level, or when low-level noise occurs immediately after changing from low level to high level, the output of the input signal 100 and delay circuit DC1 in FIG. The waveforms of the signal 101, the output signal 102 of the AND circuit AN1, the output signal 103 of the delay circuit DC2, and the output signal 104 are shown.

  When a high-level pulse-like noise having a pulse width t1 is generated immediately after changing from the high level to the low level as in the input signal 100 shown in FIG. 6A, the delay time d1 from the delay circuit DC1. A signal 101 that is delayed by an amount of time is output. The input signal 100 and the signal 101 are input to the AND circuit AN1, and the signal 102 from which noise is removed is output. The signal 102 is delayed by a delay time d2 by the delay circuit DC2, and a signal 103 is output. The signals 102 and 103 are input to the OR circuit OR1, and the signal 104 is output.

  When a low level pulse-like noise having a pulse width t1 occurs just before the change from the high level to the low level as in the input signal 100 shown in FIG. 6B, the delay is delayed from the delay circuit DC1 by the delay time d1. The signal 101 is output. The input signal 100 and the signal 101 are input to the AND circuit AN1, and a signal 102 obtained by adding the noise before delay and the noise after delay is output. However, when the signal 102 is delayed by the delay circuit DC2 by the delay time d2 and the signal 103 is output and is input to the OR circuit OR1 together with the signal 102, the signal 104 from which all noise is removed is output.

  When a high-level pulse-like noise having a pulse width t1 is generated immediately before the low-level to high-level change as in the input signal 100 shown in FIG. 6C, the delay circuit DC1 outputs only the delay time d1. A delayed signal 101 is output. The input signal 100 and the signal 101 are input to the AND circuit AN1, and the signal 102 from which noise is removed is output. The signal 102 is delayed by a delay time d2 by the delay circuit DC2, and a signal 103 is output. The signals 102 and 103 are input to the OR circuit OR1, and the signal 104 is output.

  When the low level pulse-like noise having the pulse width t1 is generated immediately after the change from the high level to the low level as in the input signal 100 shown in FIG. 6D, only the delay time d1 is generated from the delay circuit DC1. A delayed signal 101 is output. The input signal 100 and the signal 101 are input to the AND circuit AN1, and a signal 102 obtained by adding the noise before delay and the noise after delay is output. However, when the signal 102 is delayed by the delay circuit DC2 by the delay time d2 and the signal 103 is output and is input to the OR circuit OR1 together with the signal 102, the signal 104 from which all noise is removed is output.

  In this way, in the case shown in FIGS. 6B and 6C, the first stage delay circuit DC1 and the AND circuit AN1 alone do not remove noise, but are amplified in reverse. Therefore, noise is removed using the delay circuit DC2 and the OR circuit OR1 in the second stage.

Here, the pulse width t1 of the removable noise must be smaller than both the delay time d1 of the delay circuit DC1 and the delay time d2 of the delay circuit DC2, as represented by the following formula (1).
t1 <d1 and t2 <d2 (1)

Furthermore, if the delay times d1 and d2 are the same, the noise cannot be removed, and the delay amount d2 in the second stage is twice the delay amount d1 in the first stage as shown in the following equation (2). It is necessary to have the above size. Thereby, even in the case as shown in FIGS. 6B and 6C, all the noise can be removed by the second-stage delay circuit DC2 and the OR circuit OR1.
2 * d1 ≦ d2 (2)

  A phenomenon in which EMC noise is removed by the noise removal circuit according to the first embodiment will be described with reference to FIG.

  As shown in FIG. 7A, when an input signal 100 in which low level noise having a pulse width d1 is instantaneously input from a high level state is input from the delay circuit DC1 for a delay time d1. Output is delayed. The signals 100 and 101 are input to the AND circuit AN1, and the noise of the signal 100 and the noise of the signal 101 are added to output a signal 102 having a double pulse width d2 (= 2 * d1).

  The signal 102 is delayed by the delay circuit DC12 and output as the signal 103. The signals 102 and 103 are input to the OR circuit OR1, and the signal 104 from which all noise has been removed is output.

  As shown in FIG. 7B, when the input signal 100 in which the high level noise having the pulse width d1 is instantaneously input from the low level state is input from the delay circuit DC1 for the delay time d1. Output is delayed. The signals 100 and 101 are input to the AND circuit AN1, and the signal 102 from which both the noise of the signal 100 and the noise of the signal 101 are removed is output.

  The signal 102 is delayed by the delay circuit DC12 and output as the signal 103. The signals 102 and 103 are input to the OR circuit OR1 and the signal 104 is output.

  As described above, according to the first embodiment, a sufficient noise removal effect including EMC noise can be obtained. As a result, for example, in an input circuit having a crystal oscillation circuit or an input amplifier, it is possible to prevent malfunction of a counter or the like even when external noise, power supply noise, and ground noise are amplified near the operation threshold of the input amplifier. it can.

  In addition, since no Schmitt circuit or CR filter is used for noise removal, it is possible to avoid a situation in which the maximum operating frequency is limited by these frequency characteristics. Further, since a flip-flop that operates in synchronization with the clock is not used, noise can be removed even when the clock is stopped.

  As described above, according to the first embodiment, it is possible to remove noise with stable operation with a simple configuration.

(2) Embodiment 2
A second embodiment of the present invention will be described. In the first embodiment, the noise removal circuit having the configuration shown in FIG. 1 is used by connecting to the next stage of the inverter circuit INV1 included in the input circuit as shown in FIG.

  On the other hand, in the second embodiment, as shown in FIG. 8, two-stage inverters INV11 and INV12 are connected in series as input amplifiers to the input terminal IN, and the input terminal and output of the first-stage inverter INV11 are output. In an input circuit for amplifying a small amplitude in which a resistor R1 is connected in parallel with the terminal, a noise removal circuit NR11 is connected to the output side of the inverter INV12.

  A signal having a small amplitude or a sine wave is input to the input terminal IN and is amplified by the inverter INV11 and the resistor R1.

  Here, if noise is generated near the operation threshold value of the inverter INV11, a signal including the noise is amplified. If the signal is output as it is to a subsequent circuit, a malfunction occurs.

  However, normally, such noise has a pulse-like waveform with a short width, and can be removed by using the noise removal circuit NR11 having the configuration shown in FIG.

  However, parameters of elements such as inverters constituting the delay circuits DC1 and DC2 change due to fluctuations in the manufacturing process and the like, and if the delay amounts d1 and d2 change, the frequency characteristics of the input circuit are affected.

  Therefore, FIG. 9 shows a configuration of a delay circuit capable of reducing the dependency of element characteristics.

  One input terminal of an AND circuit AN11 having two input terminals is connected to the input terminal IN1 of the noise elimination circuit, and a delay circuit DC11 is connected in series between the input terminal IN1 and the other input terminal of the AND circuit AN11. ing. Further, the output terminal of the AND circuit AN11 is connected to one input terminal of the OR circuit OR11 having an input terminal, and the delay circuit DC12 is connected in series between the output terminal of the AND circuit AN11 and the other input terminal of the OR circuit OR11. It is connected to the.

  A delay amount control signal 1 for keeping the delay amount d1 constant is input to the delay circuit DC11, and a delay amount control signal 2 for keeping the delay amount d2 constant is input to the delay circuit DC12. The

  FIG. 10 shows an example of a specific circuit configuration of the delay circuits DC11 and DC12. Delay inverters DINV101 and DINV102 are connected in two stages in series. As a current source, a P-channel MOSFET PT1 is provided between the power supply terminal and the inverter DINV101, an N-channel MOSFET NT1 is provided between the inverter DINV101 and the ground terminal, and a P-channel MOSFET is provided between the power supply terminal and the inverter DINV102. An N-channel MOSFET NT2 is connected between PT2, the inverter DINV102 and the ground terminal.

  The gates of these MOSFETs PT1, NT1, PT2 and NT2 are supplied with gate signals output from delay amount control circuits to which delay amount control signals 1 and 2 are input, respectively. As a result, the gate voltages of the MOSFETs PT1, NT1, PT2, and NT2 are controlled so that the delay amounts d1 and d2 caused by the inverters DINV101 and DINV102 maintain a constant value without fluctuation depending on the manufacturing process, etc. The current value supplied to the inverters DINV101 and DINV102 is controlled.

  Thereby, the dependency of the element characteristics is suppressed, the delay times d1 and d2 are maintained at a constant value, and stable noise removal is possible.

(3) Embodiment 3
A noise removal circuit according to Embodiment 3 of the present invention will be described.

  When the noise removal circuit is used for the input circuit, when the delay amount increases, the pulse having a width smaller than the delay amount is removed as a noise component as described in the first embodiment. Therefore, when a signal having a frequency higher than the delay amount is input, the input signal component may not be output due to the presence of the delay circuit.

  Further, the sensitivity to noise varies depending on the frequency of the input signal. When the frequency is high, for example, as shown in FIG. 4B, when the input signal changes from the high level to the low level or from the low level to the high level, the slope becomes steep, and the operation threshold is crossed. Are less susceptible to noise contained in the input signal. In such a case, it is desirable that the delay amount be small so that a signal component having a high frequency can pass.

  On the other hand, when the frequency is low, for example, as shown in FIG. 5B, the slope of the input signal becomes gradual, and it is easily affected by noise included in the input signal when crossing the operation threshold. In such a case, it is desirable that the delay amount be large in order to enhance the noise reduction effect.

  Thus, the sensitivity to the noise contained in the input signal varies depending on the frequency and amplitude of the input signal.

  Therefore, the third embodiment is characterized in that the delay amount of the noise removal circuit is controlled to an optimum value according to the frequency of the input signal in order to obtain good characteristics in a wide frequency band.

  FIG. 11 shows the configuration of the delay circuit in the noise removal circuit according to the third embodiment. The circuit configuration of the entire noise removal circuit is the same as that shown in FIG. 9 in the second embodiment. In the second embodiment, each delay circuit DC11, DC12 has the configuration shown in FIG. On the other hand, in the third embodiment, each delay circuit DC11, DC12 has the configuration shown in FIG.

  The delay circuits DC21 and DC22 are connected in series, and the output from the delay circuit DC21 and the output from the delay circuit DC2 are input to the selector SL1. In the selector SL1, the delay amount control signal 1 is input, and either the output from the delay circuit DC21 or the output from the delay circuit DC2 is selected and output. As a result, either the signal delayed by the delay amount of only the delay circuit DC21 or the signal delayed by the sum of the delay amounts of the delay circuit DC21 and the delay circuit DC22 is selected and output.

  Further, the signal output from the selector SL1 is input to the delay circuit DC31, and the output from the delay circuit DC31 and the output from the selector SL1 are input to the selector SL2. The delay amount control signal 2 is input to the selector SL2, and either the output from the delay circuit DC31 or the output from the selector SL1 is selected and output.

  As a result, any one of the signal delayed by the delay amount of only the delay circuit DC21, the signal delayed by the delay amount of the delay circuits DC21 and DC22, and the signal delayed by the delay amount of the delay circuits DC21, DC22, and DC31 is selected. It will be selected and output.

  As described above, in the third embodiment, when the frequency of the input signal is high, the delay amount is decreased, and when the frequency is low, the delay amount is increased. It is possible to obtain frequency characteristics.

  Also, when testing the input circuit, if there is a concern that the test time will increase due to the presence of the noise removal circuit, the test time can be shortened by setting the delay amount small. Can be planned.

  In the first to third embodiments, an input circuit including the inverter INV1 is used as shown in FIG. 2, or two-stage inverters INV11 and INV12 and a resistor R1 are used as shown in FIG. Is used, and a noise removal circuit is provided at the subsequent stage.

  However, the present invention is not limited to this, and a configuration in which an operational amplifier OP is used and a noise removal circuit NR21 is provided at the subsequent stage as in the input circuit shown in FIG.

  Alternatively, the comparator COM and the resistor R1 may be used as in the input circuit shown in FIG. 13, and the noise removal circuit NR31 may be arranged at the subsequent stage. Alternatively, as in the input circuit shown in FIG. 14, a subsequent stage such as a crystal oscillator in which a crystal resonator CRO and capacitors C1 and C2 are externally connected to an amplifier provided with inverters INV201 and INV202 and a resistor R11. Alternatively, the noise removal circuit NR41 may be provided. In any configuration, noise included in the input signal can be removed by the noise removal circuits NR21, NR31, and NR41.

  Further, as in the input circuit shown in FIG. 15, when the output is switched between the high level and the low level, the Schmitt circuit SMC and the inverter INV301 each having different thresholds are connected in series, and the noise removal circuit NR51 is then connected. It may be connected.

  By the way, a configuration in which a power source is separated between a plurality of circuits in a semiconductor integrated circuit is increasing. In such a case, the operating current is different between the circuits, and the peak currents are different, thereby causing a shift in the noise level and the timing at which the noise is generated. The first and second embodiments can also be applied to an input / output interface circuit between circuits operating with different operating currents.

  As shown in FIG. 16, a power supply voltage is applied to the circuit A 201 via an inductor 213 parasitic on the wiring connected to the power supply terminal 211, a resistor 224, and a capacitance 212 parasitic on the terminal. Is supplied. A power supply voltage is applied to the circuit B 202 through the inductor 223 parasitic on the wiring connected to the power supply terminal 221 and the capacitor 222 parasitic on the terminal, and the operating current B is supplied. The circuit A 201 is grounded via the ground terminal 231, and the circuit B 202 is grounded via the resistor 233 that is parasitic on the wiring connected to the ground terminal 232.

  Input / output interface circuits 201a and 202a are respectively provided between the circuit A 201 and the circuit B 202, and signals are transferred to each other. In such a state, the difference between the operating current and the peak current becomes conspicuous due to the influence of the inductor, capacitance, and resistance parasitic on the wiring and terminals.

  As a result, the noise level is different between the circuit A 201 and the circuit B 202. In the input inverter 201a included in the input / output interface circuit 201a in the circuit A 201 and in the input inverter 202a included in the input / output interface circuit 202a in the circuit A 202, It is conceivable that different levels of noise occur at different timings.

  Even in such a case, the noise can be effectively removed with a simple configuration by applying the first to third embodiments to the input unit in each circuit.

  The above-described embodiments are merely examples and do not limit the present invention, and various modifications can be made within the technical scope of the present invention. For example, in the first embodiment, the AND circuit AN1 is used as the first-stage logic circuit, and the OR circuit OR1 is used as the second-stage logic circuit. However, the present invention is not limited to this, and an OR circuit may be used in the first stage and an AND circuit may be used in the second stage. Alternatively, a NAND circuit may be used in the first stage and an AND circuit in the second stage. Alternatively, a NAND circuit may be used for the first stage and a NAND circuit for the second stage. Alternatively, a NOR circuit may be used in the first stage and a NOR circuit in the second stage. Further, a NOR circuit can be used in the first stage and an OR circuit can be used in the second stage.

1 is a circuit diagram showing a configuration of a noise removal circuit according to a first embodiment of the present invention. The circuit diagram which showed the structure which provided the same noise removal circuit in the back | latter stage of input amplifier. The circuit diagram which showed the structure of the delay circuit in the noise removal circuit. The wave form diagram which showed the phenomenon which noise generate | occur | produces in an output signal when noise is contained in a digital input signal. The wave form diagram which showed the phenomenon which noise generate | occur | produces in an output signal when noise is contained in a sine wave input signal. FIG. 3 is an explanatory diagram showing a waveform of an output signal when noise is included in the input signal in the noise removal circuit according to the first embodiment. FIG. 3 is an explanatory diagram showing a waveform of an output signal when EMC noise is included in the input signal in the noise removal circuit according to the first embodiment. The circuit diagram which shows the structure of the input circuit using the noise removal circuit by Embodiment 2 of this invention. The circuit diagram which shows the structure of the noise removal circuit by the same Embodiment 2. FIG. The circuit diagram which shows the structure of the delay circuit in the noise removal circuit. The circuit diagram which shows the structure of the delay circuit contained in the noise removal circuit by Embodiment 3 of this invention. The circuit diagram which shows the structure of the input circuit by which the noise removal circuit was provided in the back | latter stage of the operational amplifier. The circuit diagram which shows the structure of the input circuit by which the noise removal circuit was provided in the back | latter stage of the comparator. The circuit diagram which shows the structure of the input circuit by which the noise removal circuit was provided in the back | latter stage of the crystal oscillator. The circuit diagram which shows the structure of the input circuit by which the noise removal circuit was provided in the back | latter stage of the Schmitt circuit. The circuit diagram which shows the structure of the circuit containing the input-output interface circuit between the circuits which operate | move with different operating current.

Explanation of symbols

NR1, NR11 Noise removal circuit DC1, DC11, DC2, DC12, DC21, DC22, DC31 Delay circuit AN1, AN11 AND circuit OR1, OR11 OR circuit SL1, SL2 selector

Claims (5)

A first delay circuit which receives an input signal and delays the first delay amount to output a first delay signal;
A first logic circuit that is provided with the input signal and the first delay signal, performs a first logic operation, and outputs a first signal;
A second delay circuit which is provided with the first signal, delays by a second delay amount and outputs a second delayed signal;
A second logic circuit that is provided with the first signal and the second delay signal, performs a second logic operation, and outputs a second signal;
With
The noise removal circuit according to claim 1, wherein the second delay amount is larger than the first delay amount.   The first delay circuit is supplied with a first delay amount control signal to control the first delay amount, and the second delay circuit is supplied with a second delay amount control signal to receive the first delay amount control signal. 2. The noise removal circuit according to claim 1, wherein a delay amount of 2 is controlled. The first delay circuit includes:
A first inverter that receives the input signal, inverts it, and outputs it;
A second inverter that receives the output from the first inverter and inverts and outputs the first delayed signal;
A first P-channel MOSFET having a source and a drain connected between the first inverter and a power supply terminal; and a first P-channel MOSFET having a drain and a source connected between the first inverter and a ground terminal. An N-channel MOSFET;
A second P-channel MOSFET having a source and a drain connected between the second inverter and a power supply terminal; and a second P-channel MOSFET having a drain and a source connected between the second inverter and a ground terminal. An N-channel MOSFET;
Have
The second delay circuit includes:
A third inverter that receives the first signal and inverts and outputs the third signal;
A fourth inverter that receives the output from the third inverter and inverts and outputs the second delayed signal;
A third P-channel MOSFET having a source and a drain connected between the third inverter and a power supply terminal; and a third P-channel MOSFET having a drain and a source connected between the third inverter and a ground terminal. N-channel MOSFET
A fourth P-channel MOSFET having a source and a drain connected between the fourth inverter and a power supply terminal; and a fourth P-channel MOSFET having a drain and a source connected between the fourth inverter and a ground terminal. An N-channel MOSFET;
Have
The first delay amount control signal is input to the gates of the first and second P-channel MOSFETs and the gates of the first and second N-channel MOSFETs,
3. The second delay amount control signal is input to gates of the third and fourth P-channel MOSFETs and gates of the third and fourth N-channel MOSFETs. The noise elimination circuit described. The first delay circuit includes:
A first delay unit that receives the input signal and delays and outputs the input signal;
A second delay unit that receives and delays the signal delayed by the first delay unit;
A signal delayed by the first delay unit and a signal delayed by the first and second delay units are given, and one of them is selected and output according to the first delay amount control signal. 1 selector,
The second delay circuit includes:
A third delay unit that receives and delays the first signal;
A fourth delay unit that receives and delays the signal delayed by the third delay unit; and
A signal delayed by the third delay unit and a signal delayed by the third and fourth delay units are given, and one of them is selected and output according to the second delay amount control signal. The noise removal circuit according to claim 1, further comprising two selectors.   The first logic circuit is an AND circuit, the second logic circuit is an OR circuit, the first logic circuit is an OR circuit, the second logic circuit is an AND circuit, and the first logic circuit is a NAND circuit. The second logic circuit is an AND circuit; the first logic circuit is a NAND circuit; the second logic circuit is a NAND circuit; the first logic circuit is a NOR circuit; and the second logic circuit is a NOR circuit; The noise removal circuit according to claim 1, wherein the first logic circuit is a NOR circuit and the second logic circuit is any one of an OR circuit.

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