KR20110060732A - Method for manufacturing semiconductor device with buried gate - Google Patents

Method for manufacturing semiconductor device with buried gate Download PDF

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Publication number
KR20110060732A
KR20110060732A KR1020090117413A KR20090117413A KR20110060732A KR 20110060732 A KR20110060732 A KR 20110060732A KR 1020090117413 A KR1020090117413 A KR 1020090117413A KR 20090117413 A KR20090117413 A KR 20090117413A KR 20110060732 A KR20110060732 A KR 20110060732A
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South Korea
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film
trench
semiconductor device
curing
buried gate
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KR1020090117413A
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Korean (ko)
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황선환
장세억
신종한
이승룡
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Abstract

PURPOSE: A method for manufacturing a semiconductor device with a buried gate is provided to prevent the loss of a capping layer by forming a thick curing oxide layer and a thick gate insulation layer on both sides of a capping layer. CONSTITUTION: A trench(26A,26B) is formed by etching a semiconductor substrate(21). A gate insulation layer(27) is formed on the surface of the trench. A conductive layer is formed on the gate insulation layer to fill the trench. A buried gate(28A) is formed by filling the trench by successively planarizing and etching back the conductive layer. A curing oxide layer(29) is formed by a plasma oxidation process.

Description

매립게이트를 구비한 반도체장치 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH BURIED GATE}Method for manufacturing semiconductor device with buried gate {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH BURIED GATE}

본 발명은 반도체장치 제조 방법에 관한 것으로서, 특히 매립게이트를 구비한 반도체장치 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a buried gate.

60nm 이하의 DRAM 공정에서 셀에서의 트랜지스터의 집적도를 증가시키고 공정 단순화 및 누설 특성과 같은 장치 특성을 향상시키기 위해 매립게이트(Buried Gate)를 형성하는 것이 필수적이다. In DRAM processes below 60nm, it is necessary to form buried gates to increase the integration of transistors in the cell and to improve device characteristics such as process simplification and leakage characteristics.

매립게이트 제조 방법은 트렌치(Trench)를 형성하고 트렌치 내부에 게이트를 매립하는 방식으로 진행하므로써 비트라인과 게이트간의 간섭을 최소화하고 적층되는 막(Film Stack)의 수를 감소시킬 수 있으며, 또한 전체 셀의 캐패시턴스(Capacitance)를 감소시켜 리프레시(Refresh) 특성을 향상시킬 수 있는 장점이 있다. The buried gate manufacturing method proceeds by forming a trench and filling a gate in the trench, thereby minimizing interference between the bit line and the gate, and reducing the number of film stacks. There is an advantage to improve the refresh characteristics by reducing the capacitance (Capacitance) of.

도 1a 내지 도 1c는 종래기술에 따른 매립게이트를 구비한 반도체장치 제조 방법을 도시한 도면이다.1A to 1C illustrate a method of manufacturing a semiconductor device having a buried gate according to the related art.

도 1a에 도시된 바와 같이, 반도체기판(11) 상에 패드산화막(12)과 패드질화막(13)을 한 후 STI(Shallow Trench Isolation) 공정을 통해 소자분리트렌치(14)에 갭필되는 소자분리막(15)을 형성한다. 소자분리막(15)에 의해 활성영역(100)이 정의된다.As shown in FIG. 1A, after the pad oxide layer 12 and the pad nitride layer 13 are formed on the semiconductor substrate 11, a device isolation layer gap-filled in the device isolation trench 14 through a shallow trench isolation (STI) process ( 15). The active region 100 is defined by the device isolation layer 15.

이어서, 매립게이트 마스크 및 식각을 진행하여 활성영역(100)과 소자분리막(15)에 트렌치(16A, 16B)를 형성한다.Subsequently, the trench gate mask and the etching process are performed to form trenches 16A and 16B in the active region 100 and the device isolation layer 15.

이어서, 트렌치(16A, 16B) 표면 상에 게이트절연막(17)을 형성한 후, 트렌치(16A, 16B)를 일부 매립하는 매립게이트(18)를 형성한다. 매립게이트(18)는 트렌치(16A, 16B)를 갭필하도록 게이트도전막을 증착한 후 화학적기계적연마(CMP) 및 에치백을 순차적으로 진행하여 형성한다.Subsequently, after the gate insulating film 17 is formed on the surfaces of the trenches 16A and 16B, the buried gates 18 which partially fill the trenches 16A and 16B are formed. The buried gate 18 is formed by depositing a gate conductive film to gap-fill trenches 16A and 16B, and then sequentially performing chemical mechanical polishing (CMP) and etch back.

이어서, 에치백에 따른 손상을 큐어링(Curing)하기 위해 선택산화(Selective oxidation)을 실시한다. 이에 따라 매립게이트(18)의 표면을 제외한 나머지 표면에 큐어링산화막(Curing oxide, 19)이 형성된다. Then, selective oxidation is performed to cure the damage due to the etch back. Accordingly, a curing oxide 19 is formed on the remaining surfaces except for the buried gate 18.

상술한 종래기술은 매립게이트(18) 형성 후에, 에치백에 따른 손상(damage)을 큐어링시키기 위해 선택산화를 진행하고 있다. 선택산화는 매립게이트(18)의 산화를 방지하는 산화방식으로서 수소가 다량 함유된(H2 rich, 이를 '수소부화'라고 약칭함) 산화분위기에서 진행한다.In the above-described prior art, after the buried gate 18 is formed, selective oxidation is performed to cure the damage caused by the etch back. Selective oxidation is an oxidation method that prevents oxidation of the buried gate 18 and proceeds in an oxidation atmosphere containing a large amount of hydrogen (H 2 rich, abbreviated as 'hydrogen enrichment').

그러나, 종래기술은 수소가 다량 함유된 산화분위기에서 선택산화를 실시하 기 때문에 수소효과(Hydrogen effect)에 의해 리프레시(Refresh)의 열화가 발생되는 문제가 있다.However, in the prior art, since selective oxidation is performed in an oxidizing atmosphere containing a large amount of hydrogen, there is a problem in that deterioration of refresh occurs due to a hydrogen effect.

수소효과에 의한 리프레시 열화를 방지하기 위해 선택산화를 실시하지 않을 수 있다.Selective oxidation may not be performed to prevent refresh degradation due to the hydrogen effect.

도 1b에 도시된 바와 같이, 매립게이트(18) 상부를 캡핑하는 캡핑막(20)을 형성한 후, 패드질화막(13)의 표면이 드러날때까지 평탄화한다.As shown in FIG. 1B, the capping film 20 capping the upper portion of the buried gate 18 is formed, and then planarized until the surface of the pad nitride film 13 is exposed.

도 1c에 도시된 바와 같이, 패드질화막(13)을 스트립한다.As shown in FIG. 1C, the pad nitride film 13 is stripped.

그러나, 선택산화를 실시하지 않는 경우에는, 매립게이트(18)의 에치백손상을 큐어링할 수 없을뿐만 아니라 패드질화막(13) 스트립시 캡핑막(20)의 손실(Loss, 도면부호 'L' 참조)이 발생하는 문제가 있다. 이는 캡핑막(20) 측벽쪽에 잔류하는 산화막(게이트절연막)의 두께가 얇기 때문이다. 선택산화를 진행한 경우에는 캡핑막(20) 측벽쪽에 산화막(게이트절연막+큐어링산화막)을 두껍게 형성하므로써 캡핑막(20)의 손실을 보호할 수 있으나, 선택산화를 진행하지 않으면 패드질화막(12) 스트립시 캡핑막(20)의 손실이 발생한다.However, in the case where selective oxidation is not performed, not only the etchback damage of the buried gate 18 can be cured, but also the loss of the capping film 20 when the pad nitride film 13 is stripped (Ls). There is a problem that occurs. This is because the thickness of the oxide film (gate insulating film) remaining on the sidewall of the capping film 20 is thin. In the case of selective oxidation, the loss of the capping film 20 can be protected by forming a thick oxide film (gate insulating film + curing oxide film) on the sidewall of the capping film 20. However, if the selective oxidation is not performed, the pad nitride film 12 ) The loss of the capping film 20 occurs during stripping.

캡핑막(20)의 손실을 최소화하기 위해 게이트절연막(17)의 두께를 증가시킬 수도 있으나, 게이트절연막(17)의 두께가 증가하면 매립게이트(18)로 사용되는 도전막 갭필시 갭필마진(Gapfill margin)이 부족해지는 문제가 있다.In order to minimize the loss of the capping layer 20, the thickness of the gate insulating layer 17 may be increased. However, when the thickness of the gate insulating layer 17 is increased, a gap fill margin may be used when gap filling the conductive layer used as the buried gate 18. There is a problem of lack of margin.

본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위해 제안된 것으로서, 매립게이트의 에치백 손상(Etchback damage)을 큐어링하면서 리프레시 열화 및 캡핑막 손실을 방지할 수 있는 반도체장치 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems according to the prior art, and provides a method of manufacturing a semiconductor device capable of preventing refresh degradation and capping film loss while curing etchback damage of a buried gate. The purpose is.

상기 목적을 달성하기 위한 본 발명의 반도체장치 제조 방법은 반도체기판을 식각하여 트렌치를 형성하는 단계; 상기 트렌치의 표면 상에 게이트절연막을 형성하는 단계; 상기 트렌치를 매립하도록 상기 게이트절연막 상에 도전막을 형성하는 단계; 상기 도전막을 순차적으로 평탄화 및 에치백하여 상기 트렌치를 일부 매립하는 매립게이트를 형성하는 단계; 및 플라즈마산화를 이용한 큐어링을 실시하는 단계를 포함하는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a trench by etching the semiconductor substrate; Forming a gate insulating film on a surface of the trench; Forming a conductive film on the gate insulating film to fill the trench; Sequentially planarizing and etching back the conductive layer to form a buried gate partially filling the trench; And performing curing using plasma oxidation.

바람직하게, 상기 플라즈마산화는 산소함유가스를 이용하여 10∼100℃의 온도에서 진행하며, 상기 플라즈마산화에 의해 5∼500Å 두께의 큐어링산화막이 형성된다.Preferably, the plasma oxidation proceeds at a temperature of 10 to 100 ° C. using an oxygen-containing gas, and a curing oxide film having a thickness of 5 to 500 kPa is formed by the plasma oxidation.

상술한 본 발명은 에치백에 의한 손상을 제거하기 위한 큐어링을 수소가 없 는 산화분위기의 플라즈마산화를 이용하여 실시하므로써 수소효과에 의한 리프레시 열화를 방지할 수 있는 효과가 있다.The present invention described above has the effect of preventing the deterioration of the refresh by the hydrogen effect by performing the curing to remove the damage caused by the etch back using plasma oxidation of the oxidation atmosphere without hydrogen.

또한, 본 발명은 플라즈마산화가 저온에서 실시되므로 매립게이트의 이상산화를 방지할 수 있는 효과가 있다.In addition, the present invention has an effect that can prevent the abnormal oxidation of the buried gate because plasma oxidation is carried out at a low temperature.

또한, 본 발명은 캡핑막의 양쪽 측벽에 큐어링산화막과 게이트절연막의 두꺼운 산화막을 형성하므로써 후속 패드질화막 스트립시 캡핑막이 손실되는 것을 방지할 수 있는 효과가 있다.In addition, the present invention has an effect of preventing the capping film from being lost during the subsequent stripping of the pad nitride film by forming a thick oxide film of a curing oxide film and a gate insulating film on both sidewalls of the capping film.

또한, 본 발명은 게이트절연막의 두께를 증가시키지 않아도 되므로 매립게이트의 갭필마진을 확보할 수 있는 효과가 있다.In addition, the present invention does not need to increase the thickness of the gate insulating film has the effect of ensuring the gap fill margin of the buried gate.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체장치 제조 방법을 도시한 공정 단면도이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체기판(21) 상에 패드산화막(22)과 패드질화막(23)을 적층한 후 STI 공정을 진행하여 소자분리트렌치(24) 내부를 갭필하는 소자분리막(25)을 형성한다. 소자분리막(25)은 스핀온절연막(Spin On Dielectric)을 이용하여 형성할 수 있고, 소자분리막(25)에 의해 활성영역(200)이 정의된다.As shown in FIG. 2A, after the pad oxide layer 22 and the pad nitride layer 23 are stacked on the semiconductor substrate 21, an STI process is performed to gap fill the inside of the device isolation trench 24. To form. The device isolation layer 25 may be formed using a spin on dielectric layer, and the active region 200 is defined by the device isolation layer 25.

도 2b에 도시된 바와 같이, 매립게이트 공정을 위한 마스크 및 식각 공정을 진행한다. 예컨대, 감광막패턴(도시 생략)을 이용하여 패드질화막(23)과 패드산화막(22)을 식각하여 패드질화막패턴(23A)과 패드산화막패턴(22A)을 형성한다. 이후 패드질화막패턴(23A)을 식각배리어로 하여 게이트예정영역의 반도체기판(21)을 식각한다. 이에 따라, 일정 깊이의 트렌치(26A, 26B)가 형성되며, 트렌치(26A, 26B)는 활성영역(200)과 소자분리막(25)을 동시에 식각하여 형성될 수 있다. 트렌치(26A, 26B) 형성후에 소자분리막은 도면부호 '25A'가 된다.As shown in FIG. 2B, a mask and an etching process for a buried gate process are performed. For example, the pad nitride layer 23 and the pad oxide layer 22 are etched using a photoresist pattern (not shown) to form the pad nitride layer pattern 23A and the pad oxide layer pattern 22A. Thereafter, the semiconductor substrate 21 of the gate region is etched using the pad nitride film pattern 23A as an etching barrier. Accordingly, trenches 26A and 26B having a predetermined depth are formed, and the trenches 26A and 26B may be formed by simultaneously etching the active region 200 and the device isolation layer 25. After the formation of the trenches 26A and 26B, the device isolation film is designated as '25A'.

도 2c에 도시된 바와 같이, 트렌치(26A, 26B)의 표면 상에 게이트절연막(27)을 형성한다.As shown in Fig. 2C, a gate insulating film 27 is formed on the surfaces of the trenches 26A and 26B.

이어서, 게이트절연막(27) 상에 트렌치(26A, 26B)를 갭필하도록 전면에 게이트도전막(28)을 증착한 후 화학적기계적연마(Chemical Mechanical Polishing; CMP)를 이용하여 평탄화한다. 게이트도전막(28)은 티타늄질화막(TiN), 탄탈륨질화막(TaN), 텅스텐막(W) 등과 같은 금속막을 포함한다. 예컨대, 일함수가 큰 티타늄질화막(또는 탄탈륨질화막)을 컨포멀(Conformal)하게 얇게 증착한 후 저항을 낮추기 위한 텅스텐막을 갭필하여 형성할 수 있다. 또한, 티타늄질화막과 탄탈륨질화막을 적층하여 형성하거나, 또는 티타늄질화막, 탄탈륨질화막 및 텅스텐막을 차례로 적층하여 형성할 수도 있다.Subsequently, the gate conductive film 28 is deposited on the entire surface of the gate insulating film 27 so as to gap fill the trenches 26A and 26B, and then planarized using chemical mechanical polishing (CMP). The gate conductive film 28 includes a metal film such as a titanium nitride film TiN, a tantalum nitride film TaN, a tungsten film W, or the like. For example, a titanium nitride film (or tantalum nitride film) having a large work function may be formed by conformally thinly depositing a tungsten film for reducing resistance. In addition, the titanium nitride film and the tantalum nitride film may be formed by laminating, or the titanium nitride film, the tantalum nitride film, and the tungsten film may be sequentially formed.

도 2d에 도시된 바와 같이, 에치백을 진행하여 트렌치(26A, 26B)를 일부 매립하는 매립게이트(28A)를 형성한다. 매립게이트(28A)의 표면은 반도체기판(21)의 표면보다 낮은 높이를 가질 수 있다.As shown in FIG. 2D, an etch back is performed to form a buried gate 28A which partially fills the trenches 26A and 26B. The buried gate 28A may have a lower height than the surface of the semiconductor substrate 21.

도 2e에 도시된 바와 같이, 매립게이트(28A)를 형성하는 에치백에 의한 손상을 제거하기 위해 큐어링을 진행한다. 이때, 큐어링은 수소가 없는 산화분위기에서 진행한다. 바람직하게, 큐어링은 수소가 없는 산화분위기에서 플라즈마산화(Plasma oxidation) 공정을 적용한다. 이와 같이, 수소가 없는 산화분위기에서 플라즈마산화공정을 실시하여 큐어링하면 수소효과에 의한 리프레시 열화가 발생하지 않는다. 아울러, 플라즈마산화 공정에 의해 형성되는 큐어링산화막(Curing oxide, 29)은 후속 패드질화막 스트립시 캡핑막의 손실을 방지하는 보호막 역할도 수행한다. 즉, 큐어링산화막(29)과 게이트절연막(27)에 의해 캡핑막 측벽쪽에서 산화막의 두께가 증가하므로 패드질화막 스트립시 캡핑막이 손실되는 것을 방지한다.As shown in Fig. 2E, curing is performed to eliminate damage by the etch back forming the buried gate 28A. At this time, curing is performed in an oxidation atmosphere without hydrogen. Preferably, curing is a plasma oxidation process in a hydrogen-free oxidation atmosphere. As such, when the plasma oxidation process is performed in a hydrogen-free oxidation atmosphere and cured, refreshing degradation due to the hydrogen effect does not occur. In addition, the curing oxide layer 29 formed by the plasma oxidation process also serves as a protective layer to prevent loss of the capping layer during subsequent stripping of the pad nitride layer. That is, since the thickness of the oxide film is increased on the sidewall of the capping film by the curing oxide film 29 and the gate insulating film 27, the capping film is prevented from being lost when the pad nitride film is stripped.

바람직하게, 플라즈마산화 공정은 10∼100℃의 온도에서 산소함유가스를 이용하여 진행한다. 여기서, 산소함유가스는 산소라디칼, O2 또는 O3를 포함한다. 산소함유가스에 Ar, He, N2 등의 비활성가스를 더 추가할 수도 있다. 플라즈마산화 공정시 고주파파워(Radio Frequency Power)는 10∼100000W의 범위로 한다. Preferably, the plasma oxidation process is performed using an oxygen-containing gas at a temperature of 10 to 100 ℃. Here, the oxygen-containing gas includes oxygen radicals, O 2 or O 3 . An inert gas such as Ar, He, or N 2 may be further added to the oxygen-containing gas. The radio frequency power in the plasma oxidation process is in the range of 10 to 100,000 W.

플라즈마산화공정에 의해 형성되는 큐어링산화막(29)은 5∼500Å의 두께를 갖는다.The curing oxide film 29 formed by the plasma oxidation process has a thickness of 5 to 500 kPa.

한편, 플라즈마산화공정이 실온(Room temperature), 즉 10∼100℃의 저온에서 진행되기 때문에 매립게이트(28A)의 이상산화가 발생하지 않는다.On the other hand, since the plasma oxidation process proceeds at room temperature, that is, at a low temperature of 10 to 100 ° C., abnormal oxidation of the buried gate 28A does not occur.

도 2f에 도시된 바와 같이, 매립게이트(28A) 상부를 캡핑하는 캡핑막(30)을 형성한 후, 패드질화막패턴(23A)의 표면이 드러날때까지 평탄화한다. 이때, 평탄화 는 화학적기계적연마(CMP)를 이용하며, 패드질화막패턴(23A)에서 연마가 정지할때까지 진행한다. 이에 따라, 매립게이트(28A) 상부는 캡핑막(30)이 캡핑하게 되고, 캡핑막(30)과 패드질화막패턴(23A) 사이에는 게이트절연막(27)과 큐어링산화막(29A)의 두꺼운 산화막이 형성된다. 캡핑막(30)은 산화막을 포함한다.As shown in FIG. 2F, the capping film 30 capping the upper portion of the buried gate 28A is formed, and then planarized until the surface of the pad nitride film pattern 23A is exposed. At this time, the planarization uses chemical mechanical polishing (CMP), and progresses until polishing stops at the pad nitride film pattern 23A. Accordingly, the capping film 30 is capped on the buried gate 28A, and a thick oxide film of the gate insulating film 27 and the curing oxide film 29A is disposed between the capping film 30 and the pad nitride film pattern 23A. Is formed. The capping film 30 includes an oxide film.

도 2g에 도시된 바와 같이, 패드질화막패턴(23A)을 제거하는 스트립(Strip)을 진행한다. 이때, 스트립은 인산(H3PO4)을 이용하여 진행할 수 있다.As shown in FIG. 2G, a strip for removing the pad nitride film pattern 23A is performed. At this time, the strip may proceed using phosphoric acid (H 3 PO 4 ).

위와 같은 스트립 진행시 캡핑막(30)의 양쪽 측벽은 게이트절연막(27)과 큐어링산화막(29A)의 두꺼운 산화막이 보호하고 있기 때문에 캡핑막(30)의 손실이 발생하지 않는다.When the strip proceeds as described above, both sidewalls of the capping film 30 are protected by the thick oxide film of the gate insulating film 27 and the curing oxide film 29A, so that the capping film 30 is not lost.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

도 1a 내지 도 1c는 종래기술에 따른 매립게이트를 구비한 반도체장치 제조 방법을 도시한 도면.1A to 1C illustrate a method of manufacturing a semiconductor device having a buried gate according to the prior art.

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체장치 제조 방법을 도시한 공정 단면도.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체기판 22A : 패드산화막패턴21: semiconductor substrate 22A: pad oxide film pattern

23A : 패드질화막패턴 25, 25A : 소자분리막23A: pad nitride film pattern 25, 25A: device isolation film

26A, 26B : 트렌치 27 : 게이트절연막26A, 26B: trench 27: gate insulating film

28A : 매립게이트 29, 29A : 큐어링산화막28A: buried gate 29, 29A: curing oxide film

30 : 캡핑막30: capping film

Claims (7)

반도체기판을 식각하여 트렌치를 형성하는 단계;Etching the semiconductor substrate to form a trench; 상기 트렌치의 표면 상에 게이트절연막을 형성하는 단계;Forming a gate insulating film on a surface of the trench; 상기 트렌치를 매립하도록 상기 게이트절연막 상에 도전막을 형성하는 단계;Forming a conductive film on the gate insulating film to fill the trench; 상기 도전막을 순차적으로 평탄화 및 에치백하여 상기 트렌치를 일부 매립하는 매립게이트를 형성하는 단계; 및Sequentially planarizing and etching back the conductive layer to form a buried gate partially filling the trench; And 플라즈마산화를 이용한 큐어링을 실시하는 단계Curing by Plasma Oxidation 를 포함하는 반도체장치 제조 방법.A semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 트렌치를 형성하는 단계는,Forming the trench, 패드질화막패턴을 식각배리어로 이용하여 진행하는 반도체장치 제조 방법.A semiconductor device manufacturing method which proceeds using a pad nitride film pattern as an etching barrier. 제2항에 있어서,The method of claim 2, 상기 큐어링을 실시하는 단계 이후에,After performing the curing, 상기 매립게이트 상부를 캡핑하는 캡핑막을 형성하는 단계; 및Forming a capping film capping an upper portion of the buried gate; And 상기 패드질화막패턴을 스트립하는 단계Stripping the pad nitride layer pattern 를 더 포함하는 반도체장치 제조 방법.A semiconductor device manufacturing method further comprising. 제3항에 있어서,The method of claim 3, wherein 상기 캡핑막은 산화막을 포함하는 반도체장치 제조 방법.And the capping film comprises an oxide film. 제1항에 있어서,The method of claim 1, 상기 큐어링을 실시하는 단계에서,In the step of performing the curing, 상기 플라즈마산화는 산소함유가스를 이용하여 진행하는 반도체장치 제조 방법.And the plasma oxidation is performed using an oxygen-containing gas. 제5항에 있어서,The method of claim 5, 상기 플라즈마산화는,The plasma oxidation, 10∼100℃의 온도에서 진행하는 반도체장치 제조 방법.The semiconductor device manufacturing method which advances at the temperature of 10-100 degreeC. 제1항에 있어서,The method of claim 1, 상기 큐어링을 실시하는 단계에서,In the step of performing the curing, 상기 플라즈마산화에 의해 5∼500Å 두께의 큐어링산화막이 형성되는 반도체장치 제조 방법.A method of manufacturing a semiconductor device in which a curing oxide film having a thickness of 5 to 500 Å is formed by the plasma oxidation.
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Publication number Priority date Publication date Assignee Title
US11133315B2 (en) 2018-10-02 2021-09-28 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11133315B2 (en) 2018-10-02 2021-09-28 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

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