KR20110003040A - Method for forming self aligned contact in semiconductor device with buried gate - Google Patents

Abstract

PURPOSE: A semiconductor device self aligning contact forming method is provided to minimize the substrate loss and increase the open margin of a contact area by using the poly silicon layer as the hard mask which is used in the buried gate forming process. CONSTITUTION: A first trench is formed by etching a substrate(31) with the hard mask as the etching barrier. An element isolation film(35) which fills the first trench is formed. A second trench is formed by etching the substrate and the element isolation film using the hard mask layer as the etching barrier. A buried gate(38A) filling the second trench is formed.

Description

METHOD FOR FORMING SELF ALIGNED CONTACT IN SEMICONDUCTOR DEVICE WITH BURIED GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a self-aligned contact of a semiconductor device having a buried gate.

In DRAM processes below 60nm, it is necessary to form buried gates to increase the integration of transistors in the cell and to improve device characteristics such as process simplification and leakage characteristics.

The buried gate manufacturing method proceeds by forming a trench and filling a gate in the trench, thereby minimizing interference between the bit line and the gate, and reducing the number of film stacks. There is an advantage to improve the refresh characteristics by reducing the capacitance (Capacitance) of.

1A to 1E illustrate a method of manufacturing a semiconductor device having a buried gate according to the related art.

As shown in FIG. 1A, the device isolation layer 12 is formed on the substrate 11 in which the cell region and the peripheral region are defined.

Subsequently, the trench 14 is formed by etching the substrate of the cell region using the hard mask layer 13, and then the first gate insulating layer 15 is formed. Subsequently, a buried gate 16 may be formed on the first gate insulating layer 15 to partially fill the trench.

As shown in FIG. 1B, after removing the hard mask layer 13, a sealing layer 17 is formed to seal the upper portion of the buried gate 16.

Subsequently, a peripheral area open process is performed such that the sealing film 17 remains only in the cell area.

Subsequently, the second gate insulating layer 18 is formed in the peripheral region through a gate oxidation process.

As shown in FIG. 1C, after the gate conductive layer 19 is formed on the second gate insulating layer 18, a bit line contact hole 20 process for bit line contact is performed in the cell region.

As shown in FIG. 1D, a metal film is deposited on the entire surface of the substrate to fill the bit line contact hole, and then a hard mask film is formed on the metal film.

Subsequently, gate etching is performed. The gate etching is a process of etching the hard mask film, the metal film and the gate conductive film. Accordingly, the gate conductive film 19, the gate metal film 21B and the gate hard mask film are formed on the second gate insulating film 18 in the peripheral region. A gate (hereinafter, abbreviated as “fergate”) PG for transistors in the peripheral region stacked in the order of 22B is completed. When the ferrite PG is formed as described above, a bit line BL is formed in the cell region in the order of the bit line wiring layer 21A and the bit line hard mask layer 22A, which serve as bit line contacts.

As shown in FIG. 1E, an interlayer insulating film 23 is formed on the entire surface. Subsequently, a contact process for etching the interlayer insulating layer 23 to form a storage node contact 24 in the cell region is performed.

In the above-described conventional technique, after the buried gate 16 is formed in the cell region, a sealing process is performed to prevent oxidation of the buried gate 16 using the sealing film 17 in the cell region. Then, gate oxide and gate conductive film deposition processes are performed to open only the peripheral region to form transistors in the peripheral region. Then, the cell region is opened again to perform a contact etching process for forming a bit line contact hole.

However, in the related art, although the sealing film 17 seals the cell region, the buried gate 16 is oxidized by an oxygen source when the gate oxidation process for forming the second gate insulating film 18 is performed in the peripheral region. There is a limit to the prevention (reference 'A' in Fig. 1b).

In addition, since the storage node contact 24 is formed after the bit line BL is formed in the cell region, it is difficult to secure a contact open area for forming the storage node contact 24. In addition, there is a problem in that the interface open area between the storage node contact and the substrate increases due to a narrow contact open area.

In addition, the prior art is a GIDL (Gate Induced Drain) between each contact and the buried gate due to the loss of the substrate (see reference numeral 'B' in Figure 1c) due to the over-etch during the storage node contact or bit line contact process Leakage is increased and the possibility of self-aligned contact fail is increased.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the problems according to the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of preventing oxidation of a buried gate according to a subsequent process.

In addition, another object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the contact resistance by increasing the open area of the contact region after the buried gate.

In addition, another object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the loss of the substrate due to the contact etching for forming the contact region.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a hard mask film on a substrate; Etching the substrate using the hard mask layer as an etch barrier to form a first trench; Forming an isolation layer gap-filling the first trenches; Forming a second trench by etching the substrate and the device isolation layer using the hard mask layer as an etch barrier; Forming a buried gate partially filling the second trench; Forming a sealing film gap-filling an upper portion of the buried gate; Removing the hard mask layer to open a contact region; And forming a landing plug to fill the contact region.

In addition, the method of manufacturing a semiconductor device of the present invention comprises the steps of forming an etching barrier film in which a pad oxide film and a hard mask film are stacked on a substrate; Forming a first trench by etching the substrate using the etching barrier layer; Stacking a sidewall oxide layer and a liner nitride layer on sidewalls of the first trenches; Forming an isolation layer gap-filling the first trenches; Etching the substrate and the isolation layer to form a second trench; Forming a buried gate partially filling the second trench; Forming a sealing film gap-filling an upper portion of the buried gate; Opening the contact region by removing the etch barrier layer and the sidewall oxide layer; And forming a landing plug to fill the contact region.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of: laminating a gate insulating film and a gate conductive film on a substrate in which a cell region and a peripheral region are defined; Etching the substrate using the gate conductive layer as an etch barrier to form a first trench; Forming an isolation layer gap-filling the first trenches; Etching the substrate and the device isolation layer using the gate conductive layer as a hard mask to form a second trench in the cell region; Forming a buried gate partially filling the second trench; Forming a sealing film gap-filling an upper portion of the buried gate; Removing the gate conductive film and the gate insulating film of the cell region to open a contact region; And forming a landing plug to fill the contact region.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of: laminating a pad oxide film and a hard mask film on a substrate in which a cell region and a peripheral region are defined; Forming a first trench by etching the substrate using the hard mask layer as an etch barrier; Forming an isolation layer for gap filling the first trench; Etching the substrate and the device isolation layer using the hard mask layer as an etch barrier to form a second trench in the cell region; Forming a buried gate partially filling the second trench; Forming a sealing film gap-filling an upper portion of the buried gate; Removing the hard mask layer and the pad oxide layer in the peripheral region; Stacking a gate insulating film and a gate conductive film on the substrate in the peripheral region; Opening the contact region by removing the hard mask layer and the pad oxide layer in the cell region; And forming a landing plug to fill the contact region.

The present invention described above can minimize the loss of the substrate in a subsequent process by applying a polysilicon film as a hard mask used in the device isolation process and the buried gate forming process and removing the buried gate after forming it, and also improving contact resistance. And increase the open margin of the contact area.

In addition, since the process of forming the gate conductive film in the peripheral region can be moved before the device isolation process, the process of forming the gate conductive film in the peripheral region can be eliminated to simplify the process. There is an effect that can prevent the oxidation of the buried gate.

In addition, the present invention has the effect that both the cell bit line and the gate of the peripheral region can be efficiently formed simultaneously in the peripheral region gate pre-structure or the peripheral region gate post-structure for forming the gate conductive film of the peripheral region first.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention. The first embodiment is a transposition structure in which the gate conductive film of the peripheral region is first formed.

As shown in FIG. 2A, a pad oxide film 32 and a hard mask polysilicon film 33 are stacked on a substrate 31 having a cell region and a peripheral region defined therein. Here, the pad oxide film 32 is used as a pad film in the cell region and as a gate oxide film in the peripheral region. The hard mask polysilicon film 33 is used as a hard mask film in the cell region and as a gate conductive film in the peripheral region. Impurities may be ion implanted into the hard mask polysilicon layer 33 to be used as the gate conductive layer in the peripheral region, and may be formed to have a thickness of 600 to 1500 Å. In the case of using the gate conductive film as a gate conductive film in the peripheral region, a doping process of an impurity for forming a channel region may be performed in advance in the peripheral region before the pad oxide film 32 is formed.

In another embodiment, a hard mask nitride film may be further formed on the hard mask polysilicon film 33. The hard mask polysilicon film 33 formed in the peripheral region is used as the gate conductive film without being removed in a subsequent process. Therefore, in order to minimize damage to the hard mask polysilicon film 33, a hard mask nitride film is further formed and applied as a hard mask for forming a subsequent device isolation film. At this time, the hard mask nitride film is completely removed in a subsequent separation process of the buried gate, and is formed to a thickness of 300 ~ 800 Å in consideration of the degree of removal.

As shown in FIGS. 2B and 2C, a shallow trench isolation (STI) process is performed. That is, after forming the first trench 34 using the hard mask polysilicon film 33 as a hard mask, the insulating film is gap-filled to form the device isolation film 35. The device isolation layer 35 may be formed by a single gapfill process using a flowable oxide, and a combination of the flowable oxide film and the deposited oxide film may also be used. The flowable oxide film may include SOD (Spin On Dielectric), and the deposition oxide film may include a high density plasma oxide film (HDP Oxide).

Before forming the device isolation layer 35, the sidewall oxide layer 35A may be formed through a wall oxidation process, and a liner nitride 35B may be formed on the sidewall oxide layer 35A.

As shown in FIG. 2D, the second trench 36 is formed in the cell region through a buried gate mask (not shown) and etching. That is, after the hard mask polysilicon layer 33 and the pad oxide layer 32 are etched, the second trench 36 is formed by sequentially etching the substrate 31 and the device isolation layer 35. The hard mask polysilicon film 33 is used as a hard mask at the time of forming the second trench 36.

As shown in FIG. 2E, a gate insulating film 37 is formed on the surface of the second trench 36. The gate insulating film 37 is a gate insulating film for transistors in the cell region, and will be abbreviated as "cell gate insulating film 37" for convenience of description below.

Subsequently, a metal film 38 is deposited on the entire surface of the cell gate insulating film 37 so as to gap-fill the second trench 36. The metal film 38 includes a titanium nitride film TiN, a tantalum nitride film TaN, a tungsten film W, or the like. For example, in order to lower the resistance, the titanium nitride film (or tantalum nitride film) may be formed by conformally thinly depositing a tungsten film. In addition, the titanium nitride film and the tantalum nitride film may be formed by laminating, or the titanium nitride film, the tantalum nitride film, and the tungsten film may be sequentially formed. At this time, the titanium nitride film is preferably formed to a thickness of 20 to 80 kPa.

Subsequently, the metal film 38 is planarized using a chemical mechanical polishing (CMP) method to expose the surface of the hard mask polysilicon film 33, and then the second trench 36 is continuously etched back. A portion of the buried gate 38A is buried. The surface of the buried gate 38A may have a height lower than that of the substrate 31.

As shown in FIG. 2F, a sealing film 39 for sealing the upper portion of the buried gate 38A is formed. Here, the sealing film 39 may be selected from an oxide film, a nitride film or a stacked structure of the nitride film and the oxide film. For example, after sealing the sealing nitride film 39A thinly, the sealing oxide film 39B such as SOD can be formed by gap filling. Preferably, since the pad oxide film serving as the gate insulating film is formed in the peripheral region, the sealing nitride film may be omitted since the risk of oxidation is small, thereby simplifying the process.

Next, the sealing film 39 is separated so that the surface of the hard mask polysilicon film 33 is exposed. The separation process of the sealing film 39 may use CMP or etch back. Preferably, CMP is advantageous in terms of wafer uniformity or prevention of loss of underlying layers.

As shown in FIG. 2G, after the cell region is opened using a mask (not shown), the hard mask polysilicon layer 33 and the pad oxide layer 32 are removed. As a result, the pad oxide film 32A used as the gate insulating film and the hard mask polysilicon film 33A used as the gate conductive film remain only in the peripheral region. Hereinafter, the pad oxide film is referred to as a 'ferrigate insulating film 32A', and the hard mask polysilicon film 33A is referred to as a 'gate polysilicon film 33A'. In the cell region, the contact region 40 in which the landing plug is to be formed between the sealing films 39 is opened.

The process of removing the hard mask polysilicon film can be performed either by a wet process using a mixed solution of nitric acid and fluoric acid or by dry etching using a plasma. The pad oxide film can be removed through a wet process. When the pad oxide film is removed, a portion of the sidewall oxide film 35A is also removed. The wet etching is no longer performed by the liner nitride film 35B, so that only a predetermined amount of the area of the contact region 40 opened can be controlled. The landing plug is embedded in the contact region 40 in a subsequent process. If the wet etching stops at the liner nitride film 35B, the contact region 40 is widened to increase the possibility of bridging between neighboring contact regions. Therefore, a process capable of controlling this can be ensured with the liner nitride film 35B.

When the pad oxide film is removed in this manner, as shown in FIG. 4, the open area of the contact region 40 increases as much as the portion of the sidewall oxide film 35A. Increasing the open area of the contact area 40 has the advantage of increasing the open margin in the subsequent storage node contact process.

FIG. 4 is a view for explaining an open area of a contact area according to an exemplary embodiment of the present invention, and shows the subsequent cell bit line BL.

According to the prior art, since the storage node contact process is performed after forming the cell bit line, the height of the storage node contact is increased and the area of the substrate on which the storage node contact is to be formed is narrow, so that the area for forming the storage node contact is increased. The shrinkage increases storage node contact resistance and increases the likelihood of self-aligned contact failing between storage node contacts and buried gates due to over etching to open or open.

As shown in FIG. 2H, the plug conductive film is deposited on the entire surface until the contact region 40 is filled, and then the plug separation process is performed so that the surface of the sealing film 39 is exposed. As a result, a self aligned landing plug 41 is formed.

Since there is no contact etching process for forming a contact region, the loss of the substrate can be kept to a minimum, thereby minimizing interference between the landing plug 41 and the buried gate 38A. In addition, since the sidewall oxide film is removed when the contact region is opened, the contact resistance can be lowered because the substrate under the contact region can be utilized to the maximum.

The plug conductive film used as the landing plug 41 may use a metal film or a polysilicon film. In addition, after the epitaxial silicon film is grown through selective epitaxial growth (SEG), the polysilicon film may be deposited. In addition, after the epitaxial silicon film is grown through selective epitaxial growth (SEG), a metal film may be deposited.

Subsequently, a bit line process in a cell region and a gate (ferrigate) formation process in a peripheral region are performed.

3A to 3J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

The second embodiment is a post structure in which a gate conductive film in the peripheral region is later formed.

When the gate conductive film of the peripheral region is completed before the device isolation layer is formed, doped impurities of the gate conductive film (particularly, the polysilicon film doped with impurities) of the gate conductive film of the peripheral region are prevented by the heat generated in a subsequent process of the cell region. Can be diffused. In order to prevent this, the gate conductive film of the peripheral region is formed after the buried gate is formed.

As shown in FIG. 3A, a pad oxide film 52 and a hard mask polysilicon film 53 are stacked on a substrate 51 having a cell region and a peripheral region defined therein. Here, the pad oxide film 52 is used as a pad film in the cell region and as a gate oxide film in the peripheral region. The hard mask polysilicon film 53 is used as a hard mask film in the cell region, and unlike the first embodiment, it is not used as a gate conductive film in the peripheral region. Since it is not used as a gate conductive film in the peripheral region, impurities are not implanted into the hard mask polysilicon film 33.

In another embodiment, a hard mask nitride film may be further formed on the hard mask polysilicon film 33. In order to minimize damage of the hard mask polysilicon layer 33, a hard mask nitride layer is further formed and applied as a hard mask for forming a subsequent device isolation layer. At this time, the hard mask nitride film is completely removed in a subsequent cell gate separation process, and is formed to have a thickness of 300 to 800 Å in consideration of the degree of removal.

As shown in FIGS. 3B and 3C, a shallow trench isolation (STI) process is performed. That is, after forming the first trench 54 using the hard mask polysilicon film 53 as a hard mask, the insulating film is gap-filled to form the device isolation film 55. The device isolation layer 55 may be formed by a single gapfill process using a flowable oxide, and a combination of the flowable oxide film and the deposited oxide film may also be used. The flowable oxide film may include SOD (Spin On Dielectric), and the deposition oxide film may include a high density plasma oxide film (HDP Oxide).

Before forming the device isolation layer 35, the sidewall oxide layer 55A may be formed through a wall oxidation process and a liner nitride layer 55B may be formed on the sidewall oxide layer 55A.

As shown in FIG. 3D, a second trench 56 is formed in the cell region through a buried gate mask (not shown) and etching. That is, after the hard mask polysilicon layer 53 and the pad oxide layer 52 are etched, the second trench 56 is formed by sequentially etching the substrate 51 and the device isolation layer 55. The hard mask polysilicon film 53 is used as a hard mask at the time of forming the second trench 56.

As shown in FIG. 3E, a gate insulating layer 57 is formed on the surface of the second trench 56. The gate insulating film 57 is a gate insulating film for transistors in the cell region, and will be abbreviated as 'cell gate insulating film 57' for convenience of description below.

Subsequently, a metal film 58 is deposited on the entire surface of the cell gate insulating film 57 so as to gap-fill the second trench 56. The metal film 58 includes a titanium nitride film TiN, a tantalum nitride film TaN, a tungsten film W, or the like. For example, in order to lower the resistance, the titanium nitride film (or tantalum nitride film) may be formed by conformally thinly depositing a tungsten film. In addition, the titanium nitride film and the tantalum nitride film may be formed by laminating, or the titanium nitride film, the tantalum nitride film, and the tungsten film may be sequentially formed. At this time, the titanium nitride film is preferably formed to a thickness of 20 to 80 kPa.

Subsequently, the metal film 58 is planarized using a method such as CMP so that the surface of the hard mask polysilicon film 53 is exposed, and then the buried gate which partially fills the second trench 56 is etched back. 58A is formed. The surface of the buried gate 58A may have a height lower than that of the substrate 51.

As shown in FIG. 3F, a sealing film 59 for sealing the upper portion of the buried gate 58A is formed. Here, the sealing film 59 may be selected from an oxide film, a nitride film or a stacked structure of the nitride film and the oxide film. For example, after sealing the sealing nitride film 59A thinly, the sealing oxide film 59B such as SOD can be formed by gap filling. Preferably, since the pad oxide film serving as the gate insulating film is formed in the peripheral region, the sealing nitride film may be omitted since the risk of oxidation is small, thereby simplifying the process.

Next, the sealing film 59 is separated so that the surface of the hard mask polysilicon film 53 is exposed. The separation process of the sealing film 59 may use CMP or etch back. Preferably, the CMP is advantageous in terms of wafer uniformity or prevention of loss of the lower layer.

As shown in FIG. 3G, after the capping layer 60 is formed to remain only in the cell region using a peripheral region open mask (not shown), both the pad oxide layer and the hard mask polysilicon layer in the peripheral region are removed. In this case, the device isolation layer, the liner nitride layer, and the sidewall oxide layer may be partially etched in the peripheral region. The capping film 60 may be formed by stacking an oxide film, a nitride film, or a nitride film with an oxide film.

As shown in FIG. 3H, the ferrite gate insulating layer 61 is formed by performing a gate oxidation process for transistors in the peripheral region. Subsequently, after the gate polysilicon film 62 is deposited on the ferrite gate insulating film 61, impurities are implanted into the gate polysilicon film 62. The gate polysilicon layer 62 may be formed to have a thickness of 600 to 1500 Å, and a doping process of impurities may be performed to form the channel region before the ferrite gate insulating layer 61 is formed.

 In the gate oxidation process as described above, since the capping film 60, the hard mask polysilicon film 53, and the sealing film 59 protect the buried gate 58A, the buried gate 58A is not oxidized.

As shown in FIG. 3I, the capping layer 60, the hard mask polysilicon layer 53, and the pad oxide layer 52 are removed after covering the peripheral region and opening the cell region. Accordingly, the contact region 63 in which the landing plug is to be formed between the sealing layers 59 is opened in the cell region.

The process of removing the hard mask polysilicon film can be performed either by a wet process using a mixed solution of nitric acid and fluoric acid or by dry etching using a plasma. The pad oxide film can be removed through a wet process. When the pad oxide film is removed, a portion of the sidewall oxide film 55A is also removed. The wet etching is no longer performed by the liner nitride film 55B, so that only a predetermined amount of the area of the contact region 63 opened can be controlled. The landing plug is embedded in the contact region 63 in a subsequent process. If the wet etching stops at the liner nitride film 55B, the contact region 63 is widened to increase the possibility of bridging between neighboring contact regions. Therefore, a process capable of controlling this can be ensured with the liner nitride film 55B.

When the pad oxide film is removed in this manner, the open area of the contact region 64 increases as much as the portion where the sidewall oxide film 55A is located. Increasing the open area of the contact area 64 has the advantage of increasing the open margin in the subsequent storage node contact process.

According to the prior art, since the storage node contact process is performed after forming the cell bit line, the height of the storage node contact is increased and the area of the substrate on which the storage node contact is to be formed is narrow, so that the area for forming the storage node contact is increased. The shrinkage increases storage node contact resistance and increases the likelihood of self-aligned contact failing between storage node contacts and buried gates due to over etching to open or open.

As shown in FIG. 3J, the plug conductive film is deposited on the entire surface until the contact region 63 is filled, and then separated to expose the surface of the sealing film 59. As a result, the landing plug 64 is formed.

Since there is no contact etching process for forming a contact region, the loss of the substrate can be kept to a minimum, thereby minimizing interference between the landing plug 64 and the buried gate 58A. In addition, since the sidewall oxide film is removed when the contact region is opened, the contact resistance can be lowered because the substrate under the contact region can be utilized to the maximum.

The plug conductive film used as the landing plug 64 may use a metal film or a polysilicon film. In addition, after the epitaxial silicon film is grown through selective epitaxial growth (SEG), the polysilicon film may be deposited. In addition, after the epitaxial silicon film is grown through selective epitaxial growth (SEG), a metal film may be deposited.

After the landing plug 64 is formed in the cell region, the plug conductive layer 64A may also remain on the gate polysilicon layer 62 in the peripheral region. The plug conductive film 64A is used as a gate in the peripheral region.

Subsequently, the bit line process in the cell region and the gate formation process in the peripheral region are performed.

According to the first and second embodiments described above, if only the cell region is selectively opened after the device isolation layer and the buried gate process, and the hard mask polysilicon layer and the pad oxide layer are removed, the contact region can be opened without loss of the substrate. Thus, interference between the landing plug and the buried gate can be prevented as much as possible. In addition, since the substrate under the contact region can be used sufficiently, it is possible to lower the contact resistance and increase the open margin of the contact region.

When the pad oxide film is removed, the sidewall oxide film is also removed at the same time, so that the area of the contact region is increased, and the increase of the area is stopped in the liner nitride film, thereby preventing the bridge between adjacent landing plugs.

In addition, in the first embodiment, since the process of forming the gate conductive film in the peripheral region can be performed before the device isolation process, the process of forming the gate conductive film in the peripheral region can be eliminated to simplify the process. There is an effect that can prevent the oxidation of the buried gate that may occur in the gate oxidation process.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1E illustrate a method of manufacturing a semiconductor device having a buried gate according to the prior art.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

3A to 3J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

4 is a view for explaining the open area of the contact area according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 substrate 32 pad oxide film

33 hard mask polysilicon film 35 device isolation film

35A: sidewall oxide film 35B: liner nitride film

38A: buried gate 39: sealing film

41: Landing plug

Claims (24)

Forming a hard mask film on the substrate; Etching the substrate using the hard mask layer as an etch barrier to form a first trench; Forming an isolation layer gap-filling the first trenches; Forming a second trench by etching the substrate and the device isolation layer using the hard mask layer as an etch barrier; Forming a buried gate partially filling the second trench; Forming a sealing film gap-filling an upper portion of the buried gate; Removing the hard mask layer to open a contact region; And Forming a landing plug to fill the contact region A semiconductor device manufacturing method comprising a. The method of claim 1, The hard mask film is a semiconductor device manufacturing method comprising a polysilicon film. The method of claim 1, And the hard mask film is formed by laminating a polysilicon film and a nitride film. The method of claim 1, The landing plug may be formed of a metal structure, a polysilicon film, a laminated structure of an epitaxial silicon film and a polysilicon film using selective epitaxial growth (SEG), or an epitaxial silicon film and a metal film laminated structure using selective epitaxial growth (SEG). A semiconductor device manufacturing method comprising any one selected. Forming an etch barrier film on which a pad oxide film and a hard mask film are stacked on a substrate; Forming a first trench by etching the substrate using the etching barrier layer; Stacking a sidewall oxide layer and a liner nitride layer on sidewalls of the first trenches; Forming an isolation layer gap-filling the first trenches; Etching the substrate and the isolation layer to form a second trench; Forming a buried gate partially filling the second trench; Forming a sealing film gap-filling an upper portion of the buried gate Opening the contact region by removing the etch barrier layer and the sidewall oxide layer; And Forming a landing plug to fill the contact region A semiconductor device manufacturing method comprising a. The method of claim 5, The hard mask film is a semiconductor device manufacturing method comprising a polysilicon film. The method of claim 5, And the hard mask film is formed by laminating a polysilicon film and a nitride film. The method of claim 5, The landing plug may be formed of a metal structure, a polysilicon film, a laminated structure of an epitaxial silicon film and a polysilicon film using selective epitaxial growth (SEG), or an epitaxial silicon film and a metal film laminated structure using selective epitaxial growth (SEG). A semiconductor device manufacturing method comprising any one selected. The method of claim 5, In the step of opening the contact area, And removing the hard mask layer using a wet process or dry etching, and removing the pad oxide layer and the sidewall oxide layer using a wet process. Stacking a gate insulating film and a gate conductive film on a substrate in which a cell region and a peripheral region are defined; Etching the substrate using the gate conductive layer as an etch barrier to form a first trench; Forming an isolation layer gap-filling the first trenches; Etching the substrate and the device isolation layer using the gate conductive layer as a hard mask to form a second trench in the cell region; Forming a buried gate partially filling the second trench; Forming a sealing film gap-filling an upper portion of the buried gate Removing the gate conductive film and the gate insulating film of the cell region to open a contact region; And Forming a landing plug to fill the contact region A semiconductor device manufacturing method comprising a. The method of claim 10, After forming the first trench, Forming a sidewall oxide film on sidewalls of the first trenches; Forming a liner nitride film on the sidewall oxide film A semiconductor device manufacturing method further comprising. The method of claim 11, And removing the sidewall oxide film in the step of opening the contact region. The method of claim 10, The gate conductive film includes a polysilicon film doped with an impurity. The method according to any one of claims 10 to 13, And forming a hard mask nitride film on the gate conductive film. The method of claim 10, The landing plug may be formed of a metal structure, a polysilicon film, a laminated structure of an epitaxial silicon film and a polysilicon film using selective epitaxial growth (SEG), or an epitaxial silicon film and a metal film laminated structure using selective epitaxial growth (SEG). A semiconductor device manufacturing method comprising any one selected. The method of claim 10, The opening of the contact region may be performed while forming a mask covering the peripheral region and opening the cell region. The method of claim 16, In the step of opening the contact area, And removing the gate conductive layer using a wet process or dry etching, and removing the gate insulating layer using a wet process. Stacking a pad oxide film and a hard mask film on a substrate in which a cell region and a peripheral region are defined; Forming a first trench by etching the substrate using the hard mask layer as an etch barrier; Forming an isolation layer gap-filling the first trenches; Etching the substrate and the device isolation layer using the hard mask layer as an etch barrier to form a second trench in the cell region; Forming a buried gate partially filling the second trench; Forming a sealing film gap-filling an upper portion of the buried gate; Removing the hard mask layer and the pad oxide layer in the peripheral region; Stacking a gate insulating film and a gate conductive film on the substrate in the peripheral region; Opening the contact region by removing the hard mask layer and the pad oxide layer in the cell region; And Forming a landing plug to fill the contact region A semiconductor device manufacturing method comprising a. The method of claim 18, After forming the first trench, Forming a sidewall oxide film on sidewalls of the first trenches; Forming a liner nitride film on the sidewall oxide film A semiconductor device manufacturing method further comprising. The method of claim 19, And removing the sidewall oxide film in the step of opening the contact region. The method of claim 18, The hard mask film is a semiconductor device manufacturing method using a polysilicon film alone or a laminated structure of a polysilicon film and a hard mask nitride film. The method of claim 18, The landing plug may be formed of a metal structure, a polysilicon film, a laminated structure of an epitaxial silicon film and a polysilicon film using selective epitaxial growth (SEG), or an epitaxial silicon film and a metal film laminated structure using selective epitaxial growth (SEG). A semiconductor device manufacturing method comprising any one selected. The method of claim 18, The opening of the contact region may be performed while forming a mask covering the peripheral region and opening the cell region. 24. The method of claim 23, In the step of opening the contact area, And removing the hard mask layer using a wet process or dry etching and removing the pad oxide layer using a wet process.

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