KR20110118981A - Method for manufacturing semiconductor device with buried gate - Google Patents

Method for manufacturing semiconductor device with buried gate Download PDF

Info

Publication number
KR20110118981A
KR20110118981A KR1020100038414A KR20100038414A KR20110118981A KR 20110118981 A KR20110118981 A KR 20110118981A KR 1020100038414 A KR1020100038414 A KR 1020100038414A KR 20100038414 A KR20100038414 A KR 20100038414A KR 20110118981 A KR20110118981 A KR 20110118981A
Authority
KR
South Korea
Prior art keywords
etching
film
gate
trench
buried gate
Prior art date
Application number
KR1020100038414A
Other languages
Korean (ko)
Inventor
조준희
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100038414A priority Critical patent/KR20110118981A/en
Publication of KR20110118981A publication Critical patent/KR20110118981A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/469—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers
    • H01L21/4757—After-treatment
    • H01L21/47573—Etching the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

PURPOSE: A method for manufacturing a semiconductor device with a buried gate is provided to prevent a buried gate from being exposed in a contact etching process by implanting nitrogen ions to a gate insulation layer exposed to the outside of the buried gate. CONSTITUTION: A trench is formed by etching a substrate(21). A gate insulation layer(23A) is formed on the surface of the substrate and the trench. A buried gate(24) is formed by partially filling the trench. An etch barrier layer(26) is formed by post-processing the gate insulation layer. An interlayer dielectric layer(27) is formed on the front surface with the etch barrier layer. A contact hole(28) is formed by etching the interlayer dielectric layer and the etch barrier layer.

Description

Method for manufacturing semiconductor device with buried gate {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH BURIED GATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a buried gate.

As DRAM design rules are getting smaller, securing contact areas and capacitances are virtually impossible in conventional Planar Cell structures.

Therefore, a buried gate (BG) structure in which a gate is embedded in a substrate is used to secure an area of a storage node contact, a bit line, and a word line.

1 is a view illustrating a semiconductor device manufacturing method according to the prior art.

Referring to FIG. 1, after the substrate 11 is etched to form the trench 12, a gate oxidation process is performed. As a result, the surface of the trench 12 is oxidized to form the gate insulating film 13.

Subsequently, a buried gate 14 which partially fills the trench 12 is formed on the gate insulating film 13.

Subsequently, the interlayer insulating film 15 is formed on the entire surface including the buried gate 14 by using an oxide film, and then contact etching is performed. As a result, a contact hole 16 exposing the surface of the substrate 11 is formed.

However, the related art has a problem in which the buried gate 14 is exposed due to lack of selectivity with the lower gate insulating layer 13 in the contact etching process (see reference numeral 17). That is, since both the interlayer insulating film 15 and the gate insulating film 13 are oxide films, when the interlayer insulating film 15 is etched, the gate insulating film 13 is not used as an etching barrier and all are etched to expose a part of the buried gate 14. . Accordingly, there is a problem in that the contact plugs and the buried gates 14 embedded in the contact holes 16 are short-circuited.

The short circuit problem described above is a problem that must be improved because it causes an operation error of the device.

An object of the present invention is to provide a method for manufacturing a semiconductor device which can prevent a short circuit between the buried gate and the contact plug.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a trench by etching the substrate; Forming a gate insulating film on surfaces of the trench and the substrate; Forming a buried gate to partially fill the trench; Performing post-processing on the gate insulating film exposed outside the buried gate to form an etch barrier film; Forming an interlayer insulating film on an entire surface of the etching barrier film; And etching the interlayer insulating layer and the etching barrier layer to form a contact hole exposing the surface of the substrate. The post-treatment is characterized in that it comprises a nitrogen ion implantation or nitriding process.

The present invention described above prevents the buried gate from being exposed during the subsequent contact etching process by performing nitrogen treatment such as nitrogen ion injection or nitriding on the gate insulating film exposed after the buried gate formation, thereby preventing a short circuit between the buried gate and the contact plug. It can be effective.

1 is a view illustrating a semiconductor device manufacturing method according to the prior art.
2A to 2E illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A through 2E are diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a trench 22 is formed by etching a substrate 21 such as a silicon substrate. Although not shown in the drawings, an isolation layer is formed on the substrate 21 through a shallow trench isolation (STI) process, and an active region 21A is defined in the substrate 21 by the isolation layer. The active area 21A includes an area to which the bit line contact and the storage node contact are subsequently connected. This area is referred to as a bit line contact node and a storage node contact node. As an etching barrier for forming the trench 22, a hard mask film (not shown) including an oxide film, a nitride film, or a structure in which an oxide film and a nitride film are stacked may be used. When the substrate 21 includes a silicon substrate, the etching process for forming the trench 22 includes dry etching or wet etching. Dry etching is performed using a gas of Cl 2 or BCl 2 , wherein the flow rate of the gas is 5 to 1000 sccm. Wet etching uses HCl, wherein the wet etching is carried out at a temperature of 500 ~ 1000 ℃.

As shown in FIG. 2B, the gate insulating film 23 is formed through a gate oxidation process. In this case, the gate insulating film 23 may include a silicon oxide film.

Subsequently, a buried gate 24 which partially fills the trench 22 is formed on the gate insulating film 23. The method of forming the buried gate 24 follows a known method. For example, after the gate conductive film is formed on the entire surface until the trench 22 is gap-filled, planarization and entire surface etching are sequentially performed. The gate conductive film used as the buried gate 24 includes a metal film or a polysilicon film. The metal film may include at least one selected from the group consisting of a tantalum nitride film (TaN), a titanium nitride film (TiN), and a tungsten film (W). For example, the metal film may be formed of W, TiN or TaN alone, or may have a two-layer structure such as TiN / W or TaN / W in which a tungsten film is laminated on the titanium nitride film and the tantalum nitride film. The gate conductive film may be a conductive metal. Planarization includes a chemical mechanical polishing (CMP) process.

As described above, when the buried gate 24 is formed, the gate insulating layer 23 is exposed on the surface and sidewalls of the active region 21A.

As shown in FIG. 2C, the post treatment 25 is performed on the gate insulating film 23 exposed outside the buried gate 24. The aftertreatment 25 includes nitrogen treatment. Nitrogen treatment includes N 2 Implantation or Nitridation. The nitriding process uses nitrogen anneal (N 2 anneal) or nitrogen plasma (N 2 Plasma).

When the post treatment 25 is performed using nitrogen treatment, the exposed gate insulating film 23 is modified to an etching barrier film 26 containing nitrogen. When the gate insulating layer 23 includes an oxide layer, the etching barrier layer 26 includes an oxynitride layer. When the gate insulating film 23 is a silicon oxide film, the etching barrier film 26 may be a silicon oxide nitride (SiON).

As described above, when the etching barrier layer 26 containing nitrogen is formed, an etching process having an excellent selectivity with respect to the etching barrier layer 26 may be applied during the subsequent contact etching process. This prevents the buried gate 24 from being exposed. Even when the etching barrier film 26 is formed, the gate insulating film 23A remains around the buried gate 24, so that the characteristics of the device are not affected in a subsequent process.

As shown in FIG. 2D, an interlayer insulating film 27 is formed on the entire surface including the etch barrier film 26. The interlayer insulating film 27 includes an oxide film.

Subsequently, a contact etching process is performed. For example, the interlayer insulating layer 27 is etched to form the contact hole 28. When the interlayer insulating layer 27 is etched, the etching may be stopped in the etch barrier layer 26. This is because the etching of the interlayer insulating film 27 is an oxide film etching process, so that the etching is stopped in the etching barrier film 26 containing nitrogen. Therefore, an oxide film etching process having an excellent selectivity with respect to the etching barrier film 26 can be applied.

On the other hand, even if the contact etching process is not aligned on the active region 21A and misaligned, the buried gate 24 is not exposed because the etching is stopped by the etching barrier layer 26.

As shown in FIG. 2E, the etching barrier layer 26 is etched to complete the contact hole 28A exposing the surface of the active region 21A. The etching of the etching barrier film 26 may apply a nitride film etching process and stops when the surface of the active region 21A is exposed, so that the buried gate 24 is not exposed.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

21 substrate 22 trench
23, 23A: gate insulating film 24: buried gate
25: Post-Processing 26: Etch Barrier Film
27: interlayer insulating film 28, 28A: contact hole

Claims (6)

Etching the substrate to form a trench;
Forming a gate insulating film on surfaces of the trench and the substrate;
Forming a buried gate to partially fill the trench;
Performing post-processing on the gate insulating film exposed outside the buried gate to form an etch barrier film;
Forming an interlayer insulating film on an entire surface of the etching barrier film; And
Etching the interlayer insulating layer and the etching barrier layer to form a contact hole exposing a surface of the substrate;
≪ / RTI >
The method of claim 1,
The post-treatment,
A semiconductor device manufacturing method comprising nitrogen treatment.
The method of claim 1,
The post-treatment,
A semiconductor device manufacturing method comprising a nitrogen ion implantation or nitriding process.
The method of claim 1,
The post-treatment,
A semiconductor device manufacturing method using nitrogen anneal or nitrogen plasma.
The method of claim 1,
And the gate insulating film comprises an oxide film and the etching barrier film comprises a film containing nitrogen.
The method of claim 1,
The gate insulating layer includes a silicon oxide layer, and the etching barrier layer includes a silicon oxynitride layer.
KR1020100038414A 2010-04-26 2010-04-26 Method for manufacturing semiconductor device with buried gate KR20110118981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100038414A KR20110118981A (en) 2010-04-26 2010-04-26 Method for manufacturing semiconductor device with buried gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100038414A KR20110118981A (en) 2010-04-26 2010-04-26 Method for manufacturing semiconductor device with buried gate

Publications (1)

Publication Number Publication Date
KR20110118981A true KR20110118981A (en) 2011-11-02

Family

ID=45390616

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100038414A KR20110118981A (en) 2010-04-26 2010-04-26 Method for manufacturing semiconductor device with buried gate

Country Status (1)

Country Link
KR (1) KR20110118981A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9153590B2 (en) 2013-11-05 2015-10-06 Samsung Electronics Co., Ltd. Semiconductor devices including buried channels
US9349858B2 (en) 2012-09-17 2016-05-24 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9349858B2 (en) 2012-09-17 2016-05-24 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9153590B2 (en) 2013-11-05 2015-10-06 Samsung Electronics Co., Ltd. Semiconductor devices including buried channels

Similar Documents

Publication Publication Date Title
KR101094372B1 (en) Method for manufacturing semiconductor device with buried gate
US8445369B2 (en) Method for fabricating semiconductor device
JP2009158591A (en) Semiconductor device and process for manufacturing same
JP2006245578A (en) Manufacturing method of semiconductor device
US20150214234A1 (en) Semiconductor device and method for fabricating the same
KR101168606B1 (en) wiring structure of semiconductor device and Method of forming a wiring structure
US8334207B2 (en) Method for fabricating semiconductor device with buried gates
KR20020031283A (en) Integrated Circuit Device And Method For Manufacture The Same
KR20090025778A (en) Method of forming a contact hole in semiconductor device
US8445957B2 (en) Semiconductor device and method of manufacturing the same
JP2010118439A (en) Semiconductor memory device and method for manufacturing the same
JP2009200154A (en) Semiconductor device and manufacturing method thereof
KR20100008942A (en) Semiconductor device and manufacturing method thereof
US7972941B2 (en) Method of manufacturing a semiconductor device
US8835280B1 (en) Semiconductor device and method for manufacturing the same
KR20110118981A (en) Method for manufacturing semiconductor device with buried gate
KR20120004241A (en) Method for manufacturing semiconductor device
KR100927777B1 (en) Manufacturing Method of Memory Device
KR100778881B1 (en) Ferroelectric random access memory and methods of forming the same
KR100791343B1 (en) Semiconductor device and method for fabricating the same
KR101103550B1 (en) A method for forming a metal line in semiconductor device
JP2005175348A (en) Semiconductor memory device and method for manufacturing the same
KR20120127026A (en) Method for fabricating semiconductor device
KR20090001396A (en) Method for manufacturing semiconductor device
US20080290429A1 (en) Semiconductor device and method for fabricating the same

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination