KR20110052047A - Test circuit in semiconductor device including copper wire - Google Patents

Abstract

The present invention provides a test circuit and a test method for a semiconductor device capable of efficiently detecting the movement of copper contained in the metal wiring in the semiconductor device. In an embodiment, a semiconductor device includes a cell region including a first metal wiring formed of copper (Cu) and a second metal wiring connected to the first metal wiring, and the scribe lane region includes a first metal wiring and a first metal wiring. A test circuit including a first pattern composed of substantially the same shape and material and a second pattern composed of substantially the same shape and material as the second metal wiring is included.

Description

TEST CIRCUIT IN SEMICONDUCTOR DEVICE INCLUDING COPPER WIRE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a circuit capable of testing a defect due to the physical properties of copper when using copper wiring in a highly integrated semiconductor device.

The semiconductor device is designed to operate according to a predetermined purpose by injecting impurities into a predetermined region of a silicon wafer or depositing a new material. A representative example is a semiconductor memory device. The semiconductor memory device includes many elements such as a transistor, a capacitor, a resistor, and a fuse to perform a predetermined purpose.

Recently, semiconductor devices have been developed to not only be highly integrated but also to reduce power consumption. When the semiconductor device is highly integrated, the size of various components included in the semiconductor device is also reduced. Specifically, the cross-sectional area occupied by transistors and capacitors is reduced, and the width and cross-sectional area of the wiring connecting the components are also reduced. On the other hand, in order to reduce power consumption, it is necessary to lower the operating voltage or reduce the resistance in the semiconductor device to prevent unnecessary power consumption. In recent years, highly integrated semiconductor devices use copper (Cu) having low resistance as the size and area of wirings, fuses, and the like decrease in resistance, thereby increasing resistance.

However, in materials with low strength, high heat conduction, and high corrosion compared to other metal materials such as copper (Cu), the residues generated during the blowing of the fuse or the materials remaining in the fuse are subjected to high temperature or high humidity conditions. Can be migrated according to their electrochemical properties.

1 is a photograph for explaining a defect of a copper wiring used in a general semiconductor device.

As illustrated, a plurality of first wires 110 and second wires 120 are formed in the semiconductor device, and the first wires 110 and the second wires 120 are connected to each other through the contact 130. It is. In detail, an empty space 140 is formed between the first wiring 110 made of copper (Cu) and the contact 130 due to the movement of copper. The empty space 140 increases the contact resistance between the contact 130 and the first wiring 110 to cause a defect of the semiconductor device.

While copper is used for metal wiring in semiconductor memory devices, copper is used for word lines in cell regions in addition to wiring for fuses and power supply. In the case of forming a contact on a word line formed of copper, as shown in FIG. 1, a defect may occur due to movement of copper. However, since many components such as cell transistors and capacitors constituting the unit cell are densely arranged in the cell region of the semiconductor memory device, it is difficult to check defects due to copper migration.

Conventionally, defects due to copper migration in the cell region could only be detected by conducting a probe test after fabrication of a semiconductor device. Probe test is a time-consuming feature that allows the overall inspection of unit cell defects in a semiconductor device. If the defects due to copper migration in copper wires are measurable only through complex and time-consuming probe tests, this results in wasteful time finding defects in the manufacturing process of semiconductor devices.

In order to solve the above-mentioned conventional problems, the present invention provides a semiconductor device capable of efficiently detecting defects in a semiconductor device by forming a simple circuit in a test area in order to detect movement of copper included in metal wirings in a semiconductor device. Provides test circuits and test methods.

The present invention provides a semiconductor device including a cell region including a first metal wiring formed of copper (Cu) and a second metal wiring connected to the first metal wiring, wherein the scribe lane region is substantially the same as the first metal wiring. A semiconductor device comprising a test circuit including a first pattern composed of the same shape and material and a second pattern composed of the same shape and material as the second metal wiring.

Preferably, the second metal wire is characterized in that it comprises a tungsten, aluminum, titanium-based metal material.

Preferably, the first metal wiring is a sub word line, and the second metal wiring is a main word line.

Preferably, the first metal wiring is a gate in the sensing amplifier, and the second metal wiring is a wiring for supplying driving power for the winding amplifier.

Preferably, the first metal wire and the second metal wire are formed at different heights and connected to each other through a first contact, and the first pattern and the second pattern are also connected to the first metal wire and the second metal wire. Characterized in that the structure is substantially the same as the metal wiring.

In addition, the present invention is a test method of a semiconductor device for detecting the movement of copper contained in the metal wiring, the scribe lane made of substantially the same shape and material as the first metal wiring formed of copper (Cu) in the cell region Measuring a resistance of a test circuit comprising a first pattern of an area and a second pattern of the scribe lane area comprised of a shape and a material substantially the same as a second metal wire connected to the first metal wire in the cell area; A test method for a semiconductor device is provided.

Preferably, the first metal wiring is a sub word line, and the second metal wiring is a main word line.

Preferably, the first metal wiring is a sub word line, and the second metal wiring is a main word line.

In the present invention, when metal wiring is formed using copper (Cu) in a highly integrated semiconductor device, defects in the semiconductor device may be efficiently replaced by measuring resistance in a simple test circuit instead of a probe test to detect copper migration. There is an advantage that can be detected.

According to the present invention, a structure identical to a structure using copper in a semiconductor memory device is formed in a scribe lane area to enable resistance measurement, thereby accurately detecting a defect due to copper migration in a short time. Provide a test circuit.

According to the present invention, when copper is used for metal wiring to prevent processing delays or power loss due to increased resistance as the size of components increases as the degree of integration of semiconductor devices increases, copper migration can be detected. Provides test circuits and test methods. On a semiconductor wafer on which a plurality of semiconductor devices are formed, a cell region including a plurality of unit cells, a peripheral region including an input / output pad, and the like, and patterns for aligning or testing the components formed in the cell region or the peripheral region. A scribe lane area is included.

Here, a plurality of components included in the cell region and the peripheral region are well known to those skilled in the art, and the shape and shape thereof may vary depending on the manufacturing process. Since the present invention relates to a test circuit formed in the scribe lane region and a test method using the test circuit, description of components formed in the cell region and the peripheral region will be omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are plan views illustrating a test circuit manufacturing method of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a first pattern 210 corresponding to a bit line formed in the cell region is formed in the scribe lane region. In this case, the first pattern 210 is formed at substantially the same height as the bit line and is formed of substantially the same material. However, the first pattern 210 is different from the bit line of the cell region and its shape, and the shape and position of the first pattern 210 correspond to the position and shape of the second pattern 220 formed in a subsequent process. Is determined.

Referring to FIG. 2B, a contact hole (not shown) is formed in an interlayer insulating film (not shown) deposited on the first pattern 210, and then a contact (not shown) is formed by filling a conductive material. To form a second pattern 220 connected thereto. This process is performed substantially the same as in the cell region, and the second pattern 220 is formed in the same shape as the gate (not shown) of the sense amplifier (not shown) formed in the cell region. The reason for forming the second pattern 220 in the same manner as the gate of the sense amplifier is to use copper (Cu) in the gate of the sense amplifier and to form a test circuit having the same structure and material in the scribe lane region. to be.

The shape of the third pattern 230 formed on the second pattern 220 is illustrated in FIG. 2C, and the fourth pattern 240 for connecting a portion of the third pattern 230 is described in FIG. 2D. do. Both the third pattern 230 and the fourth pattern 240 are connected to the second pattern through a contact and correspond to a power supply line formed on the sensing amplifier gate in the cell region.

In FIG. 2E, the fifth pattern 250 formed on the third pattern 230 and the fourth pattern 240 will be described. In this case, the fifth pattern 250 does not correspond to components included in the cell region, and is formed for a function of an input / output pad for supplying power to and outputting a test circuit formed in the scribe lane region.

3A and 3B are a plan view and a cross-sectional view for explaining the operation of a test circuit according to an embodiment of the present invention.

Referring to FIG. 3A, after a power is supplied through a fifth pattern 250 to a test circuit including the first patterns 210 to fifth patterns 250 illustrated in FIGS. 2A to 2E, another fifth pattern ( 250). When power is supplied to the test circuit, a current path as shown by a dotted line is formed, and the resistance value of the current path can be calculated through the measured value through the fifth pattern 250. The resistance value is within the range expected by the pattern structure and the material in the test circuit, but when copper (Cu) migration occurs, a resistance value much larger than the expected resistance value is obtained. If the resistance value in the test circuit in the scribe lane region is much larger than expected, it may be determined that the movement phenomenon occurs in the copper (Cu) deposited in the conductive region in the cell region.

As described above, the present invention does not determine whether copper movement occurs in the wiring formed directly in the cell region, but indirectly recognizes copper movement through a test circuit formed of the same structure and material as the cell region. On the other hand, instead of forming various test environments in a cell structure of a complex structure in the past and testing for a long time, in one embodiment of the present invention, the movement of copper is recognized simply by supplying power and measuring resistance values. can do.

Referring to FIG. 3B, a cross section of the test circuit formed in the scribe lane region will be described. The first pattern 210, the second pattern 230, and the third pattern 230 are made of the same structure and material as those of the components included in the actual cell region, and the first pattern 210 and the second pattern ( The contact connecting between the 230 and the third pattern 230 is also formed in the same manner as the cell region. Although not shown, the fourth pattern 240 and the third pattern 230 are formed at substantially the same height. When power is supplied to the test circuit having the structure through the fifth pattern 250, the first pattern 210, the second pattern 230, and the third pattern 230 electrically connected between the fifth pattern 250. The current path passing through all of the can be formed. As described above, when the second pattern 230 corresponding to the gate of the sensing amplifier included in the cell region is formed of copper (Cu), when the movement of copper occurs in the second pattern 230, It may be determined that an empty space is generated between the two patterns 230 and the contact due to the movement of copper.

In the above embodiment, a test circuit corresponding to the gate of the sensing amplifier included in the cell region formed of copper is formed in the subscription lane region, and power is supplied to test the movement of copper. Hereinafter, a case in which the sub word line is formed of copper in the cell region in another embodiment of the present invention will be described. 4A to 4D are plan views illustrating a test circuit manufacturing method of a semiconductor device according to example embodiments of the inventive concepts.

Referring to FIG. 4A, a first pattern 410 is formed in a subscription lane area corresponding to a bit line of a cell area. The first pattern 410 is formed to overlap some areas with the second pattern 420 formed in a subsequent process. When the test circuit is completed as in the above-described embodiment, the first pattern 410 has the A current path can be formed along the direction.

FIG. 4B illustrates the second pattern 420 formed of the same structure and material as the sub word line formed in the cell region. Recently, as the integration degree of a semiconductor memory device is improved and the storage capacity increases, the number of unit cells included in a cell area is increased, and a sub word line and a main word line are provided for row access. When copper is used as a sub word line that is more sensitive to resistance and signal transfer speed than the main word line, the second pattern 420 having the same structure and material of the sub word line is subscribed to confirm copper migration. Form in the lane area.

4C illustrates the third pattern 430 formed on the second pattern 420, and FIG. 4D illustrates the fourth pattern 440 formed on the third pattern 430. As described above, the first pattern 410, the second pattern 430, and the third pattern 430 are made of the same structure and material as those of the components included in the actual cell region. The contact connecting between the 410, the second pattern 430, and the third pattern 430 is also formed in the same manner as the cell region. In detail, the third pattern 430 may be formed to correspond to the main word line of the cell region, and the fourth pattern 440 may be used as a power input / output pad for supplying power to the test circuit. The power applied through the fourth pattern 440 flows along a current path composed of the third pattern 430, the second pattern 420, and the first pattern 410 electrically connected, and measures the resistance of the current path. It is determined whether the copper migration phenomenon has occurred.

As described above, a semiconductor device according to an embodiment of the present invention includes a cell region including a first metal wire formed of copper (Cu) and a cell region including a second metal wire connected to the first metal wire. The scribe lane region includes a test circuit including a first pattern formed of substantially the same shape and material as the first metal wire and a second pattern formed of substantially the same shape and material as the second metal wire. In particular, when copper (Cu) is used in some of the metal wirings included in the cell region, copper phenomena occur in the cell region by manufacturing the same pattern corresponding to the metal wiring formed of copper (Cu) in the test circuit. You can indirectly verify that you have done so.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1 is a photograph for explaining a defect of a copper wiring used in a general semiconductor device.

2A to 2E are plan views illustrating a test circuit manufacturing method of a semiconductor device according to an embodiment of the present invention.

3A and 3B are a plan view and a cross-sectional view for explaining the operation of the test circuit according to an embodiment of the present invention.

4A to 4D are plan views illustrating a test circuit fabrication method of a semiconductor device in accordance with another embodiment of the present invention.

Claims (8)

A semiconductor device comprising a cell region including a first metal wiring formed of copper (Cu) and a second metal wiring connected to the first metal wiring. The scribe lane region includes a test circuit including a first pattern composed of a shape and a material substantially the same as the first metal wire and a second pattern composed of a shape and a material substantially the same as the second metal wire. Semiconductor device. The method of claim 1, And the second metal wire includes a tungsten, aluminum, or titanium-based metal material. The method of claim 1, And the first metal wiring is a sub word line, and the second metal wiring is a main word line. The method of claim 1, And the first metal wiring is a gate in the sense amplifier, and the second metal wiring is a wiring for supplying driving power for the winding amplifier. The method of claim 1, The first metal wire and the second metal wire are formed at different heights and connected to each other through a first contact, and the first pattern and the second pattern are also substantially connected to the first metal wire and the second metal wire. A semiconductor device, characterized in that formed in the same structure. In the test method of a semiconductor device for detecting the movement of copper contained in the metal wiring, A first pattern of the scribe lane region formed of substantially the same shape and material as the first metal wiring formed of copper (Cu) in the cell region, and substantially the same as a second metal wiring connected to the first metal wiring in the cell region And measuring a resistance of a test circuit including a second pattern of the scribe lane region formed of a shape and a material. The method of claim 6, And the first metal wire is a sub word line, and the second metal wire is a main word line. The method of claim 6, And the first metal wire is a sub word line, and the second metal wire is a main word line.

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