KR20110030885A - Liquid crystal display and method of driving the same - Google Patents

Abstract

PURPOSE: A liquid crystal display and a method of driving the same are provided to increase image quality by automatically driving horizontal two dot inversion method. CONSTITUTION: In a liquid crystal display and a method of driving the same, the data lines and gate lines are crossed with the liquid crystal panel. A data driving circuit converts digital video data into the positive/negative polarity analog voltage. A gate driving circuit supplies a gate pulse to gate lines. The gate pulse is synchronized with data voltages. A timing controller(101) controls the operation timing of the data driving circuit and gate driving circuit. The timing controller controls the horizontal polarity of the data voltage with horizontal two dot inversion.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND METHOD OF DRIVING THE SAME}

The present invention relates to a liquid crystal display and a driving method thereof.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), which is applied to a display device in a portable information device, an office device, a computer, and a TV, and is rapidly replacing a cathode ray tube.

The liquid crystal cells of the liquid crystal display display an image by changing the transmittance according to the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode. In general, the liquid crystal display device is driven in an inversion method in which the polarity of the data voltage applied to the liquid crystal is periodically inverted in order to prevent deterioration of the liquid crystal. When the liquid crystal display is driven in an inversion method, the image quality of the liquid crystal display may be degraded according to the correlation between the polarity of the data voltage charged in the liquid crystal cells and the data pattern of the input image. According to the data voltage charged in the liquid crystal cell, the polarities of the data voltages charged in the liquid crystal cells do not balance the positive and negative polarities, and either polarity becomes the dominant polarity, thereby shifting the common voltage applied to the common electrode. Because it becomes. When the common voltage is shifted, the reference potential of the liquid crystal cells is shaken, and thus an observer may feel flicker or smear in an image displayed on the liquid crystal display.

1 illustrates data examples of a problem pattern in which image quality may be degraded when the liquid crystal display is driven in dot inversion.

Among the problem patterns, as shown in FIG. 1, a pattern in which the pixel data of white gray (white) and the pixel data of black gray (black) are alternated by one pixel unit is called a shutdown pattern. Each of the pixel data includes red subpixel data R, green subpixel data G, and blue subpixel data B. The detection method of the shutdown pattern may count the shutdown pattern included in the input image and determine whether the shutdown pattern is based on the count value. For example, the detection method of the shutdown pattern is to increase the count value of the problem pixel counter by 1 when the N (N is a positive integer) pixel data is white gray pixel data and the N + 1 th pixel data is black gray pixel data. When the count value is greater than or equal to a predetermined threshold, the data of the input image is determined as a shutdown pattern.

In order to recognize the shutdown pattern, as shown in FIG. 2, a maximum of (2 ³ -1) × 2 = 14 patterns that can appear in six subpixels must be defined in advance, and detection logic for detecting each of the patterns is provided. need. In the case of the smear pattern, a maximum of (2 ⁶ -1) x 2 = 126 patterns that can appear in the 12 subpixel data must be defined in advance, and a detection logic module for detecting each of the patterns is required. Do.

In addition to the shutdown pattern, there are various types of patterns that degrade image quality in dot inversion, and one of them is a flicker pattern.

Meanwhile, when recognizing the flicker pattern from the input image, a method of preventing flicker by changing the polarity inversion period of the dot inversion may be considered. An example of such a method is disclosed in Korean Patent Application No. 10-2009-0075382 (2009.08.14) filed by the applicant of the present application. However, in this method, if the flicker pattern recognition method recognizes the shutdown pattern as described above and changes the dot inversion, the flicker does not appear and thus the common voltage shift cannot be determined. Accordingly, when the dot inversion is changed when the flicker pattern is input, it is difficult to optimize the common voltage because it is difficult to know the degree of shift of the common voltage in the common voltage tuning process.

An object of the present invention is to solve the problems of the prior art, the liquid crystal display and the dot inversion control to automatically change to a dot inversion of good quality when the problem patterns are input, and to tune the common voltage To provide a method.

In order to achieve the above object, the liquid crystal display device of the present invention comprises a liquid crystal display panel crossing the data lines and the gate line; A data driving circuit converting digital video data into a positive / negative analog data voltage and outputting the digital video data to the data lines; A gate driving circuit sequentially supplying gate pulses synchronized with the data voltages to the gate lines; And supplying digital video data of an input image to the data driving circuit, controlling operation timings of the data driving circuit and the gate driving circuit, and analyzing digital video data of the input image to input data of a first problem pattern. When the horizontal polarity of the data voltage output from the data driving circuit is controlled to a horizontal two dot inversion, and when the data of the second problem pattern is input, the horizontal polarity of the data voltage output from the data driving circuit is horizontal. A timing controller for controlling by one dot inversion is provided.

The driving method of the liquid crystal display device of the present invention comprises the steps of analyzing the digital video data of the input image to determine a first problem pattern and a second problem pattern in the input image; Controlling the horizontal polarity of the data voltage output from the data driving circuit when the data of the first problem pattern is input to a horizontal two dot inversion; And controlling the horizontal polarity of the data voltage output from the data driving circuit when the data of the second problem pattern is input to horizontal one dot inversion.

According to the present invention, various types of problem patterns are defined in advance, and when a problem pattern other than a flicker pattern is input, the liquid crystal display is automatically driven with a horizontal two-dot inversion, and the image quality is exceptional. When the flicker pattern is input, the liquid crystal display is driven in a vertical 1 dot inversion to enable common voltage tuning.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 12.

Referring to FIG. 3, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel 100, a timing controller 101, a data driving circuit 102, and a gate driving circuit 103. The data driving circuit 102 includes a plurality of source drive ICs (Integrated Circuit). The gate driving circuit 103 includes a plurality of gate drive ICs.

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes liquid crystal cells Clc arranged in a matrix by a cross structure of the data lines 105 and the gate lines 106.

A pixel array is formed on the lower glass substrate of the liquid crystal display panel 100. The pixel array includes liquid crystal cells Clc formed at the intersection of the data lines 105 and the gate lines 106, TFTs connected to the pixel electrode 1 of the liquid crystal cells, and a storage capacitor Cst. do. The pixel array may be implemented in various forms as shown in FIGS. 4 to 6. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. Black matrices, color filters, and the like are formed on the upper glass substrate of the liquid crystal display panel 100. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100 to form an alignment layer for setting a pre-tilt angle of the liquid crystal.

The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate.

The liquid crystal display panel 100 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 101 supplies digital video data RGB of the input image input from the system board 104 to the data driving circuit 102. The timing controller 101 receives timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal Data Enable (DE), and a dot clock CLK from the system board 104. Control signals for controlling the operation timing of the driving circuit 102 and the gate driving circuit 103 are generated. The control signals include a gate timing control signal for controlling the operation time of the gate driving circuit 103, a data timing control signal for controlling the operation timing of the data driving circuit 102 and the vertical polarity of the data voltage. The timing controller 101 controls the gate timing control signal so that digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array PA of the liquid crystal display panel at a frame frequency of 60 x i (i is a positive integer) Hz. And the frequency of the data timing control signal can be multiplied by a frame frequency reference of 60 x i (i is a positive integer of 2 or more) Hz.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC that generates the first gate pulse to control the gate drive IC so that the first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a vertical polarity control signal (POL), a horizontal polarity control signal (HINV), and a source output enable. Signal (Source Output Enable, SOE) and the like. The source start pulse SSP controls the data sampling start timing of the data driving circuit 102. The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source drive ICs based on a rising or falling edge. The vertical polarity control signal POL controls the vertical polarity of the data voltages sequentially output from each of the source drive ICs. The horizontal polarity control signal HINV is supplied to the H_2DOT option terminal of each of the source drive ICs to control the horizontal polarity of the data voltages simultaneously output from each of the source drive ICs. The vertical polarity control signal POL is inverted in two horizontal periods when the data driving circuit 102 is controlled by the vertical two dot inversion, and is 1 when the data driving circuit 102 is controlled by the vertical one dot inversion. The logic is reversed with a period of horizontal period. The horizontal polarity control signal HINV is generated in high logic when the data driving circuit 102 is controlled by the horizontal 2-dot inversion, and low logic occurs when the data driving circuit 102 is controlled by the horizontal 1 dot inversion. do. The source output enable signal SOE controls the output timing of the data driver circuit 102. If the digital video data to be input to the data driving circuit 102 is transmitted in mini LVDS (Low Voltage Differential Signaling) interface standard, the source start pulse SSP and the source sampling clock SSC may be omitted.

The timing controller 101 recognizes various types of problem patterns in the input image data, and changes the dot inversion when the problem patterns are detected. For example, when the shutdown pattern or the smear pattern is recognized among the problem patterns, the timing controller 101 inverts the horizontal polarity control signal HINV to high logic to change the dot inversion of the liquid crystal display panel 100 to the horizontal two dot inversion. Change to In exceptional cases, the timing controller 101 does not change the dot inversion when the flicker patterns shown in FIGS. 11 and 12 are recognized. This is to recognize the shift degree of the common voltage Vcom in the common voltage tuning process.

Each of the source drive ICs of the data driver circuit 102 includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The data driving circuit 102 latches the digital video data RGB under the control of the timing controller 101. The data driving circuit 102 converts the digital video data RGB into analog positive / negative gamma compensation voltages in response to the vertical polarity control signal POL, thereby inverting the polarity of the data voltages. Data voltages having a polar pattern of horizontal dot inversion determined according to HINV) are simultaneously output.

The gate driving circuit 103 sequentially supplies gate pulses to the gate lines 106 according to gate timing control signals using a shift register and a level shifter.

4 through 6 are equivalent circuits showing various examples of the pixel array.

The pixel array of FIG. 4 is a pixel array applied to most liquid crystal displays, and the data lines D1 to D6 and the gate lines G1 to G4 intersect each other. In this pixel array, each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the column direction. Each of the TFTs includes a pixel electrode of a liquid crystal cell in which data voltages from the data lines D1 to D6 are disposed on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G4. To feed. In the pixel array illustrated in FIG. 4, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels B along a row direction (or a line direction) orthogonal to the column direction. . When the resolution of the pixel array shown in FIG. 4 is m × n, m × 3 (where 3 is RGB) data lines and n gate lines are required. Gate pulses of one horizontal period synchronized with the data voltage are sequentially supplied to each of the gate lines of the pixel array.

The pixel array shown in FIG. 5 can reduce the number of data lines required at the same resolution by one half and the number of source drive ICs required can be reduced by half compared to the pixel array shown in FIG. 4. In this pixel array, each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the column direction. In the pixel array illustrated in FIG. 5, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels G along a line direction perpendicular to the column direction. In the pixel array shown in FIG. 5, the liquid crystal cells adjacent to the left and right share the same data line and continuously charge the data voltage supplied in a time division manner through the data line. The liquid crystal cell and the TFT disposed on the left side of the data lines D1 to D4 are defined as the first liquid crystal cell and the first TFT T1, respectively, and the liquid crystal cell and the TFT disposed on the right side of the data line D1 to D4 are defined. The connection relationship between the TFTs is defined as the second liquid crystal cell and the second TFT (T2), respectively. The first TFT T1 supplies the data voltage from the data lines D1 to D4 to the pixel electrode of the first liquid crystal cell in response to the gate pulses from the odd gate lines G1, G3, G5, and G7. The gate electrode of the first TFT T1 is connected to the odd gate lines G1, G3, G5, and G7, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the first TFT T1 is connected to the pixel electrode of the first liquid crystal cell. The second TFT T2 supplies the data voltage from the data lines D1 to D4 to the pixel electrode of the second liquid crystal cell in response to the gate pulses from the even gate lines G2, G4, G6, and G8. The gate electrode of the second TFT T2 is connected to the even gate lines G2, G4, G6, and G8, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the second TFT T2 is connected to the pixel electrode of the second liquid crystal cell. When the resolution of the pixel array shown in FIG. 6 is m × n, {m × 3 (where 3 is RGB)} / 2 data lines and 2n gate lines are required. Each of the gate lines of the pixel array PA is sequentially supplied with gate pulses of 1/2 horizontal period synchronized with the data voltage.

The pixel array shown in FIG. 6 can reduce the number of data lines required by the same resolution to one third and the number of source drive ICs required to one third as compared to the pixel array shown in FIG. 4. In this pixel array, each of the red subpixel R, the green subpixel G, and the blue subpixel B are disposed along the line direction. In the pixel array illustrated in FIG. 6, one pixel includes neighboring red subpixels R, green subpixels G, and blue subpixels G in a column direction. Each of the TFTs includes a pixel electrode of a liquid crystal cell in which data voltages from the data lines D1 to D6 are disposed on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G6. To feed. When the resolution of the pixel array PA illustrated in FIG. 6 is m × n, m data lines and 3n gate lines are required. Gate pulses of one-third horizontal period in synchronization with the data voltage are sequentially supplied to each of the gate lines of the pixel array PA.

7 is a block diagram illustrating a problem pattern recognition and a polarity control part in the timing controller 101.

Referring to FIG. 7, the timing controller 101 includes a problem pattern recognizer 71 and a polarity controller 72 that detect various problem patterns from input image data.

The problem pattern recognition unit 71 extracts data having a predetermined size from one frame data of the input image, for example, sample data of 8 pixels x 12 lines as shown in FIG. The problem pattern recognition unit 71 counts the number of white-black patterns and black-white patterns for each RGB of the sample data, and compares the sum of counts for each of the RGB with the previously stored thresholds to determine whether or not the problem pattern is present. Recognize the problem pattern type. The white-black pattern is two horizontally neighboring pixel data including N-th pixel data of white gray and N + 1-th pixel data of black gray as shown in FIG. 2. The black-white pattern is two horizontally adjacent pixel data including N-th pixel data of white gray and N + 1-th pixel data of black gray as shown in FIG. 3. The problem pattern recognition unit 71 generates the problem pattern flag PR as the first logic when the flicker pattern is detected in the input image data, and generates a second problem pattern flag PR when the other problem patterns are detected. Occurs with logic Hereinafter, the first logic of the problem pattern flag PR will be described as a low logic L, and the second logic will be described as a high logic H.

The polarity control unit 72 outputs the horizontal polarity control signal HINV according to the problem pattern flag PR input from the problem pattern recognition unit 71. The polarity control unit 72 outputs the horizontal polarity control signal HINV to the low logic L when the problem pattern flag PR is the first logic to horizontally dot the horizontal polarity of the data voltages output from the source drive IC. To control. If the problem pattern flag PR is the second logic, the polarity controller 72 outputs the horizontal polarity control signal HINV to the high logic H as shown in FIG. 12 to level the horizontal polarity of the data voltages output from the source drive IC. Control by two dot inversion (H2). The polarity control unit 72 may change the logic inversion period of the vertical polarity control signal POL differently with the change of the horizontal polarity control signal HINV according to the logic of the problem pattern flag PR.

8 is a circuit diagram showing in detail the problem pattern recognition unit 71 shown in FIG. 9 shows a sample flicker pattern of 8 pixels x 12 lines. FIG. 10A and FIG. 10B are diagrams showing an example of counts of RGB for the flicker pattern sample shown in FIG. 9.

8 to 10B, the problem pattern recognition unit 71 includes counters 81R, 81G, and 81B, problem pattern determination units 82R, 82G, and 82B, exception condition determination units 83R, 83G, and 83B; An OR gate 84, a NAND gate 85, and an AND gate 86 are provided.

The problem pattern recognition unit 71 extracts sample data having the same size (8 pixels x 12 lines) as shown in FIG. 9 from the input image data. The problem pattern recognition unit 71 counts the white-black pattern WB and the black-white pattern BW for each of the R (Red) data, the G (Green) data, and the B (Blue) data, and totals the counts. And thresholds. The threshold values are previously defined for each RGB according to the problem pattern type and stored in advance in the register of the problem pattern recognition unit 71.

The R counter 81R counts the number of the white-black pattern WB and the black-white pattern BW as shown in Figs. It inputs to the government 82R and R exception condition determination part 83R. The R problem pattern determination unit 82R compares the sum of the R counts of the white-black pattern WB and the black-white pattern BW input from the R counter 81R with threshold values defined according to the problem pattern type. If the sum of the R counts is equal to any of the thresholds, an output of high logic is generated. On the other hand, the R problem pattern determination unit 82R generates an output of the low logic if the sum of the R counts is not equal to any of the threshold values. The R exception condition determination unit 83R compares the sum of the R counts of the white-black pattern WB and the black-white pattern BW input from the R counter 81R with the R thresholds of the flicker pattern. The R exception condition determination unit 83R determines that the sum of the R counts of the white-black pattern WB and the black-white pattern BW input from the R counter 81R is equal to the R threshold values of the flicker pattern. The input image data is determined as a flicker pattern to generate a high logic output. The R exception condition determination unit 83R determines that the sum of the R counts of the white-black pattern WB and the black-white pattern BW input from the R counter 81R differs from the R thresholds of the flicker pattern. Generate the output of the logic.

The G counter 81G counts the number of each of the white-black pattern WB and the black-white pattern BW as shown in Figs. 10A and 10B with only the G data in the sample data, and adds the sum to the G problem pattern plate. It inputs to the government 82G and G exception condition determination part 83G. The G problem pattern determination unit 82G compares the total G counts of the white-black pattern WB and the black-white pattern BW input from the G counter 81G with thresholds defined according to the problem pattern type. If the sum of G counts is equal to any of the thresholds, an output of high logic is generated. On the other hand, the G problem pattern determination unit 82G generates the output of the low logic if the sum of the G counts is not equal to any of the threshold values. The G exception condition determination unit 83G compares the total G counts of the white-black pattern WB and the black-white pattern BW input from the G counter 81G with the G thresholds of the flicker pattern. The G exception condition determination unit 83G, if the total G count of each of the white-black pattern WB and the black-white pattern BW input from the G counter 81G is equal to the G thresholds of the flicker pattern, is presently present. The input image data is determined as a flicker pattern to generate a high logic output. The G exception condition determination unit 83G, if the total G count of each of the white-black pattern WB and the black-white pattern BW input from the G counter 81G is different from the G thresholds of the flicker pattern, is low. Generate the output of the logic.

The B counter 81B counts the number of the white-black pattern WB and the black-white pattern BW as shown in Figs. It inputs to the government 82B and B exception condition determination part 83B. The B problem pattern determination unit 82B compares the total B counts of the white-black pattern WB and the black-white pattern BW input from the B counter 81B with threshold values defined according to the problem pattern type. If the sum of B counts is equal to any of the thresholds, an output of high logic is generated. On the other hand, the B problem pattern determination unit 82B generates an output of the low logic if the sum of B counts is not equal to any of the threshold values. The B exception condition determination unit 83B compares the total B counts of the white-black pattern WB and the black-white pattern BW input from the B counter 81B with the B thresholds of the flicker pattern. If the total B counts of the white-black pattern WB and the black-white pattern BW input from the B counter 81B are equal to the B thresholds of the flicker pattern, the B exception condition determination unit 83B The input image data is determined as a flicker pattern to generate a high logic output. The B exception condition determination unit 83B determines that the sum of the B counts of the white-black pattern WB and the black-white pattern BW input from the B counter 81B is different from the B thresholds of the flicker pattern. Generate the output of the logic.

The R thresholds of the flicker pattern include a threshold '12' of the white-black pattern WB and a threshold '12' of the black-white pattern BW as shown in FIGS. 9 to 10B. Accordingly, the R exception condition determination units 83R generate an output of high logic when the total white-black (WB) count sum of the R data in the sample data is '12' and the total black-white count sum of the R data is '12'. do.

The G thresholds of the flicker pattern include a threshold '12' of the white-black pattern WB and a threshold '12' of the black-white pattern BW as shown in FIGS. 9 to 10B. Accordingly, the G exception condition determination units 83G generate an output of high logic when the total white-black (WB) count sum of the G data in the sample data is '12' and the total black-white count sum of the G data is '12'. do.

The B thresholds of the flicker pattern include a threshold '0' of the white-black pattern WB and a threshold '0' of the black-white pattern BW as shown in FIGS. 9 to 10B. Accordingly, the B exception condition determination units 83B generate a high logic output when the total white-black (WB) count of the B data in the sample data is '0' and the total black-white count of the B data is '0'. do.

The OR gate 84 performs an OR operation on the outputs of the problem pattern determination units 82R, 82G, and 82B and inputs the result to the AND gate 86. The OR gate 84 generates an output of high logic if any of the outputs of the problem pattern determination units 82R, 82G and 82B are high logic, while the outputs of the problem pattern determination units 82R, 82G and 82B are generated. The output of low logic occurs only when all are low logic.

The NAND gate 85 performs a negative AND operation on the outputs of the exception condition determination units 83R, 83G, and 83B and inputs the result to the AND gate 86. The NAND gate 85 generates a low logic output only when the outputs of all of the exception condition determination units 83R, 83G, and 83B are high logic, that is, a flicker pattern, and otherwise generates an output of high logic. do.

The AND gate 86 performs an AND operation on the output of the OR gate 84 and the outputs of the NAND gate 85, and outputs the result as the problem pattern flag PR. The AND gate 86 generates a problem pattern flag PR as a high logic when data of other types of problem patterns except the flicker pattern is input, and a problem pattern flag when data other than the flicker pattern or the problem pattern is input. (PR) occurs with low logic. Therefore, when the problem patterns other than the flicker pattern are input, the polarity control unit 72 controls the dot inversion to the horizontal two-dot inversion H2 as shown in FIG. 12, and normal data or problem patterns not defined as the problem pattern. An exception is to control the dot inversion to the horizontal 1 dot inversion H1 when the flicker pattern is input.

FIG. 11 is a diagram illustrating polarity bias and common voltage shift of data according to dot inversion in a flicker pattern. 12 is a diagram illustrating an example in which dot inversion is changed for various problem patterns.

11 and 12, the shutdown pattern is data in which pixel data of white gradation and pixel data of black gradation are alternated by one pixel unit. The smear pattern is data in which pixel data of white gradation and pixel data of black gradation are alternated in units of 2 pixels. In the flicker pattern, R data of the Nth pixel data and G data of the N + 1th pixel data are white grayscale data in the 4i (i is a positive integer) +1 line (LINE # 1, LINE # 5, LINE # 9). In the fourth i + 3 lines (LINE # 3, LINE # 7, LINE # 11), the G data of the Nth pixel data and the R data of the N + 1th pixel data are white grayscale data, and the remaining data are black grayscales. Data.

As described above, the present invention defines various types of problem patterns such as a shutdown pattern, a smear pattern, and a flicker pattern in advance, and when two other problem patterns except for the flicker pattern are input, a horizontal 2 dot in The liquid crystal display is driven by the version. In an exemplary embodiment of the present invention, when the flicker pattern is exceptionally input, the liquid crystal display is driven with a vertical 1 dot inversion to optimize the common voltage in the common voltage tuning process.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 and 2 illustrate examples of a problem pattern that may cause a common voltage shift.

3 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

4 through 6 are equivalent circuit diagrams illustrating various examples of the pixel array illustrated in FIG. 3.

FIG. 7 is a block diagram illustrating a problem pattern recognition and a polarity control part in the timing controller shown in FIG. 3.

FIG. 8 is a circuit diagram illustrating an exemplary embodiment of a problem pattern recognition unit illustrated in FIG. 7.

9 shows a sample flicker pattern of 8 pixels x 12 lines.

FIG. 10A and FIG. 10B are diagrams showing an example of counts of RGB for the flicker pattern sample shown in FIG. 9.

FIG. 11 is a diagram illustrating polarity bias and common voltage shift of data according to dot inversion in a flicker pattern.

12 is a diagram illustrating an example in which dot inversion is changed for various problem patterns.

Description of the Related Art

71: problem pattern recognition unit 72: polarity control unit

81R, 81G, 81B: Counter 82R, 82G, 82B: Problem pattern determination unit

83R, 83G, 83B: Exception condition determination unit 84: OR gate

85: NAND gate 86: AND gate

100: liquid crystal display panel 101: timing controller

102: data driving circuit 103: gate driving circuit

Claims (10)

A liquid crystal display panel in which data lines and gate lines cross each other; A data driving circuit converting digital video data into a positive / negative analog data voltage and outputting the digital video data to the data lines; A gate driving circuit sequentially supplying gate pulses synchronized with the data voltages to the gate lines; And When the digital video data of an input image is supplied to the data driving circuit, the operation timings of the data driving circuit and the gate driving circuit are controlled, and the data of the first problem pattern is input by analyzing the digital video data of the input image. The horizontal polarity of the data voltage output from the data driving circuit is controlled to a horizontal 2-dot inversion, and when the data of the second problem pattern is input, the horizontal polarity of the data voltage output from the data driving circuit is horizontal 1 And a timing controller for controlling the dot inversion. The method of claim 1, The timing controller, Stores the threshold values of RGB for each of the first and second problem patterns, counts the white-black pattern and the black-white pattern for each of the RGB data of the input image, and counts the sum totals of the predetermined thresholds for each RGB. And a first problem pattern and a second problem pattern. The method of claim 1, The timing controller, The data driving circuit using a horizontal polarity control signal for controlling the horizontal polarity of the data voltage output from the data driving circuit and a vertical polarity control signal for controlling the vertical polarity of the data voltage output from the data driving circuit; And a polarity of the data voltage output from the furnace. The method of claim 3, wherein The timing controller, And outputting the horizontal polarity control signal to the first logic when the data of the first problem pattern is input, and outputting the horizontal polarity control signal to the second logic when the data of the second problem pattern is input. Liquid crystal display device. The method of claim 4, wherein The timing controller, The sample data having a predetermined size is extracted from the input image, and the number of white-black patterns and black-white patterns is counted for each RGB of the sample data, and the sum totals of the RGB counts are compared with previously stored thresholds. A problem pattern recognition unit recognizing a problem pattern and a problem pattern type and outputting a problem pattern flag; And And a polarity control unit for inverting the logic of the horizontal polarity control signal when the logic value of the problem pattern flag is changed. The method of claim 5 The problem pattern recognition unit, An R counter for counting the number of each of the white-black pattern and the black-white pattern using only the R data in the sample data and outputting the sum totals; An R problem pattern plate which generates an output of high logic if the sum of the counts input from the R counters is compared with thresholds of the first and second problem patterns and the sum of R counts is equal to any one of the thresholds government; An R exception condition determination unit that outputs a high logic if the sum totals input from the R counters are equal to R thresholds of the second problem pattern; A G counter for counting the number of each of the white-black pattern and the black-white pattern by using only the G data in the sample data and outputting the sum totals; Comparing the count sums input from the G counter with thresholds of the first and second problem patterns, and if the sum of G counts is equal to any one of the thresholds, a G problem pattern plate generating an output of high logic government; A G exception condition determination unit that outputs a high logic if the sum totals inputted from the G counter are equal to the G threshold values of the second problem pattern; A B counter for counting the number of each of the white-black pattern and the black-white pattern by using only the B data in the sample data and outputting the sum totals; The B problem pattern plate which generates an output of high logic if the B count sum is equal to any one of the threshold values by comparing the sum totals input from the B counter with the threshold values of the first and second problem patterns. government; A B exception condition determination unit that outputs a high logic if the sum totals inputted from the B counter are the same as the B thresholds of the second problem pattern; An OR gate for ORing the outputs of the problem pattern determination units; A NAND gate performing an AND logic operation on the outputs of the exception condition determination units; And And an AND gate for performing an AND operation on the output of the OR gate and the outputs of the NAND gate, and outputting the result as the problem pattern flag. A liquid crystal display panel in which data lines and gate lines intersect, a data driving circuit converting digital video data into a positive / negative analog data voltage and outputting the same to the data lines, and a gate pulse synchronized with the data voltages. A driving method of a liquid crystal display device having a gate driving circuit for sequentially supplying gate lines, Analyzing the digital video data of the input image to determine a first problem pattern and a second problem pattern in the input image; Controlling the horizontal polarity of the data voltage output from the data driving circuit when the data of the first problem pattern is input to a horizontal two dot inversion; And And controlling the horizontal polarity of the data voltage output from the data driving circuit to a horizontal one dot inversion when data of the second problem pattern is input. The method of claim 7, wherein Analyzing the digital video data of the input image to determine a first problem pattern and a second problem pattern in the input image, Storing threshold values by RGB for each of the first and second problem patterns; Counting a white-black pattern and a black-white pattern for each of the RGB data of the input image, and comparing the count totals with a predetermined threshold for each RGB to distinguish the first and second problem patterns; A method of driving a liquid crystal display device, characterized in that. The method of claim 7, wherein Generating a horizontal polarity control signal for controlling the horizontal polarity of the data voltage output from the data driving circuit and a vertical polarity control signal for controlling the vertical polarity of the data voltage output from the data driving circuit. Liquid crystal display comprising a. The method of claim 9, Outputting the horizontal polarity control signal to first logic when data of the first problem pattern is input; And And outputting the horizontal polarity control signal to the second logic when the data of the second problem pattern is input.

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