KR20110025473A - Semiconductor device and method for forming using the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a forming method thereof are provided to prevent the deterioration of the semiconductor device by preventing the increase of the bit line parasitic cap. CONSTITUTION: A first interlayer insulating film and a second interlayer insulation film are formed on the semiconductor substrate. The second interlayer insulation film contains the porosity nitrogen. A landing plug(110) passes through the first and second interlayer insulation films, and it is planarized by the height of the second interlayer insulation film.

Description

Semiconductor device and method for forming using the same

The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device and a method of forming the semiconductor device to accurately overlap the storage electrode contact and the landing plug.

Most modern electronic appliances are equipped with semiconductor devices. The semiconductor device includes electronic elements such as transistors, resistors, and capacitors, which are designed to perform partial functions of the electronic products and then integrated on a semiconductor substrate. For example, electronic products such as a computer or a digital camera include semiconductor devices such as a memory chip for storing information and a processing chip for controlling information, and the memory chip and the processing chip are semiconductors. And the electronic components integrated on a substrate.

On the other hand, the semiconductor devices need to be increasingly integrated in order to meet the excellent performance and low price required by the consumer. As the degree of integration of semiconductor memory devices increases, design rules decrease, and the pattern of semiconductor devices becomes smaller. As miniaturization and high integration of a semiconductor device progresses, the overall chip area increases in proportion to an increase in memory capacity, but the area of a cell area where a semiconductor device pattern is formed is actually decreasing. Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell region, so that a fine pattern with a reduced critical dimension of the pattern must be formed.

A method of forming a fine pattern includes a method of using a phase shift mask as an exposure mask or a method of forming a separate thin film on the wafer to improve image contrast. a contrast enhancement layer (CEL) method, a tri layer resister (hereinafter referred to as a TLR) method having an intermediate layer such as spin on glass (SOG) between two layers of photoresist, or an upper side of the photoresist. Silicate methods for selectively injecting silicon have been developed to lower the resolution limit.

On the other hand, the contact connecting the upper and lower conductive wiring is significantly affected by the design rule compared to the line / space pattern. In other words, as the device becomes highly integrated, as the size of the device decreases and the distance between the peripheral wiring decreases, the aspect ratio, which is a ratio of the diameter and the depth of the contact, increases, thereby forming a contact. It is important in the method of forming the device. Therefore, in the highly integrated semiconductor device having a multi-layered conductive wiring, accurate and strict alignment between the masks is required in the contact forming process, so that the induction of process contribution is reduced or the process must be carried out without margin.

In particular, during the landing plug process, a self align contact fail (SAC Fail) of the landing plug and the gate or the landing plug and the recess gate is induced, thereby causing a problem of lowering the yield. Therefore, a technique for preventing self-alignment failure with the landing plug by changing from a gate or recess gate structure to a buried gate structure has been proposed. However, the buried gate structure also causes a problem in that the storage electrode contact and the bit line self-alignment failure are caused or the landing plug and the storage electrode contact are not connected.

1 is a cross-sectional view of a semiconductor device according to the prior art.

As shown in FIG. 1, a semiconductor device according to the related art includes an interlayer insulating layer 16 and a landing plug 18 formed on a semiconductor substrate 10 including an active region 14 defined as an isolation layer 12. A bit line contact 22 connected to the landing plug 18 and a bit line 24 connected to the bit line contact 22, a storage electrode contact 28 connected to the landing plug 18, and a sidewall thereof. It includes a spacer 30 provided in. However, in the process of forming the storage electrode contact 28, the interlayer insulating film 16 provided under the bit line is etched so that the storage electrode contact 28 is formed on the sidewall of the interlayer insulating film 16 as shown in 'A'. A problem arises. Since the storage electrode contact 28 is formed under the bit line, the parasitic cap of the bit line is increased to deteriorate the characteristics of the semiconductor device.

In order to prevent this phenomenon, a method of forming a thicker spacer 30 of the storage electrode contact 28 to fill the spacer 30 with the etched interlayer insulating layer 16 has been proposed. There is a limit to increase the resistance of the storage electrode contact 28 by reducing the voltage.

The present invention is to solve the problem that the landing plug and the storage electrode contact does not exactly overlap because the problem that the interlayer insulating film provided on the landing plug side wall is etched in the process of forming the storage electrode contact is connected to the landing plug. In addition, the storage electrode contact is formed to the bottom of the bit line to increase the parasitic cap of the bit line to solve the problem of deterioration of the characteristics of the semiconductor device.

The semiconductor device of the present invention includes an oxide-based first interlayer insulating film formed on a semiconductor substrate and an oxide-based second interlayer insulating film containing porous nitrogen, and through the first and second interlayer insulating films, And a landing plug flattened in height, a bit line connected to the landing plug, and a storage electrode contact connected to the landing plug.

The second interlayer insulating film has a thickness of 500 kPa to 1000 kPa.

The apparatus may further include a bit line spacer provided on sidewalls of the bit line.

The storage electrode contact spacer may further include a storage electrode contact spacer provided on the sidewall of the storage electrode contact.

The method of forming a semiconductor device of the present invention comprises the steps of forming a first interlayer insulating film and a second interlayer insulating film on a semiconductor substrate, penetrating the first and second interlayer insulating films, and landing height and planarization of the second interlayer insulating film. Forming a plug, forming a bit line connected to the landing plug, and forming a storage electrode contact connected to the landing plug.

The forming of the landing plug may include forming a photoresist pattern defining the landing plug on the second interlayer insulating layer and exposing the semiconductor substrate with the photoresist pattern as an etch mask. Etching and forming a conductive material for landing plug on the entire upper surface, and performing a planarization etching process on the conductive material for landing plug to expose the second interlayer insulating layer.

The method may further include, after forming the landing plug, forming a third interlayer insulating layer on the entire upper portion.

The forming of the bit line may include etching the third interlayer insulating layer to expose the landing plugs, forming a barrier metal layer, a bit line metal layer, and a hard mask layer on the entire surface, and forming the bit line on the hard mask layer. Forming a photoresist pattern defining a bit line, and etching the hard mask layer, the bit line metal layer, and the barrier metal layer by using the photoresist pattern as an etch mask.

The method may further include forming a bit line spacer on a sidewall of the bit line after the forming of the bit line.

The method may further include forming a fourth interlayer insulating film on the entire upper portion after the forming of the bit line.

The forming of the storage electrode contact may include forming a first storage electrode contact hole by etching a portion of the fourth interlayer insulating layer, and forming a first spacer on a sidewall of the first storage electrode contact hole. Etching the fourth interlayer insulating layer and the third interlayer insulating layer so that the landing plug is exposed by using a first spacer as an etch mask to form a second storage electrode contact hole, and performing a cleaning process on the second storage electrode contact hole Etching the fourth and third interlayer dielectric layers provided under the first spacer, forming a second spacer on the sidewalls of the first spacer and the third and fourth interlayer dielectric layers, Forming a conductive material for a storage electrode contact and flattening etching on the conductive material for the storage electrode contact to expose the fourth interlayer insulating layer In that it comprises the step of performing forward features.

The present invention solves the problem of etching the insulating film under the bit line during the formation of the storage electrode contact, thereby preventing the increase of the bit line parasitic cap, thereby providing an effect of preventing the deterioration of the semiconductor device.

Hereinafter, with reference to the accompanying drawings in accordance with an embodiment of the present invention will be described.

2 is a cross-sectional view illustrating a semiconductor device according to the present invention, and FIGS. 3A to 3I are cross-sectional views illustrating a method of forming a semiconductor device according to the present invention.

The semiconductor device according to the present invention illustrated in FIG. 2 is provided on the semiconductor substrate 100 and the interlayer insulating films 106 and 108 on the semiconductor substrate 100 including the active region 104 defined as the device isolation film 102. And a landing plug 110 planarized with a height of the interlayer insulating film 108 and a planarized landing plug 110, a bit line 116 connected to the landing plug 110, and a landing plug 110. The storage electrode contact 130 is included. In this case, the interlayer insulating film 108 is preferably an oxide film series containing porous nitrogen. This prevents the interlayer insulating films 108 from being etched together when the interlayer insulating films 122 and 112 are etched when the storage electrode contacts 130 are formed. Therefore, the storage electrode contact 130 is not formed below the bit line 116 so that the parasitic cap of the bit line is not increased to prevent deterioration of the semiconductor device.

As shown in FIG. 3A, interlayer insulating films 106 and 108 are formed on a semiconductor substrate 100 including an active region 104 defined as an isolation layer 102. Here, the interlayer insulating films 106 and 108 are preferably oxide films. In particular, the interlayer insulating film 108 preferably contains porous nitrogen, and the thickness thereof is preferably 500 kPa to 1000 kPa. The interlayer insulating layer 106 is preferably deposited to be greater than or equal to the height of the gate hard mask layer (not shown) so that the upper portion of the gate hard mask layer (not shown) is not lost in a process of forming a subsequent landing plug.

As shown in FIG. 3B, after the photoresist pattern (not shown) defining the landing plug hole is formed on the interlayer insulating layer 108, the active region 104 is exposed with the photoresist pattern (not shown) as an etch mask. The interlayer insulating films 108 and 106 may be etched to form landing plug holes (not shown). Next, the conductive material is formed on the entire top including the landing plug hole (not shown), and the landing plug 110 is formed by performing a planarization etching process to expose the interlayer insulating layer 108.

As shown in FIG. 3C, after the interlayer insulating film 112 is formed over the entire area including the landing plug 110, the interlayer insulating film 112 is etched to expose the landing plug 110, and the barrier is formed over the entire area. The metal layer 114, the bit line conductive layer 116, and the hard mask layer 118 are formed and then patterned to form bit lines. Then, the interlayer insulating film 122 is formed over the entirety.

As shown in FIGS. 3D and 3E, the interlayer insulating layer 122 is etched to form the storage electrode contact hole 124 (FIG. 3D). Here, the storage electrode contact hole 124 is preferably removed only a part of the interlayer insulating film 122 so that the interlayer insulating film 112 is not exposed. Next, after the nitride film is formed over the entire surface including the storage electrode contact hole 124, the spacer 126 is formed on the sidewall of the storage electrode contact hole 124 by performing etch back (FIG. 3E). Here, the spacer 126 is preferably a nitride film.

As shown in FIG. 3F, the interlayer insulating layers 122 and 112 are etched to expose the landing plug 110 using the spacer 126 as an etch mask to form the storage electrode contact hole 128. Here, the storage electrode contact hole 128 exposes not only the landing plug 110 but also the interlayer insulating film 108. However, since the interlayer insulating films 122 and 112 are oxide based, the interlayer insulating film 108 containing porous nitrogen may not be etched to prevent the interlayer insulating films 122 and 112 from being lost below the interlayer insulating film 108.

As shown in FIG. 3G, the interlayer insulating layers 122 and 112 under the spacer 126 are further etched by performing a cleaning process 130 to extend the lower portion of the storage electrode contact. In this process as well, the interlayer insulating film 108 having different components from those of the interlayer insulating films 122 and 112 may not be etched to prevent loss of the interlayer insulating film 108 under the interlayer insulating film 108.

As shown in FIG. 3H, the spacers 128 are formed in portions where the interlayer insulating layers 122 and 112 under the spacers 126 removed by the above-described cleaning process 130 are etched. Here, the spacer 128 serves as a barrier to prevent the storage electrode contact 130 formed in a subsequent process from being connected to the bit line.

As shown in FIG. 3I, after the conductive material for the storage electrode contact is formed over the entire surface, the storage electrode contact 130 is formed by performing a planarization process on the conductive material for the storage electrode contact to expose the interlayer insulating layer 122. do. At this time, the lower portion of the storage electrode contact 130 is not lost by the interlayer insulating layer 108, so that the parasitic cap of the bit line does not increase, thereby preventing deterioration of semiconductor device characteristics.

As described above, the present invention divides the storage electrode contact hole into primary etching and secondary etching, and performs a cleaning process to extend a lower portion of the storage electrode contact. In this case, the storage electrode contact hole is formed to expose the oxide film containing porous nitrogen, thereby preventing the storage electrode contact hole from being etched into the lower portion of the bit line, thereby preventing the parasitic cap of the bit line from increasing.

1 is a cross-sectional view of a semiconductor device according to the prior art.

2 is a cross-sectional view showing a semiconductor device according to the present invention.

3A to 3I are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Claims (11)

An oxide-based first interlayer insulating film formed on the semiconductor substrate and an oxide-based second interlayer insulating film containing porous nitrogen; A landing plug that penetrates the first and second interlayer insulating films and is flattened with a height of the second interlayer insulating film; A bit line connected to the landing plug; And And a storage electrode contact connected to the landing plug. The method according to claim 1, And the second interlayer insulating film has a thickness of 500 mW to 1000 mW. The method according to claim 1, And a bit line spacer provided on sidewalls of the bit line. The method according to claim 1, And a storage electrode contact spacer provided on sidewalls of the storage electrode contact. Forming an oxide based first interlayer insulating film and an oxide based second interlayer insulating film containing porous nitrogen on the semiconductor substrate; Forming a landing plug that penetrates the first and second interlayer insulating films and is flattened with the height of the second interlayer insulating film; Forming a bit line connected to the landing plug; And Forming a storage electrode contact connected to the landing plug. The method according to claim 5, Forming the landing plug is Forming a photoresist pattern defining the landing plug on the second interlayer insulating film; Etching the second and first interlayer insulating layers to expose the semiconductor substrate using the photoresist pattern as an etch mask; Forming a conductive material for the landing plug on the whole; And And a planarization etching process is performed on the conductive material for the landing plug so that the second interlayer insulating film is exposed. The method according to claim 5, After forming the landing plug And forming a third interlayer insulating film over the entire surface. The method of claim 7, Forming the bit line Etching the third interlayer insulating film to expose the landing plugs; Forming a barrier metal layer, a bit line metal layer, and a hard mask layer over the entirety; Forming a photoresist pattern defining a bit line on the hard mask layer; And Etching the hard mask layer, the bit line metal layer, and the barrier metal layer using the photoresist pattern as an etch mask. The method of claim 7, After forming the bit line And forming a bit line spacer on sidewalls of the bit line. The method of claim 7, After forming the bit line And forming a fourth interlayer insulating film over the entire surface. The method according to claim 9, Forming the storage electrode contact Etching a portion of the fourth interlayer insulating film to form a first storage electrode contact hole; Forming a first spacer on sidewalls of the first storage electrode contact hole; Etching the fourth interlayer insulating layer and the third interlayer insulating layer to expose the landing plugs using the first spacers as etch masks to form second storage electrode contact holes; Etching the fourth and third interlayer insulating layers under the first spacer by performing a cleaning process on the second storage electrode contact hole; Forming a second spacer under the first spacer and on sidewalls of the third and fourth interlayer insulating films; Forming a conductive material for a storage electrode contact thereon; And And forming a planar etching process on the conductive material for the storage electrode contact to expose the fourth interlayer insulating layer.

Images