KR20110018685A - Embedded substrate and method for manufacturing the same - Google Patents

Abstract

PURPOSE: An embedded substrate and the manufacturing method thereof in which the molding progress unnecessaries. CONSTITUTION: An embedded substrate(100) and manufacturing method thereof comprises a device entering to the base substrate and the empty space having inside the base substrate(110). The insulating layer in which the empty space in which device is inserted is filled and fixing device on the base inside substrate is made.

Description

Embedded substrate and method for manufacturing the same

The present invention relates to an embedded substrate and a method of manufacturing the same. More particularly, the present invention relates to an embedded substrate and a method for manufacturing the same, which can shorten wiring length and improve signal processing efficiency and component mounting efficiency. It is about.

The present invention is derived from research conducted as part of the Ministry of Knowledge Economy's industrial technology development project.

[Task control number: 10031768, Assignment name: R2R laminated molding, plating interconnection manufacturing and reliability evaluation technology]

Recently, electronic products have entered the era of multifunctional integration using ubiquitous computing such as mobile phones or various information technology (IT) mobile devices. As the electronic device evolves, it is an information transmission medium that delivers various information to humans anytime, anywhere. It is strong against external shocks and needs easy portability. To this end, there is a need for a device embedded substrate including various devices such as semiconductor chips therein.

On the other hand, in the semiconductor packaging technology, the development of three-dimensional stacking technology is progressing in response to customer demand for higher functionality, higher speed of signal processing, smaller size, smaller size, and improved package performance. The 3D multilayer mounting technology is a high-density, high-speed mounting technology of a system that shortens the wiring length between components and increases the mounting area of mounting components, as compared to the conventional two-dimensional mounting technique of planarization. Of course, the efficiency of the mounting component per unit area of the substrate can be improved. In addition, due to the miniaturization, it is possible to miniaturize the system and to lower the power, which is a necessary technology for implementing the next generation micro system.

In a conventional method for manufacturing a device embedded substrate, after forming a cavity in a core substrate, an adhesive tape is laminated on the entire surface of the substrate in order to bond the device inside the void space. The device is then bonded. After that, the adhesive tape is removed and the surface is cleaned by plasma.

In this case, it is not easy to remove the adhesive tape and the residue of the adhesive tape and the adhesive component of the adhesive tape are not easily removed by plasma treatment, which may adversely affect the defect and reliability of the product. In addition, during the removal of the adhesive tape or the plasma cleaning process, the bonding pad portion of the device may be damaged or contaminated. This may cause a defect in the conducting process of the device and the substrate.

In addition, after bonding the device to the adhesive layer, the empty space is filled with the molding material and the curing process is performed. At this time, it is difficult to precisely control the amount of molding material and the molding height, and there is a problem that a step may occur due to a heat shrinkage phenomenon during the curing process of the molding material. Such a step may cause fine peeling and reduction of wiring strength when forming back wirings, which may cause pattern peeling.

The present invention provides a built-in substrate and a method of manufacturing the same, which does not require an additional molding process of the empty space inside the substrate by bonding the empty space formed inside the empty space formed inside the substrate. For the purpose of

The present invention, a base substrate; A device mounted in an empty space provided in the base substrate; And an insulating layer filling the empty space in which the device is mounted to fix the device inside the base substrate, wherein the insulating layer comprises a die adhesive film.

One side of the device and a portion of the insulating layer surrounding the device are exposed to one side of the base substrate, and disposed on one side of the base substrate to contact one side of the exposed device and a portion of the insulating layer. A protective layer may be further provided.

A first circuit pattern which is a conductive pattern disposed on the protective layer may be further provided.

The display device may further include a connection terminal penetrating the protective layer to electrically connect the first circuit pattern and the device.

The adhesive film having the insulating layer disposed between the device and the base substrate may be formed by filling the empty space by heating and pressing.

The base substrate being disposed on a core substrate, a conductive first conductive layer disposed on one surface of the core substrate to be in contact with the protective layer, and disposed on the other surface of the core substrate to support the device through the insulating layer. 2 conductive layers can be provided.

A first adhesive layer interposed between the core substrate and the first conductive layer and a second adhesive layer interposed between the core substrate and the second conductive layer may be further provided.

A second circuit pattern, which is a conductive pattern disposed on the other surface of the surface on which the protective layer is disposed, of the base substrate; a connecting portion connecting the first circuit pattern and the second circuit pattern through the base substrate; A first protective layer may surround at least a portion of the first circuit pattern, and a second protective layer may surround at least a portion of the second circuit pattern.

An interval between the protective layer and the second conductive layer may be substantially constant.

The die adhesive film may include polyamic acid ester and one or more compounds of dianhydride, diamine, tetraamine, and siloxane compound.

Another aspect of the invention, the step of preparing a base substrate having an empty space therein from one side; Mounting the device in an empty space provided in the base substrate; Depositing a protective layer over the device mounted with the base substrate; Forming a first circuit pattern on the protective layer; And forming a first passivation layer on the first circuit pattern, wherein the die adhesive film fills the empty space by thermocompression bonding while the device is bonded inside the base substrate by a die adhesive film. Provided is a method of manufacturing an embedded substrate for forming an insulating layer.

The preparing of the base substrate may include stacking a conductive first conductive layer in contact with the protective layer on one surface of a core substrate, forming the empty space in the first conductive layer and the core substrate, and Laminating a conductive second conductive layer on the other surface of the core substrate.

The preparing of the base substrate may further include applying a first adhesive layer and a second adhesive layer to both surfaces of the core substrate before stacking the first conductive layer.

Forming a connection terminal through the protective layer to electrically connect the first circuit pattern and the device, forming a through hole penetrating the base substrate and the protective layer, and forming the through hole in a conductive material. The method may further include forming a third conductive layer on the protective layer.

When the third conductive layer is formed, a fourth conductive layer is formed on the second conductive layer, and the second circuit pattern is formed together from the fourth conductive layer while forming the first circuit pattern from the third conductive layer. When the first protective layer is formed, a second protective layer may be formed on the second circuit pattern.

The forming of the connection terminal may include forming a via hole penetrating the protective layer by a lithography process, wherein the connection terminal forms the via hole in the third conductive layer. It can be formed to fill.

An interval between the protective layer and the second conductive layer may be substantially constant.

The die adhesive film may include polyamic acid ester and one or more compounds of dianhydride, diamine, tetraamine, and siloxane compound.

According to the embedded substrate and the method for manufacturing the same according to the present invention, a device is bonded to an empty space formed inside the substrate to fill the empty space, thereby eliminating the need for an additional molding process of the empty space inside the substrate. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

10 is a schematic cross-sectional view of the embedded substrate 100 as a preferred embodiment according to the present invention.

Referring to the drawings, the embedded substrate 100 according to the present invention includes a base substrate 110; Device 120; And an insulating layer 130.

An empty space 130a is provided inside the base substrate 110 to allow the device to be mounted. The device 120 is mounted in the empty space 130a provided in the base substrate 110.

The insulating layer 130 is an insulating layer filling the empty space 130a in which the device 120 is mounted to fix the device 120 to the inside of the base substrate 110. In this case, the insulating layer 130 includes a die attach film (DAF).

That is, the device 120 is attached to one surface of the inside of the base substrate 110 by a die adhesive film, and the die adhesive film disposed between the device 120 and the base substrate 110 is empty by heating and pressing. The insulating layer 130 is formed by filling the 130a.

At this time, when the appropriate heat and pressure is applied to the die-bonding film, the flow (flow) characteristics are generated, and the resin flow (resin flow) characteristics are used to fill the empty space 130a.

Thus, there is no fear that the bonding pads of the device will be contaminated or damaged and no further plasma cleaning process is required. In addition, a separate cure process and equipment for curing the molding epoxy is not required, thereby reducing manufacturing costs.

In addition, the active side of the device is directed upward, it is possible to reduce the product defects caused by the step in the process for forming a conductive layer. In addition, device bonding and empty space filling time can be reduced. In addition, heat dissipation characteristics of the device 120 embedded in the substrate can be improved by adding a component having excellent thermal conductivity such as silica to the material of the die-bonding film.

In addition, since the embedded substrate according to the present invention can be implemented in a roll-to-roll manner, mass production is facilitated.

On the other hand, in general, polymer materials having heat stability at high temperature have a disadvantage in that high temperature flowability is not good, and conversely, meltable polyimide having good high temperature flowability has a problem in that heat resistance is poor.

Therefore, the die-bonding film in the present invention is a polyamic acid ester, dianhydride, diamine, tetraamine, and so as to have appropriate high temperature flowability, high temperature adhesion, and heat resistance in the device bonding process. It may comprise one or more compounds of the siloxane compound.

At this time, the mole fraction of each component of the die adhesive film can be freely controlled and polymerized within the range of 3 to 70%. Through the combination of the compounds it is possible to ensure a high temperature flow while having a high glass transition temperature and heat resistance characteristics.

In this case, the device bonding conditions may be differently applied depending on the material properties according to the mole fraction of the composition compound of the die adhesive film, the temperature conditions when using the die adhesive film in the present invention is 150 ~ 200 ℃, preferably 170 ~ 180 ℃. The pressure conditions are 1 to 6 kgf, preferably 1 to 3 kgf. However, these temperature conditions and pressure conditions can be variously operated at appropriate conditions depending on the difference in physical properties according to the compound composition of the die-bonding film to be used.

On the other hand, the hole size of the empty space inside the substrate to be processed largely depends on the degree of alignment of the device bonding equipment, which is generally ± 5um. At this time, assuming that the maximum device thickness is 50um in consideration of flexibility (flexibility), and if there is a change in device size, the thickness increase rate of the die adhesive film is almost insignificant. For example, when the device size is 5x5mm, 2x2mm, 1x1mm, since the thickness of the die adhesive film needs to be increased by about 0.04, 0.25, 1um, the resin flow properties are more important than the thickness of the die adhesive film.

The device 120 may be a semiconductor device or an active and / or passive electrical and electronic device included in the base substrate 110.

The base substrate 110 may include a core substrate 111, a first conductive layer 112, and a second conductive layer 113. The first conductive layer 112 is a conductive layer disposed on one surface of the core substrate 111, for example, on the upper surface of the drawing to contact the protective layer 140. The second conductive layer 113 is disposed on another surface of the core substrate 111, for example, the lower surface of the drawing, and supports the device through the insulating layer 130.

In addition, the base substrate 110 may further include a first adhesive layer 114 and a second adhesive layer 115. The first adhesive layer 114 may be interposed between the core substrate 111 and the first conductive layer 112 to attach and stack the first conductive layer 112 to the core substrate 111. The second adhesive layer 115 may be interposed between the core substrate 111 and the second conductive layer 113 to attach and stack the second conductive layer 113 to the core substrate 111.

Core substrate 111 A conventional resin substrate such as PI (Polyimide) is applied, and the conductive layers 112 and 113 may be attached to and laminated on the core substrate 111 by the adhesive layers 114 and 115, but the present invention The present invention is not limited thereto, and a conductive layer may be directly stacked on the core substrate by applying a prepreg or the like without a separate adhesive layer.

Meanwhile, the embedded substrate 110 according to the present invention may further include a protective layer 140, a first circuit pattern 150, a connection terminal 160, and a first protective layer 191.

One surface of the device 120 and a portion of the insulating layer 130 surrounding the device 120 may be exposed on one surface of the base substrate 110, for example, the upper surface of the drawing. In this case, the protective layer 140 may be disposed on one surface of the base substrate, and may be in contact with one surface of the exposed device 120 and a portion of the insulating layer 130. The protective layer 140 protects the exposed surfaces of the base substrate 110 and the device 120, and may be a photo film resist (PFR) or a dry film solder resist (DFSR).

The first circuit pattern 150 is a conductive circuit pattern disposed on the protective layer 140. According to the present invention, the insulating layer 130 is formed by the die adhesive film, so that the gap between the protective layer 140 and the second conductive layer 1130 of the base substrate 110 can be maintained substantially constant. Accordingly, in the process of forming the first circuit pattern 150, it is possible to reduce the product defects caused by the step difference.

Meanwhile, the connection terminal 160 may electrically connect the first circuit pattern 150 and the device 120 through the protective layer 140. In this case, the connection terminal 160 may electrically connect the first circuit pattern 150 and the bonding pad of the device 120.

To this end, a via hole 160a may be formed in the passivation layer 140, and the connecting terminal 160 may be formed by filling the via hole 160a with a conductive material by electroless plating and electrolytic plating. In this case, the via hole 160a may be formed by a PFR (Phot Film Resist) lithography process. Conventionally, via holes are processed by laser drilling to limit their shape and pitch.

However, in the case of using the PFR lithography process according to the present invention, by adjusting the light intensity, the via hole can be processed into various shapes of via holes larger than, equal to, or smaller than the ends thereof, and fine pitch can be realized. .

The first passivation layer 191 surrounds at least a portion of the first circuit pattern 150. The first passivation layer 191 may be used to protect the first circuit pattern 150, and a photo solder resist (PSR) may be applied.

The first passivation layer 191 may be formed on an area excluding the connection terminal area of the first circuit pattern 150. The third passivation layer 193 may be formed on the connection terminal region of the first circuit pattern 150. The third protective layer 193 is to protect the connection terminal region of the first circuit pattern 150, and may be formed by finish plating, for example, electroless substitution plating (ENIG).

In addition, the embedded substrate according to the present invention may include the second circuit pattern 170, the connection unit 180, and the second protective layer 192.

The second circuit pattern 170 is a conductive circuit pattern disposed on another surface of the surface on which the protective layer 140 of the base substrate 110 is disposed, for example, the lower surface of the drawing. The second circuit pattern 170 may be formed together when the first circuit pattern 150 is formed.

The connector 180 penetrates the base substrate 110 to connect the first circuit pattern 150 and the second circuit pattern 170. The connection part 180 may be formed in the through-hole 180a formed through the protective layer 140 and the base substrate 110 by plating, electroless plating, or electrolytic plating.

At this time, the conductive layer may be formed during the plating electroless and electrolytic plating for forming the connection portion. The first circuit pattern 150 and the second circuit pattern 170 may be formed by a conventional pattern lithography process for the conductive layer.

The second protective layer 192 surrounds at least a portion of the second circuit pattern 170. The second passivation layer 192 may be formed on a region other than the connection terminal region of the second circuit pattern 170. The fourth passivation layer 194 may be formed on the connection terminal region of the second circuit pattern 170. The fourth protective layer 194 is to protect the connection terminal region of the second circuit pattern 170, and may be formed by finish plating, for example, electroless substitution plating (ENIG).

Meanwhile, the first conductive layer 112 may be omitted. However, by providing the first conductive layer 112, an effect of easily implementing the first circuit pattern 150 may be obtained. That is, when the first conductive layer 112 and the first circuit pattern 150 are used at the same time, the available area for designing the circuit is almost doubled compared to the case where only the first circuit pattern 150 is provided. The degree of freedom in designing circuits, such as the arrangement of via holes, can be increased. In addition, the necessity of fabricating a complicated circuit with a high degree of integration in a small area is reduced, which makes it possible to avoid difficult fine circuit fabrication.

However, this requires a lithography and etching process to circuit the first conductive layer 112 after the step of FIG. 5. Therefore, in a product which must increase the degree of freedom in circuit design and avoid the manufacture of fine circuits, the circuit is formed with the first conductive layer 112 even if the number of processes is increased. Otherwise, the first conductive layer 112 is excluded. It is appropriate.

Here, when the first conductive layer 112 is provided, the internal heat accumulated in the substrate due to the device embedded structure is transferred to the first conductive layer 112 and the first conductive layer 112 and the via hole. An effect emitted to the outside through the connected first circuit pattern 150 may also be obtained.

On the other hand, since the second conductive layer 113 is located on the rear surface of the device 120, the second conductive layer 113 may function to improve heat dissipation, which is a weak characteristic of the device embedded substrate. In addition, the second circuit pattern 170 is preferably formed as large as possible to perform the heat radiation function. In this case, the second conductive layer 113 is preferably formed integrally with the second circuit pattern 170.

According to the present invention, by filling the empty space while the device is bonded inside the empty space formed inside the substrate, there is no need for a molding process of the empty space inside the substrate.

1 to 10 are diagrams for explaining a method of manufacturing an embedded substrate, which is a preferred embodiment of the present invention, and vertical cross-sectional views of manufacturing steps according to a manufacturing process are shown.

The method of manufacturing the embedded substrate according to the present invention (FIGS. 1 to 10) is a method of manufacturing the embedded substrate 100 illustrated in FIG. 10, the same as in the description of the embedded substrate 100 illustrated in FIG. 10. This may be referred to and a detailed description may be omitted.

Referring to the drawings, a method of manufacturing an embedded substrate according to the present invention (FIGS. 1 to 10) includes a base substrate preparing step (FIGS. 1 to 3); Device mounting step (FIGS. 4 and 5); Protective layer stacking step (FIG. 6); A first pattern forming step (FIGS. 8 and 9); And a first protective layer forming step (FIG. 10).

In the base substrate preparation step (FIGS. 1 to 3), a base substrate 110a having an empty space 130a formed therein is prepared from one surface thereof. In the device mounting step (FIGS. 4 and 5), the device 120 is mounted in an empty space 130a provided in the base substrate 110a.

In the protective layer stacking step (FIG. 6), the protective layer 140a is stacked on the base substrate 110a and the device 120 mounted therein. In the first pattern forming step (FIGS. 8 and 9), the first circuit pattern 150 is formed on the passivation layer 140a. In the first protective layer forming step (FIG. 10), a first protective layer 191 is formed on the first circuit pattern 150.

At this time, in the manufacturing method of the embedded substrate according to the present invention (Figs. 1 to 10) in the device mounting step (Figs. 4 and 5) the device 120 by the die adhesive film (130a) inside the base substrate (110a) While bonding to the die adhesive film 130a fills the empty space 130a by thermocompression bonding to form the insulating layer 130.

At this time, when the appropriate heat and pressure is applied to the die-bonding film, the flow (flow) characteristics are generated, and the resin flow (resin flow) characteristics are used to fill the empty space 130a.

Thus, there is no fear that the bonding pads of the device will be contaminated or damaged and no further plasma cleaning process is required. In addition, a separate cure process and equipment for curing the molding epoxy is not required, thereby reducing manufacturing costs.

In addition, the active side of the device is directed upward, it is possible to reduce product defects due to the step difference in the process for forming a conductive layer. In addition, device bonding and empty space filling time can be reduced. In addition, heat dissipation characteristics of the device 120 embedded in the substrate can be improved by adding a component having excellent thermal conductivity such as silica to the material of the die-bonding film.

In addition, since the embedded substrate according to the present invention can be implemented in a roll-to-roll manner, mass production is facilitated.

On the other hand, in general, polymer materials having heat stability at high temperature have a disadvantage in that high temperature flowability is not good, and conversely, meltable polyimide having good high temperature flowability has a problem in that heat resistance is poor.

Therefore, the die-bonding film in the present invention is a polyamic acid ester, dianhydride, diamine, tetraamine, and so as to have appropriate high temperature flowability, high temperature adhesion, and heat resistance in the device bonding process. It may comprise one or more compounds of the siloxane compound.

At this time, the mole fraction of each component of the die adhesive film can be freely controlled and polymerized within the range of 3 to 70%. Through the combination of the compounds it is possible to ensure a high temperature flow while having a high glass transition temperature and heat resistance characteristics.

In this case, the device bonding conditions may be differently applied depending on the material properties according to the mole fraction of the composition compound of the die adhesive film, the temperature conditions when using the die adhesive film in the present invention is 150 ~ 200 ℃, preferably 170 ~ 180 ℃. The pressure conditions are 1 to 6 kgf, preferably 1 to 3 kgf. However, such temperature conditions and pressure conditions can be variously operated under appropriate conditions depending on the difference in physical properties according to the compound composition of the die-bonding film to be used.

On the other hand, the hole size of the empty space inside the substrate to be processed largely depends on the degree of alignment of the device bonding equipment, which is generally ± 5um. At this time, assuming that the maximum device thickness is 50um in consideration of flexibility (flexibility), and if there is a change in device size, the thickness increase rate of the die adhesive film is almost insignificant. For example, when the device size is 5x5mm, 2x2mm, 1x1mm, since the thickness of the die adhesive film needs to be increased by about 0.04, 0.25, 1um, the resin flow properties are more important than the thickness of the die adhesive film.

In the base substrate preparation step (FIGS. 1 to 3), a base substrate 110a having an empty space 130a formed therein is prepared from one surface thereof. The base substrate preparing step (FIGS. 1 to 3) may include a first conductive layer stacking step (FIG. 1), an empty space forming step (FIG. 2), and a second conductive layer stacking step (FIG. 3).

In the first conductive layer stacking step (FIG. 1), the conductive first conductive layer 112a in contact with the protective layer 140a is stacked on one surface of the core substrate 111a. In the empty space forming step (FIG. 2), the empty space 130a is formed in the first conductive layer 112a and the core substrate 111a. In the second conductive layer stacking step (FIG. 3), the conductive second conductive layer 113a is stacked on the other surface of the core substrate 111b in which the empty space 130a is formed.

At this time, the base substrate preparation step (FIGS. 1 to 3) is a step of applying the first adhesive layer 114a and the second adhesive layer 115a on both surfaces of the core substrate 111a before the first conductive layer 112a is laminated. It may be provided with more. In this case, the first adhesive layer 114a may be applied, the first conductive layer 112a may be stacked, and the second adhesive layer 115a may be applied.

Core substrate 111 A conventional resin substrate such as polyimide (PI) is applied, and the conductive layers 112a and 113a may be attached to and laminated on the core substrate 111 by the adhesive layers 114a and 115b. The present invention is not limited thereto, and a conductive layer may be directly stacked on the core substrate by applying a prepreg or the like without a separate adhesive layer.

In the protective layer stacking step (FIG. 6), the protective layer 140a is stacked on the base substrate 110a and the device 120 mounted therein. In this case, the via hole 160a may be formed in the passivation layer 140a by passing through the passivation layer 140a.

One surface of the device 120 and a portion of the insulating layer 130 surrounding the device 120 may be exposed on one surface of the base substrate 110a, for example, the upper surface of the drawing, and the protective layer 140 may include the base substrate ( In order to protect the exposed surface of the device 110a and the device 120, a photo film resist (PFR) or a dry film solder resist (DFSR) may be applied.

In this case, the via hole 160a may be formed by a PFR (Phot Film Resist) lithography process. Conventionally, via holes are processed by laser drilling to limit their shape and pitch.

However, in the case of using the PFR lithography process according to the present invention, as the light intensity is adjusted, via holes of various shapes larger or equal to or smaller than the ends may be processed, and fine pitch may be realized.

The method of manufacturing the embedded substrate (FIGS. 1 to 10) may further include a through hole forming step (FIG. 7). In the through hole forming step (FIG. 7), a through hole 180a penetrating the base substrate 110a and the protective layer 140a may be formed. The connection part 180 may be formed to electrically connect the upper and lower surfaces of the base substrate 110a through the through hole 180a.

The connector 180 penetrates the base substrate 110 to connect the first circuit pattern 150 and the second circuit pattern 170. The connection part 180 may be formed in the through-hole 180a formed through the protective layer 140 and the base substrate 110 by plating, electroless plating, or electrolytic plating. At this time, the via hole 160a may be filled with a conductive material by electroless and electrolytic plating to form the connection terminal 160 together.

Meanwhile, the connection terminal 160 may electrically connect the first circuit pattern 150 and the device 120 through the protective layer 140. In this case, the connection terminal 160 may electrically connect the first circuit pattern 150 and the bonding pad of the device 120.

In this case, the conductive layers 150a and 170a may be formed during plating electroless and electrolytic plating for forming the connection unit 180. The first circuit pattern 150 and the second circuit pattern 170 may be formed by a conventional pattern lithography process for the conductive layers 150a and 170a, respectively.

In the first pattern forming step (FIGS. 8 and 9), the first circuit pattern 150 is formed on the passivation layer 140a. In the first pattern forming step (FIGS. 8 and 9), first, the connection part 180 and the third conductive layer 150a formed through the through hole 180a are formed (FIG. 8), and the third conductive layer 150a is formed. The first circuit pattern 150 may be formed by a conventional pattern lithography process for.

The first circuit pattern 150 is a conductive circuit pattern disposed on the protective layer 140. According to the present invention, the insulating layer 130 is formed by the die adhesive film, so that the gap between the protective layer 140 and the second conductive layer 1130 of the base substrate 110 can be maintained substantially constant. Accordingly, in the process of forming the first circuit pattern 150, it is possible to reduce the product defects caused by the step difference.

In the first protective layer forming step (FIG. 10), a first protective layer 191 is formed on the first circuit pattern 150. The first passivation layer 191 may be formed to surround at least a portion of the first circuit pattern 150. The first passivation layer 191 may be used to protect the first circuit pattern 150, and a photo solder resist (PSR) may be applied.

The first passivation layer 191 may be formed on an area excluding the connection terminal area of the first circuit pattern 150. The third passivation layer 193 may be formed on the connection terminal region of the first circuit pattern 150. The third protective layer 193 is to protect the connection terminal region of the first circuit pattern 150, and may be formed by finish plating, for example, electroless substitution plating (ENIG).

Meanwhile, when the third conductive layer 150a is formed, for example, a fourth conductive layer 170a may be formed on the lower surface of the drawing. In this case, the second circuit pattern 170 may be formed together from the fourth conductive layer 170a while the first circuit pattern 150 is formed from the third conductive layer 150a. In addition, when the first passivation layer 191 is formed, for example, the second passivation layer 192 may be formed on the lower surface of the drawing on the second circuit pattern 170.

The second protective layer 192 surrounds at least a portion of the second circuit pattern 170. The second passivation layer 192 may be formed on a region other than the connection terminal region of the second circuit pattern 170. The fourth passivation layer 194 may be formed on the connection terminal region of the second circuit pattern 170. The fourth protective layer 194 is to protect the connection terminal region of the second circuit pattern 170, and may be formed by finish plating, for example, electroless substitution plating (ENIG).

Meanwhile, the first conductive layer 112 may be omitted. However, by providing the first conductive layer 112, an effect of easily implementing the first circuit pattern 150 may be obtained. That is, when the first conductive layer 112 and the first circuit pattern 150 are used at the same time, the available area for designing the circuit is almost doubled compared to the case where only the first circuit pattern 150 is provided. The degree of freedom in designing circuits, such as the arrangement of via holes, can be increased. In addition, the necessity of fabricating a complicated circuit with a high degree of integration in a small area is reduced, which makes it possible to avoid difficult fine circuit fabrication.

However, this requires a lithography and etching process to circuit the first conductive layer 112 after the step of FIG. 5. Therefore, in a product which must increase the degree of freedom in circuit design and avoid the manufacture of fine circuits, the circuit is formed with the first conductive layer 112 even if the number of processes is increased. Otherwise, the first conductive layer 112 is excluded. It is appropriate.

Here, when the first conductive layer 112 is provided, the internal heat accumulated in the substrate due to the device embedded structure is transferred to the first conductive layer 112 and the first conductive layer 112 and the via hole. An effect emitted to the outside through the connected first circuit pattern 150 may also be obtained.

On the other hand, since the second conductive layer 113 is located on the rear surface of the device 120, the second conductive layer 113 may function to improve heat dissipation, which is a weak characteristic of the device embedded substrate. In addition, the second circuit pattern 170 is preferably formed as large as possible to perform the heat radiation function. In this case, the second conductive layer 113 is preferably formed integrally with the second circuit pattern 170.

According to the present invention, by filling the empty space while the device is bonded inside the empty space formed inside the substrate, there is no need for a molding process of the empty space inside the substrate.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, it is merely an example, and those skilled in the art may realize various modifications and equivalent other embodiments therefrom. I can understand. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

1 to 10 are views for explaining a method of manufacturing an embedded substrate as a preferred embodiment according to the present invention, and are vertical cross-sectional views of manufacturing steps according to a manufacturing process.

10 is a cross-sectional view schematically showing an embedded substrate as a preferred embodiment according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100: embedded substrate, 110: base substrate,

120: device, 130: insulating layer,

140: protective layer, 150: first circuit pattern,

170: second circuit pattern.

Claims (18)

A base substrate; A device mounted in an empty space provided in the base substrate; And An insulating layer filling the empty space in which the device is mounted and fixing the device inside the base substrate, Embedded substrate, wherein the insulating layer comprises a die adhesive film. The method of claim 1, One side of the device and a portion of the insulating layer surrounding the device are exposed on one side of the base substrate, And a protective layer disposed on one surface of the base substrate to be in contact with one surface of the exposed device and part of the insulating layer. The method of claim 2, The embedded substrate further comprises a first circuit pattern which is a conductive pattern disposed on the protective layer. The method of claim 3, And a connection terminal penetrating the protective layer to electrically connect the first circuit pattern and the device. The method of claim 2, And the die adhesive film having the insulating layer disposed between the device and the base substrate filling the empty space by heating and pressing. The method of claim 2, The base substrate, Core substrate, A conductive first conductive layer disposed on one surface of the core substrate and in contact with the protective layer, and And a second conductive layer disposed on the other surface of the core substrate to support the device through the insulating layer. The method of claim 6, A first adhesive layer interposed between the core substrate and the first conductive layer, and And a second adhesive layer interposed between the core substrate and the second conductive layer. The method of claim 3, A second circuit pattern which is a conductive pattern disposed on the other surface of the surface on which the protective layer of the base substrate is disposed; A connection part connecting the first circuit pattern and the second circuit pattern through the base substrate; A first protective layer surrounding at least a portion of the first circuit pattern, and An embedded substrate having a second protective layer surrounding at least a portion of the second circuit pattern. The method of claim 6, An embedded substrate having a substantially constant gap between the protective layer and the second conductive layer. The method of claim 1, The die attach film comprises a polyamic acid ester, a dianhydride, a diamine, a tetraamine, and a siloxane compound. Preparing a base substrate having an empty space formed therein from one surface; Mounting the device in an empty space provided in the base substrate; Depositing a protective layer over the device mounted with the base substrate; Forming a first circuit pattern on the protective layer; And Forming a first passivation layer on the first circuit pattern; And the device is bonded to the inside of the base substrate by a die adhesive film, wherein the die adhesive film fills the empty space by thermal compression to form an insulating layer. The method of claim 11, Preparing the base substrate, Stacking a conductive first conductive layer in contact with the protective layer on one surface of a core substrate, Forming the empty space in the first conductive layer and the core substrate, and Stacking a conductive second conductive layer on the other surface of the core substrate. The method of claim 12, Preparing the base substrate, And applying the first adhesive layer and the second adhesive layer to both surfaces of the core substrate before stacking the first conductive layer, respectively. The method of claim 12, Forming a connection terminal penetrating the protective layer to electrically connect the first circuit pattern and the device; Forming a through hole penetrating the base substrate and the protective layer, and Filling the through-hole with a conductive material and forming a third conductive layer on the protective layer. The method of claim 14, At the time of forming the third conductive layer, a fourth conductive layer is formed on the second conductive layer, The second circuit pattern is formed together from the fourth conductive layer while the first circuit pattern is formed from the third conductive layer. And forming a second protective layer over the second circuit pattern when the first protective layer is formed. The method of claim 15, Forming the connection terminal comprises forming a via hole penetrating the protective layer by a lithography process, And the connection terminal fills the via hole with a conductive material when the third conductive layer is formed. The method of claim 12, The method of manufacturing the embedded substrate having a substantially constant gap between the protective layer and the second conductive layer. The method of claim 1, The die adhesive film comprises a polyamic acid ester and a dianhydride, a diamine, a tetraamine, and a compound of one or more of siloxane compounds.

Images