KR20110010536A - Array substrate and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate and a method for fabricating the same are provided to prevent the formation of a thermal oxidation layer on an active layer. CONSTITUTION: A gate wiring(145) contacts a gate electrode through a gate contact hole at the boundary area of a pixel region over a first passivation layer. The gate wiring crosses a data wiring. A second protection layer(150) has a drain contact hole which exposes a drain electrode over the gate wiring. A pixel electrode(170) contacts the drain electrode through the drain contact hole over the second protection layer. The pixel electrode is formed at the pixel region.

Description

Array substrate and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate. In particular, active damage of the surface of the active layer is fundamentally suppressed by dry etching, and furthermore, thermal active film formation is prevented on the surface of the active layer during the crystallization process, and the mobility is excellent. The present invention relates to a thin film transistor array substrate having a layer and a method of manufacturing the same.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of adjusting the on / off voltage of each pixel, has a resolution and a moving picture. Its outstanding implementation ability attracts the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of DC 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which is essentially a switching element, is provided to remove each pixel area on / off.

FIG. 1 is a cross-sectional view of a pixel area including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting display device.

As illustrated, the gate electrode 15 is disposed in the switching region TrA in the plurality of pixel regions P defined by the plurality of gate lines (not shown) and the data lines 33 intersecting on the array substrate 11. Is formed, and a gate insulating film 18 is formed on the entire surface of the gate electrode 15. The active layer 22 of pure amorphous silicon and the ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon. The configured semiconductor layer 28 is formed. The source electrode 36 and the drain electrode 38 are spaced apart from each other on the ohmic contact layer 26 to correspond to the gate electrode 15. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA form a thin film transistor Tr.

In addition, a protective layer 42 including a drain contact hole 45 exposing the drain electrode 38 is formed over the source and drain electrodes 36 and 38 and the exposed active layer 22. The pixel electrode 50 is formed on the passivation layer 42 independently of each pixel region P and contacts the drain electrode 38 through the drain contact hole 45. In this case, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 made of the same material forming the ohmic contact layer 26 and the active layer 22 below the data line 33. ) Is formed.

Referring to the semiconductor layer 28 of the thin film transistor Tr formed in the switching region TrA in the conventional array substrate 11 having the above-described structure, the active layers 22 of pure amorphous silicon are disposed on top of each other. It can be seen that the first thickness t1 of the portion where the spaced ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion are removed by removing the ohmic contact layer 26. The thickness difference (t1 ≠ t2) of the active layer 22 is due to the manufacturing method, and the characteristic difference of the thin film transistor (Tr) occurs due to the thickness difference (t1 ≠ t2) of the active layer 22. have.

2A through 2E are cross-sectional views illustrating a process of forming a semiconductor layer, a source, and a drain electrode during a manufacturing process of a conventional array substrate. In the drawings, the gate electrode and the gate insulating film are omitted for convenience of description.

First, as shown in FIG. 2A, the pure amorphous silicon layer 20 is formed on the substrate 11, and the impurity amorphous silicon layer 24 and the metal layer 30 are sequentially formed thereon. Thereafter, a photoresist is formed on the metal layer 30 to form a photoresist layer (not shown), and the photoresist is exposed using an exposure mask, and subsequently developed to correspond to a portion where the source and drain electrodes are to be formed. A first photoresist pattern 91 having a thickness is formed, and at the same time, a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed to correspond to the spaced area between the source and drain electrodes. .

Next, as shown in FIG. 2B, the metal layer (30 of FIG. 2A) exposed to the outside of the first and second photoresist patterns 91 and 92, an impurity and a pure amorphous silicon layer below it (of FIG. 2A) 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top, and an impurity amorphous silicon pattern 25 and an active layer 22 below.

Next, as shown in FIG. 2C, the second photoresist pattern 92 of FIG. 2B having the fourth thickness is removed by ashing. In this case, the first photoresist pattern (91 in FIG. 2B) having the third thickness forms the third photoresist pattern 93 while the thickness thereof is reduced, and remains on the source drain pattern 31.

Next, as illustrated in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching by removing the source drain pattern 31 of FIG. 2C exposed to the outside of the third photoresist pattern 93. To form. In this case, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, the source and drain electrodes are dry-etched on the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the separation region between the source and drain electrodes 36 and 38. (36, 38) An ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside.

In this case, the dry etching is continued for a long time to completely remove the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside of the source and drain electrodes (36, 38), in this process the impurity amorphous silicon pattern (Fig. Even a portion of the active layer 22 disposed below 25) of 2d may have a predetermined thickness etched at a portion where the impurity amorphous silicon pattern (25 of FIG. 2d) is removed. Therefore, a difference (t1 ≠ t2) occurs in the portion where the ohmic contact layer 26 is formed on the active layer 22 and the exposed portion. If the dry etching is not performed for a long time, the impurity amorphous silicon pattern (25 in FIG. 2D) to be removed in the spaced region between the source and drain electrodes 36 and 38 remains on the active layer 22. This is to prevent this.

Therefore, in the above-described method of manufacturing the array substrate 11, the thickness difference of the active layer 22 is inevitably generated, which causes a decrease in the characteristics of the thin film transistor (Tr in FIG. 1).

In addition, the pure amorphous silicon layer constituting the active layer 22 is sufficiently thick considering the thickness of the active layer 22 that is etched and removed during the dry etching process for forming the ohmic contact layer 26 (20 in FIG. 2A). It is necessary to deposit a thick enough to have a thickness of 1000Å or more, which results in increased deposition time and reduced productivity.

On the other hand, the most important component of the array substrate is formed for each pixel region, and is connected to the gate wiring, the data wiring and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode thin film transistor Can be mentioned.

However, in the case of a thin film transistor generally constructed in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using the amorphous silicon, the amorphous silicon is changed to a quasi-stable state when irradiated with light or an electric field because the atomic arrangement is disordered, which causes a problem in stability when used as a thin film transistor element. The mobility of the carrier is low at 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as a driving circuit element.

In order to solve this problem, a method of manufacturing a thin film transistor using polysilicon as an active layer has been proposed by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by a crystallization process using a laser device.

However, referring to FIG. 3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate having a thin film transistor including a polysilicon semiconductor layer, the polysilicon may be formed using a semiconductor layer ( In the fabrication of the array substrate 51 including the thin film transistor Tr to be used as 55, the n + region 55b including high concentration of impurities in both sides of the first region 55a in the semiconductor layer 55 made of polysilicon or Requires formation of a p + region (not shown). Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the doping process. In this case, the manufacturing cost is increased, and a problem arises in that a manufacturing line must be newly configured to manufacture the array substrate 51 by adding new equipment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing an array substrate in which the active layer is not exposed to dry etching, thereby preventing damage to the surface thereof, thereby improving characteristics of the thin film transistor. .

In addition, another object of the present invention is to provide a method of manufacturing an array substrate having a thin film transistor capable of improving mobility characteristics without forming a semiconductor layer using polysilicon.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate, including a buffer layer made of an inorganic insulating material, an amorphous amorphous silicon layer, a first inorganic insulating layer, and a substrate on which a pixel region and a switching region are defined. Sequentially laminating a pure amorphous silicon layer and a second inorganic insulating layer; Performing a solid phase crystallization (SPC) process to crystallize each of the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and a first impurity polysilicon layer; A gate electrode and a gate insulating film of impurity polysilicon, which are sequentially stacked and have the same planar area in the switching region, are formed on the switching layer, and the edges of the gate insulating film are exposed on the gate insulating layer, and the same planar area is formed sequentially Forming an active layer and an inorganic insulating pattern of stacked pure polysilicon; An active contact hole is formed by depositing an inorganic insulating material on the entire surface of the inorganic insulating pattern to form an interlayer insulating layer, and patterning the interlayer insulating layer and the inorganic insulating pattern thereunder to expose both sides of the active layer and spaced apart from each other. Forming a; A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line connected to the source electrode at a boundary of the pixel region over the interlayer insulating film; A gate contact hole forming a first passivation layer over the data line and the source and drain electrodes, and patterning the first passivation layer, the interlayer insulating layer, and the gate insulating layer to expose the gate electrode outside the active layer; Forming a; Forming a gate wiring on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode through the gate contact hole and crossing the data wiring; Forming a drain contact hole exposing the drain electrode by forming a second passivation layer on the entire surface of the substrate over the gate wiring, and patterning the second passivation layer and a first passivation layer thereunder; Forming a pixel electrode in contact with the drain electrode through the drain contact hole in the pixel region over the second passivation layer, and performing a solid phase crystallization process in a state where the second inorganic insulating layer is formed. The thermal oxide film is prevented from being formed at the interface between the polysilicon layer and the second inorganic insulating layer.

Forming a gate electrode of impurity polysilicon sequentially stacked on the switching region in the switching region with an island shape, and a gate insulating film, exposing the edge of the gate insulating film over the gate insulating film, and having the same planar area as an island shape. Forming an active insulating layer and an inorganic insulating pattern of pure polysilicon sequentially stacked may include a first photoresist pattern having a first thickness corresponding to a portion in which the active layer is formed in the switching region over the second inorganic insulating layer. Forming second and third photoresist patterns having a second thickness that is thinner than the first thickness and different in width from each other to correspond to edges of the gate electrode exposed to the outside of the active layer; The second inorganic insulating layer exposed to the outside of the first to third photoresist patterns, the pure polysilicon layer, the first inorganic insulating layer, and the impurity polysilicon layer are sequentially removed to form an island in the switching region. Forming a gate electrode, a gate insulating film, a pure polysilicon pattern, and an inorganic insulating material pattern having the same planar area and sequentially stacked on the impurity polysilicon; Exposing the edges of the inorganic insulating material pattern to the outside of the first photoresist pattern by removing the second and third photoresist patterns by ashing; The edges of the gate insulating layer are exposed on the gate insulating layer by removing the inorganic insulating material pattern exposed to the outside of the first photoresist pattern and the pure polysilicon pattern under the first photoresist pattern. Forming an active layer and an inorganic insulating pattern of pure polysilicon; Removing the first photoresist pattern.

In addition, the buffer layer, the impurity amorphous silicon layer, the first inorganic insulating layer, the pure amorphous silicon layer, and the second inorganic insulating layer are continuously in the same vacuum chamber through chemical vapor deposition (CVD) equipment. It is characterized by forming.

In addition, the solid phase crystallization (SPC) process is preferably an alternating magnetic field crystallization using a thermal crystallization or alternating magnetic field crystallization apparatus through heat treatment in a temperature atmosphere of 600 ℃ to 800 ℃.

In addition, the barrier pattern, the ohmic contact layer, and the source and drain electrodes are patterned and formed at the same time by performing the same mask process.

In addition, the active layer of the pure polysilicon has a thickness of about 300 kPa to 1000 kPa, the inorganic insulating pattern has a thickness of about 100 kPa to 500 kPa, and the interlayer insulating film has a thickness of each of the gate electrode and the gate insulating film disposed thereunder. It is preferable to form to have a thickness thicker than the combined thickness.

The forming of the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line, and the forming of the gate line may include one end of the gate line. And forming a connected gate pad electrode, wherein forming the second protective layer having the drain contact hole comprises: a data pad contact exposing the gate pad contact hole and the data pad electrode exposing the gate pad electrode; And forming a hole, wherein forming the pixel electrode contacts a gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole, and contacting the data pad electrode through the data pad contact hole. Forming a data auxiliary pad electrode.

An array substrate according to the present invention comprises: a buffer layer formed of an inorganic insulating material on a front surface of a substrate on which a pixel region and a switching region are defined; A gate electrode and a gate insulating film of polysilicon sequentially stacked in the switching region on the buffer layer in the form of islands; An active layer of pure polysilicon formed in an island shape exposing the edge of the gate insulating film over the gate insulating film; An inorganic insulating pattern having the same planar area as the active layer and completely overlapping the active layer, and preventing a thermal oxide film from forming at an interface of the active layer; An interlayer insulating film formed over the substrate, the active contact hole exposing the active layer over the inorganic insulating pattern and spaced apart from each other, and acting as an etch stopper for a central portion of the active layer; A barrier pattern of pure amorphous silicon formed in the switching region in contact with the active layer through the active contact hole and spaced apart from each other through the active contact hole; An ohmic contact layer of impurity amorphous silicon formed on the spaced apart barrier pattern, respectively; Source and drain electrodes spaced apart from each other on the spaced apart ohmic contact layer; A data line formed on a boundary of the pixel area over the interlayer insulating layer and connected to the source electrode; A first passivation layer having a gate contact hole exposing the gate electrode to the outside of the inorganic insulating pattern on the data line; A gate wiring formed on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode and crossing the data wiring; A second protective layer having a drain contact hole exposing the drain electrode over the gate line; And a pixel electrode formed in the pixel area in contact with the drain electrode through the drain contact hole on the second passivation layer.

In this case, the gate electrode of the impurity polysilicon has a thickness of 500 kPa to 1000 kPa, the active layer of the pure polysilicon has a thickness of 300 kPa to 1000 kPa, and the inorganic insulating pattern has a thickness of 100 kPa to 500 kPa. The thickness of the film is 50 kPa to 300 kPa, and the interlayer insulating film is formed to have a thickness thicker than the sum of the thicknesses of each of the gate electrode and the gate insulating film disposed thereunder.

And a gate pad electrode connected to an end of the gate line, and a data pad electrode connected to an end of the data line, wherein the second passivation layer has a gate pad contact hole exposing the gate pad electrode. And a data pad contact hole exposing the data pad electrode, wherein the first passivation layer has a gate contacting the gate pad electrode through the gate pad contact hole with the same material forming the pixel electrode on the second passivation layer. An auxiliary pad electrode and a data auxiliary pad electrode contacting the data pad electrode through the data pad contact hole.

According to still another aspect of the present invention, there is provided a method of fabricating an array substrate, including a buffer layer made of an inorganic insulating material, an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous layer on a substrate on which a pixel region and a switching region are defined. Sequentially depositing silicon layers; A solid oxide crystallization (SPC) process is performed to crystallize each of the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and a first impurity polysilicon layer, and a thermal oxide film having a first thickness on the pure polysilicon layer. Forming a; A gate electrode and a gate insulating film of impurity polysilicon, which are sequentially stacked and have the same planar area in the switching region, are formed on the switching layer, and the edges of the gate insulating film are exposed on the gate insulating layer, and the same planar area is sequentially formed in the island shape. Forming an active layer and a thermal oxide film pattern of stacked pure polysilicon; An active contact hole is formed by depositing an inorganic insulating material on the entire surface of the thermal oxide layer pattern to form an interlayer dielectric layer, and patterning the interlayer dielectric layer and the thermal oxide layer pattern thereunder to expose both sides of the active layer and spaced apart from each other. Forming a; A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line connected to the source electrode at a boundary of the pixel region over the interlayer insulating film; A gate contact hole forming a first passivation layer over the data line and the source and drain electrodes, and patterning the first passivation layer, the interlayer insulating layer, and the gate insulating layer to expose the gate electrode outside the active layer; Forming a; Forming a gate wiring on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode through the gate contact hole and crossing the data wiring; Forming a drain contact hole exposing the drain electrode by forming a second passivation layer on the entire surface of the substrate over the gate wiring, and patterning the second passivation layer and a first passivation layer thereunder; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area.

In this case, the solid phase crystallization (SPC) process is a thermal crystallization (Thermal Crystallization) through a heat treatment in a temperature of 600 ℃ to 800 ℃ and oxygen (O ₂ ) gas atmosphere or a temperature and oxygen (O ₂ ) of 600 ℃ to 700 ℃. It is preferable that it is an alternating magnetic field crystallization using an alternating magnetic field crystallization apparatus in a gas atmosphere.

In addition, the first thickness is characterized in that 50 ~ 100Å.

In addition, the barrier pattern, the ohmic contact layer, the source and the drain electrode may be formed to have the same shape and the same shape in planar shape by completely patterning the same pattern by performing the same mask process.

In addition, the active layer of the pure polysilicon has a thickness of about 300 kPa to 1000 kPa, and the interlayer insulating film is formed to have a thickness thicker than the sum of the thicknesses of each of the gate electrode and the gate insulating film disposed thereunder. .

The forming of the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line, and the forming of the gate line may include one end of the gate line. And forming a connected gate pad electrode, wherein forming the second protective layer having the drain contact hole comprises: a data pad contact exposing the gate pad contact hole and the data pad electrode exposing the gate pad electrode; And forming a hole, wherein forming the pixel electrode contacts a gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole, and contacting the data pad electrode through the data pad contact hole. Forming a data auxiliary pad electrode.

In the array substrate according to the present invention, an inorganic insulating layer is formed on the amorphous silicon layer which is patterned to form the active layer, and then a crystallization process is performed to prevent the thermal oxide film from being formed on the surface of the crystallized active layer. . Therefore, since the BOE process for removing the thermal oxide film can be omitted, productivity per unit time can be improved by reducing the material cost and simplifying the process.

In addition, since the active layer is not exposed to dry etching by the method of manufacturing the array substrate according to the present invention, surface damage does not occur and thus the thin film transistor characteristics are prevented from deteriorating.

Since the active layer is not affected by dry etching, it is not necessary to consider the thickness lost by etching, thereby reducing the thickness of the active layer, thereby reducing the deposition time, thereby improving productivity.

The array substrate manufactured by the manufacturing method according to the present invention comprises a thin film transistor including a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process and forming a thin film transistor using the semiconductor layer as a semiconductor layer. There is an effect of improving the mobility characteristics by several tens to several hundred times compared to one array substrate.

Since the active layer of polysilicon is used as a semiconductor layer of the thin film transistor, doping of impurities is not necessary, and thus, the initial investment cost can be reduced because new equipment investment for the doping process is not required.

In addition, by forming the gate electrode made of polysilicon containing impurities, problems such as deformation of the gate electrode generated during the crystallization process of the conventional array substrate in which the gate electrode of the metal material is formed or short circuit between the gate electrode and the semiconductor layer are eliminated. There is an effect to solve at the source.

The solid crystallization process is performed in an oxygen (O ₂ ) gas atmosphere so that a thermal oxide film having a thickness of about 50 kPa to 100 kPa is formed on the pure polysilicon layer so that the pure polysilicon layer is exposed to air. By omitting the formation of a separate inorganic insulating layer to prevent the effect is further simplified the process.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>

4A through 4M are cross-sectional views illustrating manufacturing processes of one pixel area, a gate pad part, and a data pad part including a thin film transistor of an array substrate according to the first exemplary embodiment of the present invention. In this case, for convenience of description, a portion in which the thin film transistor Tr, which is connected to the gate and the data line in each pixel region P, is to be formed is defined as a switching region TrA.

First, as shown in FIG. 4A, a thickness of about 1000 kV to 3000 kPa is obtained by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on a transparent insulating substrate 101, for example, a glass substrate. A buffer layer 102 is formed. According to a feature of the present invention, a solid phase crystallization (SPC) process is performed in a subsequent process, and the solid phase crystallization (SPC) process requires a high temperature of 600 ° C to 800 ° C. In this case, when the substrate 101 is exposed to a high-temperature atmosphere, alkali ions may be eluted from the surface of the substrate 10 to deteriorate the characteristics of the component made of polysilicon. To form.

Next, the impurity amorphous silicon is deposited on the buffer layer 102 to form a first impurity amorphous silicon layer 103 having a thickness of about 500 mW to about 1000 mW. Subsequently, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) is deposited on the first impurity amorphous silicon layer 103 to form a first inorganic insulating layer 108 having a thickness of about 500 kPa to about 4000 kPa. Pure amorphous silicon is deposited on the first inorganic insulating layer 108 to form a pure amorphous silicon layer 111 having a thickness of about 300 mW to about 1000 mW.

The pure amorphous silicon layer 111 was formed to have a thickness of 1000 kPa or more, considering that some of the pure amorphous silicon layer 111 is etched by being exposed to dry etching proceeding to form an ohmic contact layer spaced apart from each other, and some thickness is removed from the surface thereof. However, in the exemplary embodiment of the present invention, the active layer of polysilicon (115 of FIG. 4m) finally implemented through the pure amorphous silicon layer 111 is not exposed to dry etching, and thus its thickness is thin by dry etching. There is no problem such as losing. Therefore, the pure amorphous silicon layer 111 may be formed to have a thickness of 300 mW to 1000 mW, which may serve as an active layer. In this case, the material cost and unit process time may be reduced.

Next, as a characteristic of the manufacturing method according to an embodiment of the present invention, the inorganic insulating material, for example, silicon oxide (SiO ₂ ) is deposited on the pure amorphous silicon layer 111 to have a thickness of about 100 kPa to about 500 kPa. An inorganic insulating layer 116 is formed. The reason why the second inorganic insulating layer 116 is formed on the pure amorphous silicon layer is that the pure amorphous silicon layer 111 is not exposed to the air during a crystallization process requiring a high temperature of 600 ° C to 800 ° C. This is to prevent the formation of a thermal oxide film on the surface.

On the other hand, if the process proceeds to the above-mentioned step of forming the second inorganic insulating layer 116, a total of five layers of material layers 102, 103, 108, 111, 116 are formed on the substrate 101. At this time, as another feature of the present invention, the five-layer material layers 102, 103, 108, 111, and 116 are all semiconductor materials or inorganic insulating materials, and therefore, all of these materials are chemical vapor deposition (CVD). By changing only the reaction gas in the same vacuum chamber 195 through the equipment (not shown) is formed continuously without exposure to the atmosphere. When the five-layer material layers 102, 103, 108, 111, and 116 are continuously deposited in one vacuum chamber 195, the surface of the pure amorphous silicon layer 111, which will form an active layer later, is atmospheric. It is characterized by being able to prevent the deterioration of the characteristics of the thin film transistor due to the surface contamination of the active layer by not being exposed to.

Next, as shown in FIG. 4B, the pure amorphous silicon layer (111 of FIG. 4A) is subjected to a solid phase crystallization (SPC) process in order to improve mobility characteristics of the pure amorphous silicon layer (111 of FIG. 4A). The crystallization is performed to form the pure polysilicon layer 112. In this case, the solid phase crystallization (SPC) process is, for example, a thermal crystallization process through heat treatment in an atmosphere of 600 ℃ to 800 ℃, or alternating in a temperature atmosphere of 600 ℃ to 700 ℃ using an alternating magnetic field crystallization device It is preferable that the magnetic field crystallization (Alternating Magnetic Field Crystallization) process.

At this time, as a result of the solid state crystallization (SPC) process, not only the pure amorphous silicon layer (FIG. 4A 111) but also the first impurity amorphous silicon layer (103 of FIG. 4A) are crystallized to form the impurity polysilicon layer 104. .

Next, as shown in FIG. 4C, a photoresist is formed on the second inorganic insulating layer 117 to form a photoresist layer (not shown), and a light transmitting region with respect to the photoresist layer (not shown). And a blocking region (not shown), and a slit form, or further provided with a plurality of coating films to adjust the amount of light passing through the light transmittance is smaller than the transmission region (not shown) and than the blocking region (not shown) Diffraction exposure or halftone exposure is performed using an exposure mask (not shown) composed of a large semi-transmissive region (not shown).

Thereafter, the exposed photoresist layer (not shown) is developed to partially form a portion of the portion where the gate electrode 105 of FIG. 4M is to be formed on the second inorganic insulating layer 116 corresponding to the switching region TrA. The first and second photoresist patterns 191a and 191b having a first thickness are formed to correspond to the active layer of the pure polysilicon formed (not overlapping with 115 of FIG. 4M), and the gate electrode (FIG. 4M). The third photoresist pattern 191c having a second thickness thicker than the first thickness corresponds to a portion where the active layer (115 of FIG. 4M) of pure polysilicon is to be formed. Form. Accordingly, a third photoresist pattern 191c having a second thickness is formed to correspond to a portion overlapping with the active layer (115 of FIG. 4M) of the pure polysilicon among the portion where the gate electrode (105 of FIG. 4M) is to be formed. The region where the active layer (115 of FIG. 4M) of pure polysilicon is not formed among the portions where the gate electrode (105 of FIG. 4M) is to be formed is formed of the first and second photoresist patterns 191a of the first thickness. 191b is formed, and the photoresist layer (not shown) is removed in all regions on the substrate 101 where the gate electrode 105 of FIG. 4M is not formed, thereby exposing the second inorganic insulating layer 116. To achieve the state.

At this time, the first and second photoresist patterns 191a and 191b are exposed to the outside of the third photoresist pattern 191c in the switching region TrA, and outside the third photoresist pattern 191c. The first and second photoresist patterns 191a and 191b exposed to each other may have different widths. The gate electrode (105 in FIG. 4M), the gate insulating film (109 in FIG. 4M), and the active layer (115 in FIG. 4M) of pure polysilicon and the inorganic insulating pattern (FIG. The edge portion of 118 of 4m forms a stepped shape to prevent the interlayer insulating film 122 (FIG. 4M) formed thereafter from being broken or lifted, and further formed gate wiring (145 of FIG. 4M) and the inorganic insulating pattern ( This is to secure an area for forming a gate contact hole (142 of FIG. 4M) for contact with the gate electrode (114 of FIG. 4M) exposed to the outside of 118 of FIG. 4M.

Next, as shown in FIG. 4D, the second inorganic insulating layer 116 of FIG. 4C and the lower portion of the first, second and third photoresist patterns 191a, 191b, and 191c are sequentially positioned below the second inorganic insulating layer. The pure polysilicon layer (112 in FIG. 4C), the first inorganic insulating layer (108 in FIG. 4C), and the impurity polysilicon layer (104 in FIG. 4C) are sequentially etched and removed to the switching region TrA. A gate electrode 114, a gate insulating layer 109, a pure polysilicon pattern 113, and an inorganic insulating material pattern 117 of impurity polysilicon sequentially stacked in an island form are formed on the buffer layer 102. In this case, for the regions other than the switching region TrA, the second inorganic insulating layer 116 of FIG. 4C, the pure polysilicon layer 112 of FIG. 4C, the first inorganic insulating layer 108 of FIG. 4C, and the impurities All of the polysilicon layers (104 in FIG. 4C) are removed, leaving the buffer layer 102 exposed.

Meanwhile, in the embodiment of the present invention, forming the gate electrode 105 with impurity polysilicon rather than a metal material may occur when the pure polysilicon pattern 113 formed on the gate electrode 105 is formed. To solve the problem. When forming a thin film transistor having a bottom gate structure, a gate electrode is formed of a metal material on a substrate, and a pure amorphous silicon layer is formed on the substrate through a gate insulating film to form a semiconductor layer. The solid phase crystallization from the pure polysilicon layer requires a relatively high temperature of 600 ° C or higher. Accordingly, during the solid phase crystallization process requiring a relatively high temperature, the gate electrode made of a metal material may be deformed or may have spikes that come into contact with the crystallized pure polysilicon layer through the gate insulating layer. Causes

Accordingly, in the embodiment of the present invention, in order to solve the problem occurring during the crystallization process by forming the gate electrode of the metal material, the gate electrode 105 is formed using impurity polysilicon that does not cause the above-described problem even when exposed to such a high temperature atmosphere. ) Is formed.

On the other hand, in the case of the gate electrode 105 made of impurity polysilicon, although the conductivity is lower than that of the metal material, when the thickness of the gate electrode 105 of the impurity polysilicon is 500 mW to 1000 mW, the resistance value per unit area is 150 mW / sq ( □) to 230 mW / sq (□), which is similar to that of indium tin oxide (ITO) or indium zinc oxide (IZO), a transparent conductive material. Therefore, even if the gate electrode is formed of impurity polysilicon, it is not a problem to perform a role as the gate electrode such as to form a channel in the active layer sufficiently.

Next, as shown in FIG. 4E, the substrate 101 on which the gate electrode 105, the gate insulating layer 109, the pure polysilicon pattern 113, and the inorganic insulating material pattern 117 of impurity polysilicon are formed is ashed. (ashing) to remove the first and second photoresist patterns 191a and 191b of FIG. 4D to the outside of the third photoresist pattern 191c in the switching region TrA. Both surfaces of the inorganic insulating material pattern 117 are exposed. At this time, the thickness of the third photoresist pattern 191c is also reduced due to the ashing process, but is still on the inorganic insulating material pattern 117.

 Next, as illustrated in FIG. 4F, the inorganic insulating material pattern 117 of FIG. 4E and the pure polysilicon pattern 113 of FIG. 4E exposed to the outside of the third photoresist pattern 191c are etched. And the edges of the gate insulating layer 109 corresponding to the gate electrodes 105 are exposed. In this case, the gate insulating layer 109 exposed to the outside of the third photoresist pattern 191c may have a different width based on the third photoresist pattern 191c. In order to correspond to the gate insulating layer 109 having a wide width and exposed to the outside of the third photoresist pattern 191c, a gate wiring (145 of FIG. 4M) that is to be later contacted with the gate electrode 105 should be formed to reflect this. For sake. In this case, the pure polysilicon pattern (113 of FIG. 4E) remaining on the gate insulating layer 109 without being etched by the third photoresist pattern 191c forms the active layer 115 of pure polysilicon. . In this case, the active layer 115 of the pure polysilicon is formed on the top of the active layer 115 in a state where the area thereof is reduced, and the inorganic insulating pattern 118 is completely overlapped.

Next, as shown in FIG. 4G, the inorganic insulating pattern 118 is formed by removing the third photoresist pattern (191c of FIG. 4F) remaining on the inorganic insulating pattern 118 by performing a strip. Expose

Next, as illustrated in FIG. 4H, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is deposited on the inorganic insulating pattern 118 to form a third inorganic insulating layer having a single layer structure. (Not shown) or by depositing the two materials in succession to form a third inorganic insulating layer (not shown) of a double layer structure. In this case, the third inorganic insulating layer (not shown) may be formed to have a thickness larger than the sum of the thicknesses of the gate electrode 105 and the gate insulating layer 109 formed with the same planar area and completely overlapping each other. .

The third inorganic insulating layer (not shown) is formed to have a thickness larger than the sum of the thicknesses of the gate electrode 105 and the gate insulating layer 109 in the patterned state disposed below the buffer layer 102. This is to ensure that the gate electrode 105 and the gate insulating film 109 are well formed in a portion forming a step without reference. In this case, the thickness of the gate electrode 105 and the gate insulating layer 109 is greater than the sum of the thicknesses of the active layer 115 of the pure polysilicon and the inorganic insulating pattern 118 thereon. If the third inorganic insulating layer 122 is formed thicker than the sum of the respective thicknesses of the gate insulating layer 109 and the gate insulating layer 109, the active layer 115 and the inorganic insulating pattern of the pure polysilicon may be formed based on the gate insulating layer 109. It is not a problem in the stepped portion by 118.

The gate electrode 105 has a thickness of 500 kPa to 1000 kPa, and the thickness of the gate insulating film 109 is 500 kPa to 4000 kPa so that the thickness of the third inorganic insulating layer (not shown) is thicker than 1000 kPa to 5000 kPa. It is preferable to form. For example, if the gate electrode 105 has a thickness of about 1000 GPa and the gate insulating film 109 is formed with a thickness of about 2000 GPa, the third inorganic insulating layer (not shown) has a thickness greater than 3000 GPa. For example, it is possible to prevent the occurrence of a break in a portion where a step is generated by forming the layer to have a thickness of, for example, about 3100 mm 3.

  Thereafter, the third inorganic insulating layer (not shown) formed on the entire surface of the substrate 101 is coated with a photoresist, exposure using an exposure mask, development of an exposed photoresist, etching and stripping, etc. Interlayer having two contact holes (not shown) exposing the inorganic insulating pattern 118 to both sides thereof based on the central portion of the active layer 115 of the pure polysilicon by patterning by performing a mask process including a. The insulating film 122 is formed. Two active contacts that finally expose the active layer 115 of pure polysilicon by performing dry etching to remove the inorganic insulating pattern 118 exposed in correspondence with the two contact holes (not shown). The hole 123 is formed.

In this case, the interlayer insulating film 122 serves as an etch stopper by covering the active layer 115 of pure polysilicon to correspond to the central portion of the active layer 115 of pure polysilicon, and to insulate other regions. It is characterized by acting as a layer.

Next, as shown in FIG. 4I, the active contact hole 123 is exposed to correspond to the active layer 115 of the pure polysilicon, and the center portion of the active layer 115 of the pure polysilicon is etched. Pure amorphous silicon is deposited on the entire surface of the interlayer insulating film 122 serving as a stopper to further form a barrier layer (not shown) having a thickness of about 50 to about 300 microns, and subsequently by depositing impurity amorphous silicon to about 100 to about 300 microns. A second impurity amorphous silicon layer (not shown) having a thickness is formed. In this case, the reason for forming a barrier layer (not shown) made of pure amorphous silicon is because the bonding strength of the pure polysilicon with the active layer 115 is better than pure amorphous silicon than impurity amorphous silicon. C) is interposed between the active layer 115 of pure polysilicon and the impurity amorphous silicon layer (not shown) to improve the bonding force between the two layers 115 (not shown) and further reduce the contact resistance. .

Subsequently, a first metal layer (not shown) is deposited on the second impurity amorphous silicon layer (not shown) by depositing any one of a second metal material, for example, molybdenum (Mo), chromium (Cr), and molybdenum (MoTi). To form.

On the other hand, before forming the barrier layer (not shown) on the interlayer insulating film 122, the active contact hole 123 by performing a cleaning process using a buffered oxide etchant (BOE) (hereinafter referred to as BOE cleaning). Although the thermal oxide film formed naturally during the crystallization process is performed on the surface of the active layer 115 of pure polysilicon exposed through), the BOE cleaning is performed in the fabrication of the array substrate 101 according to the embodiment of the present invention. It is not necessary to carry out. Array substrate 101 according to the present invention is a second inorganic insulation continuously in the vacuum chamber (195 of FIG. 4A) of the chemical vapor deposition (CVD) equipment without exposure to the atmosphere over the pure amorphous silicon layer (111 of FIG. 4A) A layer (116 of FIG. 4A) was formed, and the solid state crystallization (SPC) process was performed while the second inorganic insulating layer (116 of FIG. 4A) covered the pure amorphous silicon layer (111 of FIG. 4A). The surface of the active layer 115 of pure polysilicon More precisely, no thermal oxide film was formed at the interface between the active layer 115 of pure polysilicon and the inorganic insulating pattern 118.

Therefore, BOE (buffered oxide etchant) cleaning to remove the thermal oxide film does not need to proceed separately. If a thermal oxide film is formed on the surface of the active layer of pure polysilicon, it must be removed. This is because the thermal oxide film (not shown) acts as an element that degrades ohmic properties when the active layer 115 of pure polysilicon contacts the barrier layer (not shown). Further, when the thin film transistor is formed without removing the thermal oxide film, the characteristics thereof may be very degraded or may not operate as the thin film transistor. Therefore, the thermal oxide film must be formed with the barrier layer (not shown) removed. do.

Next, each pixel is formed on the interlayer insulating layer 122 by patterning the first metal layer (not shown), the second impurity amorphous silicon layer (not shown) and the barrier layer (not shown) under the mask process. The data pad electrode 138 is formed on the boundary of the area P, and is connected to one end of the data wire 130 at the data pad part DPA at which one end of the data wire 130 is located. ).

At the same time, in the switching region TrA, source and drain electrodes 133 and 136 spaced apart from each other are formed on the interlayer insulating layer 122 and impurity amorphous silicon is formed under the source and drain electrodes 133 and 136. A barrier pattern 125 of pure amorphous silicon is formed under the ohmic contact layer 127 formed below. In this case, the barrier pattern 125 of pure amorphous silicon is in contact with the active layer 115 of pure polysilicon through the active contact hole 123, respectively.

In addition, the source electrode 133 and the data line 130 formed in the switching region TrA are formed to be connected to each other, and at this time, the source and drain electrodes 133 and 136 spaced apart from each other The ohmic contact layer 127 and the barrier pattern 125 have the same planar shape and planar area as that of the source and drain electrodes 133 and 136, respectively, and are completely overlapped with each other.

 As described above, the first dummy pattern 128 made of impurity amorphous silicon and the second dummy pattern 126 made of pure amorphous silicon are also formed under the data line 130 and the data pad electrode 138. Will be formed.

Meanwhile, in the exemplary embodiment of the present invention, pure polysilicon forming a channel region in the process of forming the data line 130, the source and drain electrodes 133 and 136, the ohmic contact layer 127, and the barrier pattern 125 is performed. An inorganic insulating pattern 118 and an interlayer insulating film 122 serving as an etch stopper are formed to correspond to a central portion of the active layer 115 of the active layer 115, and the ohmic contact layer is formed after the source and drain electrodes 133 and 136 are formed. In the dry etching process for patterning 127 and the barrier pattern 125, the active layer 115 of pure polysilicon is not affected at all.

Therefore, it can be seen that the surface damage of the active layer due to the dry etching process, which is a problem mentioned in the related art, does not occur. Since the thickness of the active layer 115 of the pure polysilicon is not reduced, the entire switching area TrA is not reduced. Therefore, it can be seen that the active layer 115 of pure polysilicon has a predetermined thickness.

On the other hand, the gate electrode 105 of the impurity polysilicon, the gate insulating film 109, the active layer 115 of pure polysilicon and the sequentially stacked in the switching region (TrA) by the process proceeds to the above-described step The inorganic insulating pattern 118, the interlayer insulating film 122, the barrier pattern 125 of pure amorphous silicon, the ohmic contact layer 127 of impurity amorphous silicon, and the source and drain electrodes 133 and 136 are formed of a thin film. A transistor Tr is formed.

On the other hand, although not shown in the drawings, when the above-described array substrate 101 is manufactured as an array substrate for an organic light emitting device, the data on the same layer on which the data wiring 130 is formed in parallel with the data wiring 130 Power wirings (not shown) may be further spaced apart from the wiring 130 by a predetermined distance, and in each pixel area P, the data wiring 130 and the gate wiring (145 of FIG. 4M) to be manufactured in a later process. In addition to the thin film transistor Tr (which constitutes a switching thin film transistor) connected thereto, a driving thin film transistor (not shown) having the same structure and connected to the power line and the switching thin film transistor Tr may be further formed.

Next, as illustrated in FIG. 4J, a substrate on which the data line 130, the data pad electrode 138, the source and drain electrodes 133 and 136, the ohmic contact layer 127, and the barrier pattern 125 are formed ( 101 by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the source and drain electrodes 133 and 136 and the data line 130 and the data pad electrode 138. A protective layer 140 is formed, and a mask process is performed to pattern the first protective layer 140, the interlayer insulating layer 122, and the gate insulating layer 109 to form an outer side of the active layer 115 of the pure polysilicon. The gate contact hole 142 exposing the gate electrode 105 is formed.

Next, as shown in FIG. 4K, a second metal material such as aluminum (Al), aluminum alloy (AlNd), and copper (Cu) is disposed on the first protective layer 140 provided with the gate contact hole 142. ), Copper alloy, molybdenum (Mo) and chromium (Cr) are deposited to form a second metal layer (not shown). Subsequently, the second metal layer (not shown) is patterned by performing a mask process so as to contact the exposed gate electrode 105 at the boundary of each pixel region P over the first passivation layer 140 and the data line. A gate wiring 145 intersecting with 130 is formed.

At the same time, a gate pad electrode 147 connected to one end of the gate line 145 is formed in the gate pad part GPA at which one end of the gate line 145 is positioned.

In this case, the gate wiring 145 and the gate pad electrode 147 may be formed of only one metal material of the above-described second metal material to form a single layer structure, or two or more different second metal materials may be different from each other. The vapor deposition may be performed to form a double layer or triple layer structure. For example, when the gate line 145 and the gate pad electrode 147 have a double layer structure, the gate line 145 and the gate pad electrode 147 may be made of aluminum alloy (AlNd) / molybdenum (Mo), and when the triple layer structure is formed, molybdenum (Mo) It may be made of aluminum alloy (AlNd) / molybdenum (Mo). In the drawing, the gate wiring 145 and the gate pad electrode 147 having a single layer structure are shown.

Next, as shown in FIG. 4L, the second protection is performed by depositing an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), on the entire surface of the gate line 145 and the gate pad electrode 147. Form layer 150. Thereafter, a mask process is performed to pattern the second protective layer 150 and the first protective layer 140 below the drain contact hole exposing the drain electrode 136 in each switching region TrA. 152 and a gate pad contact hole 154 exposing the gate pad electrode 147 in the gate pad part GPA. At the same time, in the data pad part DPA, a data pad contact hole 156 exposing the data pad electrode 138 is formed.

Next, as shown in FIG. 4M, a transparent conductive material such as indium is formed on the entire surface of the second protective layer 150 including the drain contact hole 152 and the gate and data pad contact holes 154 and 156. Tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited to form a transparent conductive material layer (not shown), and then patterned by performing a mask process to form the drain contact hole in the pixel region P. The pixel electrode 170 in contact with the drain electrode 136 is formed through 152.

At the same time, in the gate pad part GPA, a gate auxiliary pad electrode 172 is formed on the second passivation layer 150 to contact the gate pad electrode 147 through the gate pad contact hole 154. Also, in the data pad part DPA, the data auxiliary pad electrode 174 may be formed on the second passivation layer 150 to contact the data pad electrode 138 through the data pad contact hole 156. The array substrate 101 according to the first embodiment of the invention is completed.

Meanwhile, although not shown in the drawings, when a driving thin film transistor (not shown) is formed in each pixel region P, the thin film transistor Tr (which forms a switching thin film transistor) formed in the switching region TrA is formed. The drain electrode (not shown) of the driving thin film transistor (not shown) does not contact the pixel electrode 170, but instead the drain electrode (not shown) of the pixel electrode 170 and the driving thin film transistor (not shown). It exposes to form a contact so as to be electrically connected through the formed drain contact hole (not shown). In this case, the thin film transistor Tr formed in the switching region TrA is completely covered by the first and second protective layers 140 and 150 without forming the drain contact hole 152. When the thin film transistor Tr (which forms a switching thin film transistor) connected to the gate and data lines 145 and 130 and the driving thin film transistor (not shown) are formed in the pixel region P in the switching region TrA. The array substrate for the organic light emitting diode is formed instead of the array substrate for the liquid crystal display device.

&Lt; Embodiment 2 >

5A through 5F are cross-sectional views illustrating manufacturing processes of one pixel region, a gate pad portion, and a data pad portion including a thin film transistor of an array substrate according to a second exemplary embodiment of the present invention. In this case, for convenience of description, a portion in which the thin film transistor Tr, which is connected to the gate and data lines in each pixel region P, is to be formed is defined as a switching region TrA. 100 is added to refer to reference numerals.

At this time, in the method of manufacturing the array substrate according to the second embodiment of the present invention, since the step after the solid phase crystallization process proceeds in the same manner as the first embodiment described above, the description will be mainly focused on the steps having different points.

First, as shown in FIG. 5A, a thickness of about 1000 kV to 3000 kPa is obtained by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on a transparent insulating substrate 101, for example, a glass substrate. A buffer layer 202 is formed.

Next, the impurity amorphous silicon is deposited on the buffer layer 202 to form a first impurity amorphous silicon layer 203 having a thickness of about 500 mW to about 1000 mW. Subsequently, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) is deposited on the first impurity amorphous silicon layer 203 to form a first inorganic insulating layer 208 having a thickness of about 500 kV to about 4000 kPa. Pure amorphous silicon is deposited on the first inorganic insulating layer 208 to form a pure amorphous silicon layer 211 having a thickness of about 300 mW to about 1000 mW.

In the second embodiment of the present invention, since the active layer of polysilicon (215 of FIG. 5F) finally implemented through the pure amorphous silicon layer 211 is not exposed to dry etching, its thickness is thin by the dry etching. There is no problem such as losing. Accordingly, the pure amorphous silicon layer 211 may be formed to have a thickness of 300 mW to 1000 mW, which can serve as an active layer, and in this case, the material cost and unit process time can be shortened.

Meanwhile, as described above, a buffer layer 202 sequentially formed on the substrate 201, an impurity amorphous silicon layer 203, a first inorganic insulating layer 208, and a pure amorphous silicon layer 211 are provided. It can be seen that the material layers of the middle layer are all semiconductor materials or inorganic insulating materials, all of which are the same vacuum chamber 295 through chemical vapor deposition (CVD) equipment (not shown). By changing only the reaction gas in the interior it is characterized by being formed continuously without exposure to the atmosphere.

Next, as shown in FIG. 5B, the pure amorphous silicon layer (211 of FIG. 5A) is subjected to a solid phase crystallization (SPC) process in order to improve mobility characteristics and the like of the pure amorphous silicon layer (211 of FIG. 5A). The crystallization is performed to form the pure polysilicon layer 212.

In this case, as the most characteristic in the second embodiment of the present invention, the solid phase crystallization (SPC) process is a thermal crystallization through heat treatment in an oxygen (O ₂ ) gas atmosphere and temperature of 600 ℃ to 800 ℃, for example. ) Or an alternating magnetic field crystallization (Alternating Magnetic Field Crystallization) process in an oxygen (O ₂ ) gas atmosphere at a temperature of 600 ° C. to 700 ° C. using an alternating magnetic field crystallization apparatus.

When the thermal crystallization or the alternating magnetic field crystallization process is performed in an oxygen (O ₂ ) gas atmosphere, the pure amorphous silicon layer (211 of FIG. 5A) is crystallized to be changed to pure polysilicon layer 212 and the surface thereof is In response to the oxygen (O ₂ ) gas, a thermal oxide film 291 having a thickness of about 50 Pa to about 100 Pa is formed. In this case, since the thermal oxide film 291 is formed by reacting with pure oxygen (O ₂ ) gas containing no pollutant present in the general atmosphere, the thermal oxide film 291 has a very good film quality.

Thermal crystallization which is generally performed is usually carried out by heating to a temperature of 600 ° C. to 800 ° C. in a chamber or furnace having a general atmospheric atmosphere. In this case, the thermal oxide film formed by reacting with oxygen contained in the general atmosphere contains contaminants, and the oxygen oxide contained in the atmosphere has a relatively low density, and thus the thickness of the thermal oxide film formed on the surface of the pure polysilicon layer. Since it is less than 10Å, it is too thin to play a role for the protection of the pure polysilicon layer 212 is unable to perform its role.

In addition, the alternating magnetic field crystallization is usually carried out in an inert gas (N ₂ ) gas atmosphere or in one atmosphere atmosphere as in the thermal crystallization, and thus the pure water when proceeding in a nitrogen (N ₂ ) gas atmosphere. Almost no thermal oxide film is generated on the polysilicon layer 212, and when the process proceeds in a general atmosphere, the pollutant may be contained or the thickness of the thermal oxide film may be 10 Å or less, thereby preventing the pure polysilicon layer from serving as a protection. do.

However, in the second embodiment of the present invention, the thermal crystallization or the alternating magnetic field crystallization process is performed in the chamber 297 in which the oxygen (O ₂ ) gas atmosphere is formed. Therefore, in this case, the oxygen (O ₂ ) gas is continuously supplied to have a constant density in the chamber 297 to have a thickness of about 50 kPa to about 100 kPa on the surface of the pure polysilicon layer 212 in a high temperature atmosphere. A thermal oxide film 291 is formed to smoothly perform the role of protection of the silicon layer 212. In this case, since the thermal oxide film 291 does not contain contaminants, the surface of the pure polysilicon layer 212 may be formed. Problems such as contamination do not occur.

Meanwhile, as a result of the solid state crystallization (SPC) process in the pure oxygen (O ₂ ) gas atmosphere, not only the pure amorphous silicon layer (FIG. 5A 211) but also the first impurity amorphous silicon layer (203 of FIG. 5A) are crystallized. An impurity polysilicon layer 204 is formed.

Next, the same process is performed on the substrate 201 on which the pure thermal oxide film 212 having a thickness of about 50 Pa to 100 Pa is formed through FIGS. 4C to 4G of the first embodiment, as shown in FIG. 5C. A gate insulating film 209 having the same planar area as that of the impurity polysilicon gate electrode 205 in island form over the buffer layer 202 and completely overlapping the switching region TrA on the substrate 201, and the gate insulating film 209. The active layer 215 of pure polysilicon exposing the edges of the ()) and the thermal oxide film pattern 292 having the same planar area as the active layer 215 and completely overlapping are formed.

In this process, since the active layer 215 of pure polysilicon is covered by the thermal oxide pattern 292 having a thickness of about 50 kPa to about 100 kPa, the active layer 215 is not exposed to air and thus protected from contamination.

Next, as shown in FIG. 5D, the inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the thermal oxide pattern 292 to form a third inorganic insulating layer having a single layer structure. A third inorganic insulating layer (not shown) having a double layer structure is formed by forming a layer (not shown) or depositing the two materials in succession. In this case, the third inorganic insulating layer (not shown) is formed to have a thickness greater than the sum of the thickness of each of the gate electrode 205 and the gate insulating film 209 having the same planar area and completely overlapping each other. The reason for this formation is omitted since it is already mentioned in the first embodiment.

Subsequently, the third inorganic insulating layer (not shown) formed on the entire surface of the substrate 201 is coated with a photoresist, an exposure using an exposure mask, a development of an exposed photoresist, an etching and a strip, etc. An interlayer insulating film having two holes hl exposing the thermal oxide pattern 292 to both sides thereof based on a central portion of the active layer 215 of the pure polysilicon by patterning by performing a mask process including 222 is formed.

Next, as shown in FIG. 5E, the thermal oxide pattern 292 exposed in correspondence with the two holes (hl in FIG. 5D) is removed by dry etching to finally remove the thermal oxide pattern 292 in each switching region TrA. Two active contact holes 223 exposing the active layer 215 of pure polysilicon are formed.

In this case, the interlayer insulating layer 222 and the thermal oxide pattern 292 remaining thereunder cover the active layer 215 of pure polysilicon so as to correspond to the central portion of the active layer 215 of pure polysilicon. Therefore, it serves as an etch stopper, and serves as an insulating layer in correspondence with other areas.

In this case, a hole (hl of FIG. 5D) is formed in the interlayer insulating layer 222 to expose the thermal oxide pattern 292, and the thermal oxide pattern 292 exposed inside the hole (hl of FIG. 5D). Although the step of forming the active contact hole 223 exposing the active layer 215 by exposing the active layer 215 is shown as proceeding separately in the figure, it proceeds substantially continuously. That is, since the interlayer insulating film 222 is also made of an inorganic insulating material, patterning of the interlayer insulating film 222 is also performed through dry etching. Therefore, the holes (hl in FIG. 5D) and the active contact holes 223 are continuously formed in the chamber (not shown) for dry etching without any additional movement. In this case, when the interlayer insulating layer 222 and the material forming the thermal oxide pattern 292 are different, only the reaction gas in the chamber (not shown) may be changed. For this reason, the formation of the hole (hl in FIG. 5D) and the active contact hole may be performed. The formation of 223 may proceed through dry etching continuously.

Next, as in FIG. 5F, the active contact hole 223 is disposed on the interlayer insulating layer 222 in the switching region TrA by proceeding in the same manner as the process according to the first embodiment described with reference to FIGS. 4I to 4M. A barrier pattern 225 of pure amorphous silicon, an ohmic contact layer 227 of impurity amorphous silicon, and source and drain electrodes 233 and 236 are formed to be spaced apart from each other in contact with the active layer 215. In this case, the gate electrode 205 of the impurity polysilicon, the gate insulating layer 209, the active layer 215 of pure polysilicon, the inorganic insulating pattern 218, and the stacking layer are sequentially stacked on the switching region TrA, The interlayer insulating film 222, the barrier pattern 225 of pure amorphous silicon, the ohmic contact layer 227 of impurity amorphous silicon, and the source and drain electrodes 233 and 236 form a thin film transistor Tr.

In addition, a data line 230 is formed on the boundary of each pixel region P on the interlayer insulating layer 222, and the data line 230 is formed on the data pad part DPA where one end of the data line 230 is located. The data pad electrode 238 connected to one end of the () is formed.

In addition, the source and drain of the substrate 201 having the data line 230, the data pad electrode 238, the source and drain electrodes 233 and 236, the ohmic contact layer 227, and the barrier pattern 225 are formed. The first protective layer 240 is formed by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the electrodes 233 and 236, the data line 230, and the data pad electrode 238. The gate electrode 205 is formed outside the active layer 215 of pure polysilicon by patterning the first passivation layer 240, the interlayer insulating layer 222, and the gate insulating layer 209 by performing a mask process. A gate contact hole 242 is formed to be exposed.

In addition, the gate contact hole 205 contacts the exposed gate electrode 205 at the boundary of each pixel region P on the first passivation layer 240 provided with the gate contact hole 242 and crosses the data line 230. The gate wiring 245 is formed.

At the same time, a gate pad electrode 247 connected to one end of the gate line 245 is formed in the gate pad part GPA at which one end of the gate line 245 is positioned.

Next, a second protective layer 250 is formed by depositing an inorganic insulating material, such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), on the entire surface of the gate line 245 and the gate pad electrode 247. Subsequently, a drain process hole exposing the drain electrode 236 in each switching region TrA by patterning the second passivation layer 250 and the first passivation layer 240 under the mask process is performed. 252 is formed, and in the gate pad part GPA, a gate pad contact hole 254 exposing the gate pad electrode 247 is formed. At the same time, the data pad part DPA forms a data pad contact hole 256 exposing the data pad electrode 238.

Next, a transparent conductive material such as indium-tin-oxide (ITO) on the front surface of the second protective layer 250 having the drain contact hole 252 and the gate and data pad contact holes 254 and 256, or Indium-Zink Oxide (IZO) is deposited to form a transparent conductive material layer (not shown), which is then patterned by performing a mask process, through the drain contact hole 252 in the pixel region P, through the drain electrode. A pixel electrode 270 in contact with 236 is formed.

At the same time, in the gate pad part GPA, a gate auxiliary pad electrode 272 is formed on the second passivation layer 250 to contact the gate pad electrode 247 through the gate pad contact hole 254. Also, in the data pad part DPA, the data auxiliary pad electrode 274 is formed on the second passivation layer 250 to contact the data pad electrode 238 through the data pad contact hole 256. The array substrate 201 according to the second embodiment of the invention is completed.

The array substrate 201 according to the second embodiment manufactured by this step intentionally runs a solid crystallization (SPC) process in an oxygen (O ₂ ) gas atmosphere and is intentionally on top of the pure polysilicon layer (212 in FIG. 5B). By forming a thermal oxide film (291 of FIG. 5B) having a thickness sufficient to serve as an insulating layer, the formation of a second additional inorganic insulating layer separate from that of the first embodiment is eliminated, thereby further simplifying the manufacturing process. Is characteristic.

1 is a cross-sectional view of a pixel region including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting device.

2A through 2E are cross-sectional views illustrating a step of forming a semiconductor layer, a source and a drain electrode during a manufacturing step of a conventional array substrate;

3 is a cross-sectional view of one pixel area including the thin film transistor in an array substrate having a thin film transistor having a polysilicon semiconductor layer in the related art.

4A through 4M are cross-sectional views illustrating manufacturing processes of one pixel area, a gate pad part, and a data pad part including a thin film transistor of an array substrate according to a first exemplary embodiment of the present invention.

5A through 5F are cross-sectional views illustrating manufacturing processes of one pixel area, a gate pad part, and a data pad part including a thin film transistor of an array substrate according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

101 substrate 102 buffer layer

104 impurity polysilicon layer 108 first inorganic insulating layer

112: pure polysilicon layer 116: second inorganic insulating layer

DPA: Data Pad Section GPA: Gate Pad Section

P: Pixel Area Tr: Thin Film Transistor

TrA: switching area

Claims (16)

Sequentially stacking a buffer layer made of an inorganic insulating material, an impurity amorphous silicon layer, a first inorganic insulating layer, a pure amorphous silicon layer, and a second inorganic insulating layer on a substrate on which a pixel region and a switching region are defined; Performing a solid phase crystallization (SPC) process to crystallize each of the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and a first impurity polysilicon layer; A gate electrode and a gate insulating film of impurity polysilicon, which are sequentially stacked and have the same planar area in the switching region, are formed on the switching layer, and the edges of the gate insulating film are exposed on the gate insulating layer, and the same planar area is sequentially formed. Forming an active layer and an inorganic insulating pattern of stacked pure polysilicon; An active contact hole is formed by depositing an inorganic insulating material on the entire surface of the inorganic insulating pattern to form an interlayer insulating layer, and patterning the interlayer insulating layer and the inorganic insulating pattern thereunder to expose both sides of the active layer and spaced apart from each other. Forming a;  A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line connected to the source electrode at a boundary of the pixel region over the interlayer insulating film; A gate contact hole forming a first passivation layer over the data line and the source and drain electrodes, and patterning the first passivation layer, the interlayer insulating layer, and the gate insulating layer to expose the gate electrode outside the active layer; Forming a; Forming a gate wiring on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode through the gate contact hole and crossing the data wiring; Forming a drain contact hole exposing the drain electrode by forming a second passivation layer on the entire surface of the substrate over the gate wiring, and patterning the second passivation layer and a first passivation layer thereunder; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area And a solid state crystallization process in a state where the second inorganic insulating layer is formed, thereby preventing formation of a thermal oxide film at an interface between the pure polysilicon layer and the second inorganic insulating layer. Manufacturing method. The method of claim 1, Forming a gate electrode of impurity polysilicon sequentially stacked on the switching region in the switching region with an island shape, and a gate insulating film, exposing the edge of the gate insulating film over the gate insulating film, and having the same planar area as an island shape. Forming the active layer and the inorganic insulating pattern of pure polysilicon sequentially stacked, A first photoresist pattern having a first thickness may be formed on the second inorganic insulating layer to correspond to a portion where the active layer is formed in the switching region, and may correspond to an edge of the gate electrode exposed to the outside of the active layer. Forming second and third photoresist patterns having a second thickness thinner than the first thickness and varying in width from each other; The second inorganic insulating layer exposed to the outside of the first to third photoresist patterns, the pure polysilicon layer, the first inorganic insulating layer, and the impurity polysilicon layer are sequentially removed to form an island in the switching region. Forming a gate electrode, a gate insulating film, a pure polysilicon pattern and an inorganic insulating material pattern of the impurity polysilicon having the same planar area and sequentially stacked; Exposing the edges of the inorganic insulating material pattern to the outside of the first photoresist pattern by removing the second and third photoresist patterns by ashing; By removing the inorganic insulating material pattern exposed to the outside of the first photoresist pattern and the pure polysilicon pattern thereunder, the edge of the gate insulating film is exposed on the gate insulating film and is sequentially stacked having the same planar area as an island shape. Forming an active layer and an inorganic insulating pattern of the pure polysilicon; Removing the first photoresist pattern Method of manufacturing an array substrate comprising a. The method of claim 1, The buffer layer, the impurity amorphous silicon layer, the first inorganic insulating layer, the pure amorphous silicon layer, and the second inorganic insulating layer are continuously formed in the same vacuum chamber through chemical vapor deposition (CVD) equipment. The manufacturing method of the array substrate characterized by the above-mentioned. The method of claim 1, The solid phase crystallization (SPC) process is an array magnetic field crystallization using a thermal crystallization or alternating magnetic field crystallization device through a heat treatment in a temperature atmosphere of 600 ℃ to 800 ℃ Way. The method of claim 1, The barrier pattern, the ohmic contact layer, and the source and drain electrodes are patterned and formed at the same time by performing the same mask process to have the same shape and the same size in planar shape, and have a completely overlapped shape. The method of claim 1, The active layer of the pure polysilicon has a thickness of about 300 mW to 1000 mW, the inorganic insulating pattern has a thickness of about 100 mW to 500 mW, and the interlayer insulating film is formed by adding the thicknesses of each of the gate electrode and the gate insulating layer disposed thereunder. A method of manufacturing an array substrate, characterized in that formed to have a thickness thicker than the thickness. The method of claim 1, The forming of the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line. The forming of the gate wiring may include forming a gate pad electrode connected to one end of the gate wiring, The forming of the second passivation layer having the drain contact hole may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. The forming of the pixel electrode may include forming a gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole and a data auxiliary pad electrode contacting the data pad electrode through the data pad contact hole. Method of manufacturing an array substrate comprising a. A buffer layer formed of an inorganic insulating material on the entire surface of the substrate on which the pixel region and the switching region are defined; A gate electrode and a gate insulating film of polysilicon sequentially stacked in the switching region on the buffer layer in the form of islands; An active layer of pure polysilicon formed in an island shape exposing the edge of the gate insulating film over the gate insulating film; An inorganic insulating pattern having the same planar area as the active layer and completely overlapping the active layer, and preventing a thermal oxide film from forming at an interface of the active layer; An interlayer insulating film formed over the substrate, the active contact hole exposing the active layer on the inorganic insulating pattern and spaced apart from each other, and acting as an etch stopper for a central portion of the active layer;  A barrier pattern of pure amorphous silicon formed in the switching region in contact with the active layer through the active contact hole and spaced apart from each other through the active contact hole; An ohmic contact layer of impurity amorphous silicon formed on the spaced apart barrier pattern, respectively; Source and drain electrodes spaced apart from each other on the spaced apart ohmic contact layer; A data line formed on a boundary of the pixel area over the interlayer insulating layer and connected to the source electrode; A first passivation layer having a gate contact hole exposing the gate electrode to the outside of the inorganic insulating pattern on the data line; A gate wiring formed on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode and crossing the data wiring; A second protective layer having a drain contact hole exposing the drain electrode over the gate line; A pixel electrode formed in the pixel region in contact with the drain electrode through the drain contact hole on the second passivation layer; Array substrate comprising a. The method of claim 8, The gate electrode of the impurity polysilicon has a thickness of 500 mW to 1000 mW, the active layer of pure polysilicon has a thickness of 300 mW to 1000 mW, the inorganic insulating pattern has a thickness of 100 mW to 500 mW, and the barrier pattern is And a thickness of 50 kPa to 300 kPa, wherein the interlayer insulating film is formed to have a thickness thicker than the sum of the thicknesses of each of the gate electrode and the gate insulating film disposed below the interlayer insulating film. The method of claim 9, A gate pad electrode connected to an end of the gate line and a data pad electrode connected to an end of the data line, The second passivation layer includes a gate pad contact hole exposing the gate pad electrode, the second passivation layer includes a data pad contact hole exposing the data pad electrode, A gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole with the same material forming the pixel electrode on the second passivation layer, and data auxiliary contacting the data pad electrode through the data pad contact hole Pad electrode Array substrate comprising a. Sequentially stacking a buffer layer made of an inorganic insulating material, an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer on a substrate on which a pixel region and a switching region are defined; A solid oxide crystallization (SPC) process is performed to crystallize each of the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and a first impurity polysilicon layer, and a thermal oxide film having a first thickness on the pure polysilicon layer. Forming a; A gate electrode and a gate insulating film of impurity polysilicon, which are sequentially stacked and have the same planar area in the switching region, are formed on the switching layer, and the edges of the gate insulating film are exposed on the gate insulating layer, and the same planar area is sequentially formed in the island shape. Forming an active layer and a thermal oxide film pattern of stacked pure polysilicon; An active contact hole is formed by depositing an inorganic insulating material on the entire surface of the thermal oxide layer pattern to form an interlayer dielectric layer, and patterning the interlayer dielectric layer and the thermal oxide layer pattern thereunder to expose both sides of the active layer and spaced apart from each other. Forming a;  A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line connected to the source electrode at a boundary of the pixel region over the interlayer insulating film; A gate contact hole forming a first passivation layer over the data line and the source and drain electrodes, and patterning the first passivation layer, the interlayer insulating layer, and the gate insulating layer to expose the gate electrode outside the active layer; Forming a; Forming a gate wiring on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode through the gate contact hole and crossing the data wiring; Forming a drain contact hole exposing the drain electrode by forming a second passivation layer on the entire surface of the substrate over the gate wiring, and patterning the second passivation layer and a first passivation layer thereunder; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area Method for producing an array substrate comprising a. The method of claim 11, The solid phase crystallization (SPC) process is a thermal crystallization through heat treatment at a temperature of 600 ℃ to 800 ℃ and oxygen (O ₂ ) gas separation or a temperature and oxygen (O ₂ ) gas of 600 ℃ to 700 ℃ An alternating magnetic field crystallization method using an alternating magnetic field crystallization apparatus in an atmosphere. The method of claim 11, And said first thickness is from 50 kPa to 100 kPa. The method of claim 11, The barrier pattern, the ohmic contact layer, and the source and drain electrodes may be formed by simultaneously patterning the same mask process to have the same shape and the same size and have a completely overlapped shape. . The method of claim 11, The active layer of the pure polysilicon has a thickness of about 300 ~ 1000Å, and the interlayer insulating film is formed to have a thickness thicker than the thickness of the sum of the thickness of each of the gate electrode and the gate insulating film disposed thereunder Method of manufacturing a substrate. The method of claim 11, The forming of the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line. The forming of the gate wiring may include forming a gate pad electrode connected to one end of the gate wiring, The forming of the second passivation layer having the drain contact hole may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. The forming of the pixel electrode may include forming a gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole and a data auxiliary pad electrode contacting the data pad electrode through the data pad contact hole. Method of manufacturing an array substrate comprising a.

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