KR20110003678A - Fuse of semiconductor device - Google Patents

Abstract

PURPOSE: The fuse of a semiconductor device is provided to increase net dices by reducing entire chip sizes according to the pitch reduction of the fuse. CONSTITUTION: A plurality of first fuses(11) is formed on a semiconductor substrate. A plurality of second fuses is formed on a layer. The layer on which the second fuses are formed is different from the layer on which the first fuses are formed. A plurality of contacts electrically connects the first fuses and the second fuses. The first fuses and the second fuses include a structure the half of which is cut in a fuse guard ring(10). A first fuse and a second fuse are based on metal wirings.

Description

Fuse of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse of a semiconductor device, and more particularly, to a fuse that is included in a highly integrated semiconductor device and determines whether to transfer an electrical signal or connect two different terminals.

In general, a fuse is defined as a type of circuit breaker that is used to prevent overcurrent from flowing in a line. In other words, the fuse melts itself by the heat generated by the electric current, which can be easily seen in the surrounding life.

Fuses keep current flowing in normal conditions, but if they are blown, they permanently block the flow of current before replacing it with a new one, which is different from a switch that can control the blocking or connection of current flow. have.

The semiconductor device may be operated according to a predetermined purpose by injecting impurities into a predetermined region of a silicon wafer or depositing a new material.

A representative example is a semiconductor memory device. The semiconductor memory device includes many elements such as transistors, capacitors, and resistors to perform a predetermined purpose, and a fuse is one of them.

Fuses are used in various places in semiconductor memory devices, and representative examples thereof include redundancy circuits and power supply circuits. Fuses used in these circuits remain normal in the manufacturing process, but are selectively blown (ie, blown) through various tests after manufacture.

The redundancy circuit will be described in more detail. When a specific unit cell is defective in a semiconductor memory device, a recovery step is performed to replace the spare unit with an extra normal cell.

That is, when an address for accessing a defective unit cell is input from the outside, a recovery step stores the address of the defective unit cell so that the redundant normal cell is accessed instead of the defective unit cell. Do not allow access.

The most commonly used fuse in this recovery phase is a laser blown through the corresponding fuse in the semiconductor device to blow the fuse and permanently break the place where the electrical connection was maintained. This operation is called fuse blowing.

The semiconductor memory device includes a plurality of unit cells, and no one knows where a defective unit cell exists among the plurality of unit cells after the manufacturing process. Therefore, in the semiconductor memory device, a fuse box including a plurality of fuses is provided in order to replace a normal spare unit cell even if a defect occurs in any of the unit cells.

The data storage capability of semiconductor memory devices is increasing. Accordingly, the number of unit cells included therein increases and the number of fuses used to replace an extra unit cell when a defect occurs also increases.

On the other hand, the total area of the semiconductor memory device is reduced and high integration is required. As described above, since some of the plurality of fuses selectively blow a laser to physically blow, it is necessary to maintain a certain distance between the fuses in order not to affect neighboring fuses that are not blown. However, this becomes a factor of lowering the degree of integration of the semiconductor memory device.

1 and 2 are diagrams for describing a fuse in a conventional semiconductor device.

In DRAM, a redundancy cell is used to compensate for a defect of a main cell, and a fuse is used as a means of replacing the defect. The fuses used in the prior art form fuses 2 in a row in a fuse box 1 having a rectangular structure as shown in FIGS. 1 and 2. The fuse 2 to be written is cut using a laser.

In this case, the prior art uses laser energy for fuse cutting. However, in this process, the fuses adjacent to the cutting fuses are damaged due to the diffuse reflection or the explosive force of the laser, thereby causing a defect of the fuses.

That is, the conventional fuse has a problem that the adjacent fuse is damaged as shown in Figure 3a during the blowing of the fuse.

In addition, the semiconductor package is mounted on a substrate, the chip is electrically connected between the chip and the substrate by a wire, and then sealed by an epoxy modulating compound (EMC) to protect the chip and the wire.

However, due to the stress generated when the package coating material or the EMC is injected in the subsequent package process, the fuse 2 collapses as shown in FIG. 3B or the fuse crack as shown in FIG. 3C. There is a problem that occurs.

In addition, the conventional fuse has a limitation in its width in consideration of the definition of the fuse line when setting the pitch. In addition, there is a limitation of the laser spot size and the space between the fuses when blowing the fuse.

Accordingly, there is a limit in reducing the area of the fuse, and there is a problem that it is difficult to increase the net die due to the increase in the chip size.

In order to solve the above-mentioned conventional problems, the present invention has the following object.

First, the fuse line is formed of two layers and the upper layer is arranged to be alternated with the adjacent fuse to prevent damage of the adjacent fuse during blowing.

Secondly, the purpose of the present invention is to prevent damage to the lower layer when blowing the fuse and to minimize the pitch of the fuse.

The fuse of the semiconductor device of the present invention for achieving the above object is a plurality of first fuses formed on top of the semiconductor substrate and arranged alternately on a plane in the fuse box; A plurality of second fuses formed on different layers with the plurality of first fuses and arranged alternately with each other, and arranged adjacent to the plurality of first fuses; And a plurality of contacts electrically connecting the plurality of first fuses and the plurality of second fuses.

The present invention includes a first lower fuse formed on the upper portion of the semiconductor substrate; A second lower fuse formed on the same layer as the first lower fuse and staggered with the first lower fuse on a plane in the fuse box; A first upper fuse formed on an upper layer of the first lower fuse and the second lower fuse and connected to the first lower fuse in a line shape; And a second upper fuse formed on the upper layer and connected to the second lower fuse in a line shape.

The present invention has the following effects.

First, the fuse line is formed of two layers, and the upper layer is alternated with the adjacent fuses to prevent damage of the adjacent fuses when blowing.

Second, to prevent damage to the lower layer during the blowing of the fuse and to minimize the pitch (pitch) of the fuse.

As a result, it is possible to reduce the size of the entire chip due to the pitch of the fuse and increase the net die.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 to 7 are plan views illustrating fuses of a semiconductor device according to example embodiments.

First, as shown in FIG. 4, a lower fuse 11 made of a first metal wiring is formed in a fuse guardring 10 of the fuse box.

Here, the lower fuse 11 forms only half of the fuse line.

That is, the conventional fuse line is formed in an 'I' shape so as to have a length greater than the fuse guard ring 10 on a plane.

However, the lower fuse 11 of the present invention has a '┬' shaped structure because only half of the 'I' shaped fuse line is formed.

In addition, the lower fuse 11 arranged adjacent to the lower fuse 11 having a '⊥' shape has a 'ㅗ' shape.

The lower fuse 11 having a '┬' shape and the lower fuse 11 having a '⊥' shape are arranged adjacent to each other and alternately alternately arranged with each other.

That is, the lower fuse 11 having a '┬' shape and the lower fuse 11 having a '⊥' shape are formed in a zigzag pattern.

As shown in FIG. 5, an interlayer insulating film (not shown) is formed on the lower fuse 11, and a contact hole (not shown) is formed by selectively etching the interlayer insulating film (not shown).

Subsequently, a contact hole (not shown) is filled with a conductive material to form a contact 12 electrically connected to a second metal wiring, which will be described later, on the lower fuse 11.

Subsequently, as shown in FIG. 6, an upper fuse 13 is formed on the upper layer of the lower fuse 11 to be electrically connected to the contact 12.

Here, the upper fuse 13 is preferably made of a second metal wiring.

In addition, the upper fuse 13 is a part that is substantially blown during the fuse blowing process.

The upper fuse 13 of the present invention has a '┬' shaped structure because only half of the 'I' shaped fuse line is formed.

In addition, the upper fuse 13 arranged adjacent to the upper fuse 13 having a '⊥' shape has a 'ㅗ' shape.

The upper fuse 13 in the '┬' shape and the upper fuse 13 in the '⊥' shape are arranged adjacently and alternately alternately arranged with each other.

That is, the upper fuse 13 having a '┬' shape and the upper fuse 13 having a '⊥' shape are formed in a zigzag pattern.

According to the present invention, since the upper fuse 13 and the lower fuse 11 are formed in different layers on one fuse line, a multilayer fuse structure is formed.

In this case, the lower fuse 11 and the upper fuse 13 formed on different layers are disconnected from each other and electrically connected to each other by the contact 12.

That is, the plurality of upper fuses 13 and the plurality of lower fuses 11 are arranged to be staggered in different directions to correspond one-to-one.

Next, as shown in FIG. 7, an interlayer insulating film (not shown) is formed on the entire upper surface of the upper fuse 13 and the lower fuse 11.

The interlayer insulating film (not shown) is selectively etched to form a contact hole (not shown).

Subsequently, a contact hole (not shown) is filled with a conductive material to form a contact 14 for connecting the fuse to the upper side of the upper fuse 13 and the lower fuse 11.

According to the present invention, the fuse line is formed in two layers of the lower fuse 11 and the upper fuse 13, and the upper fuse 13 is alternately arranged alternately with the adjacent upper fuse 13.

That is, the fuse F1 and the fuse F2 are arranged adjacent to each other on the top view.

For example, the fuse F1 has an upper fuse 13 formed at an upper side thereof and a lower fuse 11 formed at a lower side thereof.

At this time, the fuse F1 is formed in the upper fuse 13 and the lower fuse 11 in different layers, but has a structure that is connected in the form of a line on the top view.

On the contrary, in fuse F2, a lower fuse 11 is formed on an upper side, and an upper fuse 11 is formed on a lower side of the fuse F2.

In this case, the fuse F2 has the lower fuse 11 and the upper fuse 13 formed on different layers, but have a structure in which the fuse F2 is connected in a line shape on a plan view.

In addition, when the redundancy cell is replaced to remedy the defective cell, the upper fuse 13 is blown as in (A).

At this time, when the fuse is blown, the upper fuse 13 becomes a substantially blowing point, so that damage does not occur in a layer of the adjacent lower fuse 11 as in (B).

In the present invention, the blown upper fuse 13 is described as an embodiment, but the present invention is not limited thereto, and the lower fuse 11 is blown, or both the upper fuse 13 and the lower fuse 11 are both. Can also be blown.

In addition, when the upper fuse 13 is blown as shown in (A), the adjacent upper fuse 13 is alternately arranged as in (C) so that damage does not occur in the adjacent upper fuse 13.

In the present invention, since the upper fuse 13 and the lower fuse 11 are alternately arranged in different layers, the pitch D of the fuse is not largely limited to the allowable limit of the processing capability.

Accordingly, the pitch of the fuse including the width of the fuse and the space between the fuses may be minimized.

1 and 2 are diagrams for explaining a fuse in a conventional semiconductor device.

3A to 3C are diagrams for describing a problem of the fuse shown in FIGS. 1 and 2.

4 to 7 are plan views illustrating a fuse in a semiconductor device according to an embodiment of the present invention.

Claims (12)

A plurality of first fuses formed on the semiconductor substrate and alternately arranged alternately on a plane in the fuse box; A plurality of second fuses formed on different layers with the plurality of first fuses and alternately arranged alternately with each other and arranged adjacent to the plurality of first fuses; And And a plurality of contacts electrically connecting the plurality of first fuses and the plurality of second fuses. The fuse of claim 1, wherein the plurality of first fuses and the plurality of second fuses have a structure in which half of the fuses are disconnected in the fuse guard ring. The fuse of claim 1 or 2, wherein the plurality of first fuses are arranged in a '┬' shape structure and a '⊥' shape structure repeatedly. The fuse of claim 1 or 2, wherein the plurality of second fuses are arranged in a '⊥' shape structure and a '┬' shape structure repeatedly. The fuse of claim 1, wherein the plurality of first fuses and the plurality of second fuses are arranged to be staggered in different directions to correspond one-to-one. The fuse of claim 1, wherein the plurality of second fuses are formed on the plurality of first fuses. The fuse of claim 1 or 6, wherein the plurality of second fuses become a blowing point during a blowing process of the fuse. The fuse of claim 1, wherein the first fuse and the second fuse are formed of metal wires. A first lower fuse formed on an upper portion of the semiconductor substrate; A second lower fuse formed on the same layer as the first lower fuse and alternate with the first lower fuse on a plane in a fuse box; A first upper fuse formed on an upper layer of the first lower fuse and the second lower fuse and connected to the first lower fuse in a line shape; And And a second upper fuse formed in the upper layer and connected to the second lower fuse in a line shape. The method of claim 9, A first contact connecting the first lower fuse and the first upper fuse; And And a second contact connecting the second lower fuse and the second lower fuse. 10. The fuse of claim 9, wherein the first lower fuse, the second lower fuse, the first upper fuse, and the second upper fuse have a structure in which the fuse is cut off in the fuse guard ring. 10. The fuse of claim 9, wherein the first upper fuse and the second upper fuse become a blowing point during a blowing process of the fuse.

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