KR20110002142A - Dvr and video-channel scalable digital video recording system using the same - Google Patents

Abstract

PURPOSE: A DVR and a video-channel scalable digital video recording system using the same are provided to easily extend a DVR video channel by operating digital video recorders in the same timing through the same video sync signal. CONSTITUTION: A sync signal generating/inputting unit(310) separates a sync signal and clock signal from an LVDS(Low-Voltage Difference Signaling) signal, and a video data synthesizing unit(330) synthesizes external video data and a video activating flag of a DVR(Digital Video Recorder) of a previous terminal with synchronized internal video data and an internal video activating flag. A serial converter(340) converts the synthesized video data of parallel data type of the video data synthesizing unit into serial data.

Description

Digital video recorder device and digital video recording system capable of video channel extension using the same {DVR and video-channel scalable digital video recording system using the same}

The present invention relates to channel expansion of a digital video recorder (hereinafter referred to as 'DVR'), and more particularly, to a DVR device and a digital video recording system capable of expanding a video channel using the same.

Conventional DVR generally refers to a device for recording, storing, retrieving, and transmitting 4, 8 (9), and 16 channels to a network, and is a core of video surveillance equipment, but supports only limited video input channels.

In general, DVR uses less than 16 channels, and two approaches have been used to support an area requiring more than 16 channels of camera. The first method is to design more than 32 and 64 channels of video input in DVR system. Although there are some of these products, except for the drawback of developing a separate DVR for each channel, the expansion of more than 32 channels in the DVR system increases the complexity due to the concentration of large-capacity video data, the difficulty of implementation, and the increase of instability. In addition, there is a problem of durability due to heat problems, it is difficult to practical commercialization. The second way to overcome this is to connect an 8 (9) / 16 channel DVR to an internet protocol (IP) based network and use a central monitoring system (CMS) to monitor a personal computer (PC). It has been connected to DVR for centralized monitoring and management. 1 is a diagram illustrating a multi-channel expansion method using a CMS method as a second method in the related art. Here, Cxy means the y th video channel of DVR [x].

The conventional method of FIG. 1 transmits video data compressed in MPEG-4 / H.264, etc. from M N-channel DVRs 110 to a personal computer (PC) 120 through a network together with information such as recording time and alarm. do. The PC 120 restores the transmitted compressed video data and displays the desired shape on the monitor 122 to provide the user with the unified surveillance video and various information. However, in the above scheme, the PC 120 may experience an excessive load on MPEG-4 / H.264 video reconstruction, especially when the compressed transmission video is D1 (704 × 480) high resolution high speed (30 fr / sec). The disadvantage is the use of a high-performance PC. In addition, a screen delay occurs due to the construction of a real-time screen by restoring the compressed video, and has a disadvantage in that real-time monitoring is difficult due to a low screen update rate. As a result, some sites use expensive video matrix switches. This approach is very costly due to added PC and network equipment or video matrix switches for unified management.

The present invention is to solve the conventional problems as described above, by daisy-chaining M N-channel DVR to a high-speed serial channel, by implementing a video channel expansion by implementing to be N x M channel DVR It is an object of the present invention to provide a possible DVR device and a digital video recording system using the same.

In order to achieve the above object, a digital video recorder apparatus according to an aspect of the present invention generates a synchronization signal and a clock signal or receives an LVDS signal from a digital video recorder of a previous stage and separates the synchronization signal and the clock signal from the LVDS signal. A synchronization signal generation / input unit; A video data generator for generating internal video data synchronized with a video activation indicator in accordance with the video signal and the video data generated or synthesized by the digital video recorder of the previous stage included in the LVDS signal according to the synchronization signal; A video data synthesizing unit for synthesizing the external video data and the video activation flag of the previous stage digital video recorder with the synchronized internal video data and the internal video activation flag from the video data generator; A serial converter for converting the composite video data in the form of parallel data from the video data synthesizing unit into serial data and transmitting the serial video data to a next digital video recorder; And a controller for controlling the operation of the synchronization signal generator / input unit, the video data generator, the video data synthesizer, and the serial converter.

According to another aspect of the present invention, a video channel expandable digital video recording system sequentially connects a plurality of digital video recorders for multiple channels through a high speed serial channel, and an output terminal of the first digital video recorder is connected to a monitor. 2 The output terminals of the digital video recorder to the N-th digital video recorder are connected to the input terminals of the digital video recorder of the next stage, and according to the synchronization signal, The video data generated or synthesized by the digital video recorder is synthesized by the video data generated by the digital video recorder of the present stage. The synthesized video data is transmitted to the monitor and synchronously displayed on one screen. do.

According to the present invention, the DVR [1], DVR [2], and DVR [N] are operated at the same timing with the same video synchronization signal, so that the connected DVR operates as if it is one DVR, thereby easily expanding the DVR video channel. can do. For example, if DVR [n, n = 1, 2, N] is implemented with 4 channels, 4, 8, 4 × N channels of DVR are possible, and if 8 channels are implemented, 8, 16,, 8 × N It is possible to form a DVR of a channel. This expansion method can operate with PLUG-N-PLAY, which is automatically configured when connecting high-speed serial channels, and does not develop DVRs for each of 4, 8 (9), 16, and 32 channels separately. Innovative reductions in development costs, development maintenance costs and production management costs are possible. Compared to the 4, 8 (9), 16, 32 channel DVR separately developed and supplied by the present invention it is possible to supply at a cost of arithmetic 1/4.

In addition, an effect of the present invention is that an external memory (DRAM) is not used in the process of transmitting partial video data from the DVR [N] to the DVR [1]. In general, since the external video input and the internal video synchronization signal do not coincide with each other during video synthesis, an external memory for temporarily storing video data is used. Such video external memory is commonly referred to as frame memory. In the case of using such a frame memory, an expensive field programmable gate array (FPGA) having a large number of logic gates is used to deal with the complexity and cost of the entire system. In contrast, the present invention can generate video data signals by matching each system to video synchronization signals, and synthesize them in stages, and select a possible method to synthesize video with simple logic such as MUX and AND gate.

In addition, since the compressed image is not transmitted and restored as compared with the conventional method, the screen delay does not occur. Since the screen is updated in real time, the matrix video switch equipment required for the real-time monitoring is not required, and the high performance PC and IP network equipment are not required.

Hereinafter, a digital video recording system capable of extending a video channel according to an embodiment of the present invention will be described in detail with reference to the accompanying example drawings. 2 is a diagram illustrating a digital video recording system capable of extending a video channel according to an embodiment of the present invention.

Referring to FIG. 2, a digital video recording system capable of expanding a video channel according to an exemplary embodiment of the present invention connects a plurality of digital video recorders 210 sequentially through a high speed serial channel, and a first digital video recorder DVR [1]. ] Is connected to the monitor 220, and each output of the second digital video recorder DVR [2] to the Nth digital video recorder DVR [N] is connected to an input of the next digital video recorder, and the synchronization signal According to the N-th digital video recorder DVR [N] from the first digital video recorder DVR [1], the video data generated or synthesized by the digital video recorder of the previous stage may be changed by the digital video recorder of the current stage. The synthesized video data is transmitted to the monitor 220 by synthesizing the generated video data and synchronously displayed on one screen. The ray. The high speed serial channel may use methods such as low-voltage difference signaling (LVDS) or common-mode logic (CML). In the present invention, a low voltage difference signal (LVDS) is used as a transmission method. Here, the auxiliary monitor 212 means that it can be used to increase the monitoring efficiency. The signal is also unidirectionally transmitted from the N-th digital video recorder DVR [N] to the first digital video recorder DVR [1].

3 is a detailed block diagram of each DVR device shown in FIG. 2.

Each of the plurality of DVRs includes: a synchronization signal generator / input unit 310, a video data generator 320, a video data synthesizer 330, a serial converter 340, and a controller 350.

The synchronizing signal generation / input unit 310 generates a synchronizing signal and a clock signal or receives an LVDS signal from a digital video recorder of a previous stage and separates the synchronizing signal FSYNC and the clock signal LCLK from the LVDS signal. FIG. 6 is a diagram illustrating an example of the synchronous video generation / input device 310 illustrated in FIG. 3, and a deserialization chip may be used as a device that performs the reverse of the serial converter 340. In FIG. 6, P (N-1) and N (N-1) represent P (N-1) and N (N-1) of FIG. 8. When LVDS is used, transmission is possible up to 3 Gbps.

The video data generator 320 may generate internal video data synchronized with a video activation indicator by synchronizing the video data generated by the previous stage digital video recorder included in the LVDS signal and the internal video data with the synchronization signal. Occurs.

The video data synthesizing unit 330 synchronizes the external video data EVD and the video activation flag EVV_flag and the external guitar flag EO_flag of the previous stage of the digital video recorder from the video data generator 320. It synthesizes with the internal video data IVD, the internal video activation flag IVV_flag, and the internal other flag IO_flag.

The serial converter 340 converts the composite video data in the form of parallel data from the video data synthesizing unit 330 into serial data and transmits the serial video data to the next digital video recorder.

The controller 350 controls operations of the sync signal generator / input unit 310, the video data generator 320, the video data synthesizer 330, and the serial converter 340. In FIG. 3, EVD (N) and IVD (N) refer to external video data and internal video data of DVR [N].

The controller 310 selects initial values of the synchronization signal generator / input unit 310, the video data generator 320, the video data synthesizer 330, and the serial converter 340 by using a loaded program, and activates each device. do. When there is no external LVDS signal, the activated sync signal generator / initiator 310 generates the sync signal shown in FIG. 4 and applies it to the screen divider 334 of the sync signal generator / input device 320. If is present, VCLK and FSYNC are converted from LVDS to TTL / CMOS signal. The VCLK and FSYNC signals are generated by the DVR [N] in FIG. 2 and transmitted to the DVR [1].

The video sync signal used is the video clock VCLK and the field sync signal FSYNC. In general, VCLK uses 27 MHz for SD (Standard Definition) video and 74.25 MHz (30 fr / sec) or 148.5 MHz (60 fr / sec) for HD (high definition), but other clocks Can be used. The FSYNC is used to determine the timing indicating the start of the video, and is transmitted to the DVR of the next stage as a daisy-chained signal through the synchronous screen transmission apparatus 350 as a 1 CLK delayed signal. The 1 CLK delay is intended to compensate for the 1 CLK delay that occurs during video synthesis, which will be described later.

The DVR of the next stage uses the transmitted VCLK if there is a transmitted VCLK and the self-generated VCLK if it does not exist as the main video processing clock. FSYNC is used to create horizontal sync (HSYNC) and vertical sync (VSYNC), and the vertical sync and horizontal sync are generated as shown in FIG. 5 in synchronization with the FSYNC inputted by each DVR.

In FIG. 5, A and B mean that a change in rounding of VSYNC and HSYNC occurs at a value determined at a rising edge of FSYNC. VSYNC and HSYNC are used to create and control rectangular screens.

The screen divider 324 of the video data generator 320 received a command from the controller 350 creates a real-time split screen from a video signal (internal video signal) directly connected to the DVR. During the search, the controller 350 searches for and restores the recorded screen on the HDD and sends it to the screen generating device. The video data generation unit 320 synchronizes the above two types of video data, namely, external video data and internal video data from a previous DVR, with the video activation indicator VV_flag in accordance with the video horizontal and vertical synchronization. Occurs. The indicator may include a time synchronization indicator and a PL (search / real time) indicator for time synchronization. FIG. 7 shows the DVR [N] of the N-level and the DVR [N-1] of the (N-1) step. The N-level DVR [N] shows the first quadrant and the DVR of the (N-1) step. N-1] shows a signal waveform diagram when the second quadrant is activated. The signal at the bottom of FIG. 7 shows the state of the signal at the time indicated by C. FIG.

FIG. 7 is a signal waveform of video data activation indicator and video data outputted by the screen generator illustrated in FIG. 3, and the signal HSYNC (N) and the signal HSYNC (N-1) differ by 1 CLK. To compensate for the 1 CLK delay.

FIG. 8 is a circuit diagram illustrating a logic circuit as an example of the video synthesis unit illustrated in FIG. 3. In FIG. 8, a thick line represents a vector component. (N) represents the signal of DVR [N].

The video data synthesis unit 330 includes a first D flip-flop 810, a multiplexer 820, an OR gate 830, a first D flip-flop 840, and a second D flip-flop 850. It includes.

The first D flip-flop 810 delays the sync signal from the sync signal generator / input unit 310 in synchronization with the clock signal from the sync signal generator / input unit 310.

The multiplexer 820 receives the video data and the internal video data from the digital video recorder of the previous stage and outputs the video data and the video data generator of the previous stage according to the logic level of the video activation flag of the previous stage input to the selection terminal. One of the internal video data from 320 is selected and output.

OR gate 830 ORs the video activation flag and the internal video activation flag from the previous stage of the digital video recorder.

The first D flip-flop 840 delays the output of the multiplexer by one clock in synchronization with the clock signal VCLK.

The second D flip-flop 850 delays the output of the OR gate 720 in synchronization with the clock signal VCLK.

In FIG. 8, video data, that is, external video data EVD and internal video data IVD are input to an input terminal of a multiplexer MUX 710, and a selection terminal of the MUX 710 is input to an external video activation flag EVV_flag. Is connected by. All the activation flags are synthesized by the AND gate 720, and the synthesized video data and the flag signal are sent to the synchronous screen transmitting apparatus 350 using the D-delay 730.

The synchronous video signal bus represents (1 CLK delayed synthesized video data, 1 CLK delayed synthesized video activation indicator, 1 CLK delayed other indicator, 1 CLK delayed FSYNC, VCLK), and the serial converter 340, which is a synchronous video transmission device, After converting the synchronous video signal bus to LVDS transmission method, the device transmits the synchronous video signal bus to the next (N-1) DVR. A simple serialization chip (SERIALIZER IC) is used that converts parallel data into high-speed serial data and transmits it as an LVDS signal.

9 shows video data, i.e., VCLK (N-1), FSYNC (N-1), EVV_flag (N-1), EO_flag (N-1), EVD (N-1) from P (N) and N (N). ) Is shown as a waveform of the process of restoring. VCLK (N) and VCLK (N-1) are the same clock with only phase differences.

The video data synthesized in the manner described above is continuously transmitted from step N to step (N-1), and this transmission is terminated in the DVR of step 1. In the first stage, the video data synthesized in the final stage constitutes a complete screen, or the portion where the video activation indicator is not activated is displayed in a designated color of black or blue to finally synthesize the completed video.

FIG. 10 illustrates an example of a process of obtaining a completed video by connecting three DVRs, that is, DVR [1], DVR [2], and DVR [3]. In Fig. 10, the hatched portion means the activated area. DVR [3] activates the right two zones indicated by the number 3, DVR [2] generates the upper middle zone indicated by the number two, and the two right video are transmitted from DVR [3]. Synthesize and transmit to DVR [1]. The DVR [1] is a final step in the video data transmitted from the DVR [2], that is, the video data of the parts indicated by numbers 2 and 3 and the video data generated inside the DVR [1], that is, displayed on the part indicated by the number 1. The video data is synthesized to produce a complete video picture.

The completed video screen is displayed on the monitor 220 via a digital-to-analog converter (not shown).

Although the present invention has been described as a specific preferred embodiment, the present invention is not limited to the above-described embodiments, and the present invention is not limited to the above-described embodiments without departing from the gist of the present invention as claimed in the claims. Anyone with a variety of variations will be possible.

The digital video recorder device and a digital video recording system capable of extending a video channel using the same may be used for a surveillance camera system such as a CCTV camera system.

1 is a diagram illustrating a multi-channel extension method using a CMS method.

2 is a diagram illustrating a digital video recording system capable of extending a video channel according to an embodiment of the present invention.

3 is a detailed block diagram of each DVR shown in FIG. 2.

FIG. 4 is a diagram illustrating a video synchronization signal and a clock signal used for each DVR of FIG. 3.

FIG. 5 is a view illustrating video vertical and horizontal synchronization signals synchronized to the video synchronization signal shown in FIG. 4.

FIG. 6 is a diagram illustrating an example of a synchronous video generation / input device illustrated in FIG. 3.

7 is an activation indicator of video data and a signal waveform of video data output by the screen generator illustrated in FIG. 3.

FIG. 8 is a circuit diagram illustrating a logic circuit as an example of the video synthesis unit illustrated in FIG. 3.

9 is a timing diagram illustrating a video data reconstruction process according to an embodiment of the present invention.

10 is a diagram illustrating an example of synthesizing a screen by connecting three DVRs according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

310: sync signal generation / input unit

320: video data generator

332: M channel video input

324: screen splitter

326: memory

330: video data synthesis unit

340: serial converter

350: control unit

810: First D flip-flop

820: multiplexer

830: or gate

840: second D flip-flop

850: third D flip-flop

Claims (5)

A synchronization signal generation / input unit 310 for generating a synchronization signal and a clock signal or receiving an LVDS signal from a previous digital video recorder and separating the synchronization signal and the clock signal from the LVDS signal; The video data generator 320 generating internal video data synchronized with a video activation indicator by synchronizing the video data and internal video data generated or synthesized by the digital video recorder of the previous stage included in the LVDS signal with the synchronization signal. ); A video data synthesizing unit 330 for synthesizing the external video data and the video activation flag of the previous stage digital video recorder with the synchronized internal video data and the internal video activation flag from the video data generator; A serial converter 340 for converting the composite video data in the form of parallel data from the video data synthesizing unit 330 into serial data and transmitting the serial data to a digital video recorder in a next stage; And Digital video recorder including a control unit 350 for controlling the operation of the synchronization signal generator / input unit 310, the video data generator 320, the video data synthesis unit 330, and the serial converter 340 Device. The method of claim 1, wherein the screen synthesizing unit A first D flip-flop (810) for delayed outputting the synchronization signal from the synchronization signal generation / input unit (310) in synchronization with the clock signal from the synchronization signal generation / input unit (310); The video data of the previous stage and the internal video from the video data generator according to the logic level of the video activation flag of the previous stage that receives the video data and the internal video data from the digital video recorder of the previous stage and is input to the selection terminal. A multiplexer 720 for selecting and outputting one of the data; An OR gate 730 for ORing the video activation flag and the internal video activation flag from the previous stage's digital video recorder; A first D flip-flop (740) for delaying the output of the multiplexer in synchronization with the clock signal; And And a second D flip-flop (750) for delaying the output of the OR gate (720) in synchronization with the clock signal. A plurality of digital video recorders for multiple channels are sequentially connected through a high speed serial channel, the output end of the first digital video recorder is connected to the monitor, and each output end of the second digital video recorder to the Nth digital video recorder is connected to the next stage. A video data generated or synthesized by a digital video recorder of a previous stage in order from the N-th digital video recorder to the first digital video recorder in accordance with the synchronization signal and connected to an input of a digital video recorder. A digital video recording system capable of extending a video channel for synthesizing the video data generated by a video recorder and transmitting the synthesized video data to the monitor and displaying them synchronously on one screen. The plurality of DVRs are each: A synchronization signal generation / input unit 310 for generating a synchronization signal and a clock signal or receiving an LVDS signal from a previous digital video recorder and separating the synchronization signal and the clock signal from the LVDS signal; The video data generator 320 generating internal video data synchronized with a video activation indicator by synchronizing the video data and internal video data generated or synthesized by the digital video recorder of the previous stage included in the LVDS signal with the synchronization signal. ); The video data synthesizing unit 330 for synthesizing the external video data EVD and the video activation flag of the previous stage digital video recorder with the synchronized internal video data IVD and the internal video activation flag from the video data generator. ; A serial converter 340 for converting the composite video data in the form of parallel data from the video data synthesizing unit 330 into serial data and transmitting the serial data to a digital video recorder in a next stage; And Digital video expandable digital video including a control unit 350 for controlling the operation of the synchronization signal generator / input unit 310, the video data generator 320, the video data synthesizer 330, and the serial converter 340 Recording system. The method of claim 1, wherein the screen synthesizing unit A first D flip-flop (810) for delayed outputting the synchronization signal from the synchronization signal generation / input unit (310) in synchronization with the clock signal from the synchronization signal generation / input unit (310); The video data of the previous stage and the internal video from the video data generator according to the logic level of the video activation flag of the previous stage that receives the video data and the internal video data from the digital video recorder of the previous stage and is input to the selection terminal. A multiplexer 720 for selecting and outputting one of the data; An OR gate 730 for ORing the video activation flag and the internal video activation flag from the previous stage's digital video recorder; A first D flip-flop (740) for delaying the output of the multiplexer in synchronization with the clock signal; And And a second D flip-flop (750) for delaying the output of the OR gate (720) in synchronization with the clock signal.

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