KR20110001167A - Embedded semiconductor package and method of manufacturing the same - Google Patents
Embedded semiconductor package and method of manufacturing the same Download PDFInfo
- Publication number
- KR20110001167A KR20110001167A KR1020090058572A KR20090058572A KR20110001167A KR 20110001167 A KR20110001167 A KR 20110001167A KR 1020090058572 A KR1020090058572 A KR 1020090058572A KR 20090058572 A KR20090058572 A KR 20090058572A KR 20110001167 A KR20110001167 A KR 20110001167A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive resin
- wiring
- insulating member
- bump
- semiconductor chip
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 229920005989 resin Polymers 0.000 claims abstract description 76
- 239000011347 resin Substances 0.000 claims abstract description 76
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 15
- 238000007747 plating Methods 0.000 claims description 8
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 claims description 7
- 239000004593 Epoxy Substances 0.000 claims description 6
- 230000009969 flowable effect Effects 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
Landscapes
- Engineering & Computer Science (AREA)
- Wire Bonding (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
Abstract
An embedded semiconductor package and a method of manufacturing the same are disclosed. An embedded semiconductor package includes a semiconductor chip having a bonding pad disposed on an upper surface thereof, a bump disposed on the bonding pad, an insulating member having an opening covering the upper surface and exposing a portion of the bump, and a portion of which is connected to the bump through the opening. The remaining portion is electrically connected and disposed on the insulating member, and includes a conductive resin wiring including a conductor and a resin and a metal wiring disposed on the conductive resin wiring.
Description
The present invention relates to an embedded semiconductor package and a method of manufacturing the same.
Recently, semiconductor packages including semiconductor chips and semiconductor chips capable of storing massive data and processing massive data in a short time have been developed.
Recently, embedded packages in which semiconductor chips are embedded in a substrate have been developed. Embedded packages are used for various purposes such as significantly reducing the size of semiconductor packages and preventing damage to semiconductor chips.
In the conventional embedded package, in order to embed the semiconductor chip in the substrate, the semiconductor chip is attached to the printed circuit board to expose the pad of the semiconductor chip, the semiconductor chip is covered with a dielectric material, and the pad of the semiconductor chip is exposed through laser drilling, pad plating and the like. It is electrically connected to the pad and requires a process of forming a circuit pattern on the dielectric material.
However, such a conventional embedded package exposes the pad of the semiconductor chip by a laser drilling process, which is difficult to apply when the pad gap of the semiconductor chip is very narrow, and has a disadvantage in that the process is very complicated and the number of processes is large.
In order to solve the problem of the embedded package, bumps are formed on the bonding pads, and then, the resin chips are thermocompressed to a resin coated copper (RCC) substrate coated on a copper substrate. At this time, the copper substrate of the RCC substrate is in electrical contact with the bumps, and the copper substrate and the bumps are simply in contact with each other. Thereafter, the copper substrate of the RCC substrate is patterned to form a circuit pattern on the resin.
However, the improved embedded package has a problem in that the circuit patterns and the bumps are easily disconnected due to the deformation of the resin or the distortion of the semiconductor chip because the circuit patterns of the bumps are simply in contact.
One object of the present invention is to provide an embedded semiconductor package which can have a shorter manufacturing process than the conventional embedded package and can prevent the disconnection of bumps and wires.
Another object of the present invention to provide a method of manufacturing the embedded semiconductor package.
An embedded semiconductor package according to the present invention includes a semiconductor chip having a bonding pad disposed on an upper surface thereof, a bump disposed on the bonding pad, an insulating member having an opening covering the upper surface and exposing a portion of the bump, and a portion of the opening. The remaining portion includes a conductive resin wiring including a conductor and a resin and a metal wiring disposed on the conductive resin wiring, the electrical wiring being electrically connected to the bump through the remaining portion.
The conductive resin wiring of the embedded semiconductor package is an embedded semiconductor package comprising any one of a conductive epoxy, an anisotropic conductive film and PEDOT.
The metal line of the embedded semiconductor package includes a plating layer.
A method of manufacturing an embedded semiconductor package according to the present invention includes manufacturing a semiconductor chip having a bonding pad formed on an upper surface thereof, forming bumps on the bonding pads, and insulating members having openings exposing portions of the bumps. Disposing on the top surface of the semiconductor chip, a conductive resin material having a conductor and a resin, a part of which is electrically connected with the bump through the opening and the other part of which is formed on the insulating member Forming a metal wiring on the conductive resin wiring;
The forming of the insulating member on the upper surface of the semiconductor chip may include disposing a metal plate and a preliminary insulating substrate attached to a bottom surface of the metal plate and facing the bumps on the top surface of the semiconductor chip. Contacting the bump and the metal plate by thermal compression on the upper surface, and removing the metal plate from the preliminary insulating substrate.
The forming of the conductive resin wiring may include disposing a mask substrate having a through hole exposing the bump on the insulating substrate, filling the through hole with a flowable conductive resin material disposed on the mask substrate, and Curing the flowable conductive resin material.
In the step of forming the metal wiring, the metal wiring is formed by a plating process.
According to an aspect of the present invention, there is provided a method of manufacturing an embedded semiconductor package, the method including: manufacturing a semiconductor chip having a bonding pad formed on an upper surface thereof, forming a bump on the bonding pad, and insulating insulation having an opening exposing a portion of the bump. Forming on the upper surface of the semiconductor chip and the conductive resin wiring formed on the release film and the metal wiring disposed on the conductive resin wiring on the insulating member by a transfer method to form the conductive resin wiring and the bump The method of manufacturing an embedded semiconductor package comprising the step of electrically connecting.
The conductive resin wiring is formed of any one of a conductive epoxy, a PEDOT, and an anisotropic conductive film.
According to the present invention, not only the adhesion between the wiring and the bump in the embedded semiconductor package can be greatly improved, but the size of the embedded semiconductor package can be greatly reduced.
Hereinafter, an embedded semiconductor package and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and is commonly known in the art. Persons having the present invention may implement the present invention in various other forms without departing from the spirit of the present invention.
1 is a cross-sectional view illustrating an embedded semiconductor package according to an embodiment of the present invention.
Referring to FIG. 1, the embedded
The
Inside the
The
The
The
A portion of the
In the present embodiment, the
The
The
2 to 5 are cross-sectional views illustrating a method of manufacturing an embedded semiconductor package according to an embodiment of the present invention.
2, in order to manufacture an embedded semiconductor package,
A plurality of
Subsequently, the preliminary
Subsequently, heat and / or pressure is applied to the preliminary
Subsequently, the
Referring to FIG. 4, after the insulating
After the
The flowable
Thereafter, the
After the
Thereafter, the
6 to 8 are cross-sectional views illustrating an embedded semiconductor package according to another exemplary embodiment of the present invention.
Referring to FIG. 6, in order to manufacture an embedded semiconductor package,
A plurality of
Subsequently, the preliminary insulating member and the release film 38 disposed on the preliminary insulating member are aligned with the portion facing the
Subsequently, heat and / or pressure is applied to the preliminary insulating
The release film 38 is then removed from the insulating
Referring to FIG. 7, after the insulating
In the present embodiment, the
After the
In this embodiment, the anisotropic film included in the
Subsequently, the
As described in detail above, in the embedded semiconductor package, not only the adhesion between the wiring and the bumps may be greatly improved, but also the size of the embedded semiconductor package may be greatly reduced.
In the detailed description of the present invention described above with reference to the embodiments of the present invention, those skilled in the art or those skilled in the art having ordinary knowledge in the scope of the present invention described in the claims and It will be appreciated that various modifications and variations can be made in the present invention without departing from the scope of the art.
1 is a cross-sectional view illustrating an embedded semiconductor package according to an embodiment of the present invention.
2 to 5 are cross-sectional views illustrating a method of manufacturing an embedded semiconductor package according to an embodiment of the present invention.
6 to 8 are cross-sectional views illustrating a method of manufacturing an embedded semiconductor package in accordance with another embodiment of the present invention.
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20090058572A KR101088820B1 (en) | 2009-06-29 | 2009-06-29 | Embedded semiconductor package and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20090058572A KR101088820B1 (en) | 2009-06-29 | 2009-06-29 | Embedded semiconductor package and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20110001167A true KR20110001167A (en) | 2011-01-06 |
KR101088820B1 KR101088820B1 (en) | 2011-12-01 |
Family
ID=43609766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR20090058572A KR101088820B1 (en) | 2009-06-29 | 2009-06-29 | Embedded semiconductor package and method of manufacturing the same |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR101088820B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9209150B2 (en) | 2013-06-13 | 2015-12-08 | SK Hynix Inc. | Embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same |
KR102407050B1 (en) * | 2020-12-10 | 2022-06-10 | 루센트엘앤디 주식회사 | Method for Transferring a Large Amount of Interconnecting Materials for Micro LEDs |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100771319B1 (en) | 2006-05-15 | 2007-10-29 | 삼성전기주식회사 | Embedded chip printed circuit board and fabricating method of the same |
KR100775583B1 (en) | 2006-10-02 | 2007-11-09 | 주식회사 코리아 인스트루먼트 | A probing needle part for probe card and a probe card having thereof |
-
2009
- 2009-06-29 KR KR20090058572A patent/KR101088820B1/en not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9209150B2 (en) | 2013-06-13 | 2015-12-08 | SK Hynix Inc. | Embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same |
KR102407050B1 (en) * | 2020-12-10 | 2022-06-10 | 루센트엘앤디 주식회사 | Method for Transferring a Large Amount of Interconnecting Materials for Micro LEDs |
Also Published As
Publication number | Publication date |
---|---|
KR101088820B1 (en) | 2011-12-01 |
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