KR20100129077A - Power on reset circuit and memory device having the same - Google Patents

Abstract

PURPOSE: A power on reset circuit and a memory device having the same are provided to prevent an error and initial operation by outputting a power on reset signal after power voltage is stable. CONSTITUTION: A discharge unit(314) discharges a reference voltage for a predetermined time. A discharge controller(315) outputs a discharge control signal to control the discharge unit. A reference voltage generator(311) divides power voltage to generate the reference voltage. An output unit(313) outputs a power on reset signal and includes first and second inverters(IN10-IN40).

Description

Power on reset circuit and semiconductor device having same {Power on reset circuit and memory device having the same}

The present invention relates to a power-on reset circuit for generating a power-on reset signal and a semiconductor device having the same.

The semiconductor device includes a power on reset circuit that generates a power on reset signal (POR). The malfunction of the semiconductor device is prevented by generating a power-on reset signal at the start of the power supply and initializing the internal circuit.

The power-on reset circuit is to protect the semiconductor device from unexpected malfunctions from significant initial voltage changes.

1 shows a power on reset circuit.

Referring to FIG. 1, the power on reset circuit 100 includes a reference voltage generator 110, a voltage detector 120, and an output unit 130.

The reference voltage generator 110 includes a first PMOS transistor P1 and a first resistor R1, and the voltage detector 120 includes a second PMOS transistor P2 and first and second NMOS transistors N1. , N2). The output unit 130 includes first to fourth inverters IN1 to IN4.

In the reference voltage output unit 110, since the gate of the first PMOS transistor P1 is connected to the ground node, the power supply voltage VDD is connected to the ground through the first PMOS transistor P1 and the first resistor R1. Since Iref increases, the reference voltage Vref of the node K2 gradually increases.

In the initial operation of the voltage detector 120, the second PMOS transistor P2 is turned on because the reference voltage Vref of the node K2 is not sufficiently high. Since the power supply voltage VDD is applied to the node K3 when the second PMOS transistor P2 is turned on, the voltage Vref_inverse of the node K3 becomes a high level, and the output unit 130 has a high level. Output a power-on reset signal (VPOR).

When the reference voltage Vref of the node K2 gradually increases, the second PMOS transistor P2 is turned off and a time point at which the first NMOS transistor N1 is turned on occurs.

When the first NMOS transistor N1 is turned on, the node K3 is connected to the ground node. The second NMOS transistor N2 is connected in the form of a diode so that the voltage Vref_inverse of the node K3 does not have a voltage level that is too low.

Meanwhile, when the node K3 is connected to the ground node, the output unit 130 outputs a power on reset signal VPOR having a low voltage level.

The power-on reset signal VPOR output by the power-on reset circuit 100 is maintained at a high level during an initial operation and then falls to a low level when a power supply voltage VDD is applied to some extent. The semiconductor device (not shown) to which the power on reset circuit 100 is applied starts an initialization operation when the power on reset signal VPOR is changed from a high level to a low level.

Since the semiconductor device operates after the power-on reset signal VPOR is changed to the low level, the semiconductor device may be initialized using the stable power supply voltage VDD.

The semiconductor device operating by the power-on reset signal VPOR output by the power-on reset circuit 100 may cause a malfunction in response to a ramping-up time at which the voltage level of the input power supply voltage VDD is increased. Can be.

2A and 2B show the output of the power on reset signal when the power ramping up time is different.

2A illustrates a case where the power ramping up time is fast, and FIG. 2B illustrates a case where the power ramping up time is slow. The power ramping up time of FIG. 2A is 0.1u second and the power ramping up time of FIG. 2B is 1mu second.

Referring to FIG. 2A, when the time for which the power supply voltage VDD is raised to 2V is short, the power-on reset signal VPOR drops to a low level after the power supply voltage VDD is stabilized to 2V.

However, referring to FIG. 2B, it can be seen that the power-on reset signal VPOR falls to the low level before the power supply voltage VDD is stabilized. This phenomenon is related to the gate capacitance of the second PMOS transistor P2 and the first NMOS transistor N1. The capacitor's impedance is large at low frequencies while small at high frequencies. Therefore, in the low frequency region, little current flows through the capacitor. However, in the high frequency region, the capacitor is almost short.

In addition, when the power supply is fast, the current Iref passed by the first PMOS transistor P1 flows first toward the capacitance of the gate having a lower resistance than the first resistor R1. In addition, since the current Iref flows to the first resistor R1 after filling the capacitance of the gate, the voltage increase rate of the node K2 is slowed down.

On the contrary, when the slow power supply voltage is supplied, the current Iref flows toward the first resistor R1 from the beginning, so that the reference voltage Vref of the node K2 is increased quickly, and the first NMOS transistor N1 is turned on too quickly. .

If the power-on reset signal VPOR is changed to a low level before the power supply voltage VDD is stabilized, the semiconductor device may not receive the stable power supply voltage VDD when the initialization operation is performed, and thus a malfunction may occur.

Therefore, the technical problem to be achieved by the present invention is that the semiconductor device performing the initialization operation by the power-on reset signal is normally initialized by outputting the power-on reset signal after the power supply voltage is stabilized regardless of the time when the power supply voltage is stabilized. The present invention provides a power-on reset circuit and a semiconductor device having the same.

Power on reset circuit according to a feature of the invention,

A power on reset signal generator for outputting a power on reset signal when the voltage level of the reference voltage input to the first node rises above the set voltage; A discharge unit for discharging the reference voltage for a predetermined time; And a discharge control unit configured to control the discharge unit by outputting a discharge control signal in response to the operation of the discharge unit in response to the voltage level of the power-on reset signal.

And a reference voltage generator configured to generate the reference voltage in response to a power supply voltage and output the reference voltage to the first node.

The apparatus may further include an output unit including first to 2N (N is a natural number) inverters for delaying the power-on reset signal.

The discharge unit may include a first switching device connected between the first node and a ground node and operated in response to the discharge control signal.

The discharge controller includes: a second switching element connected between a power supply voltage input terminal and a second node and operating in response to a voltage level of an output terminal of the second N-1 inverter; A third switching element connected between the power supply voltage input terminal and a third node and operating in response to a voltage level of an output terminal of the second N inverter; And a latch circuit connected to the second and third nodes, wherein the discharge control signal is output from the third node.

The discharge controller generates and outputs the discharge control signal for turning on the first switching element for a predetermined time.

A semiconductor device according to a feature of the present invention,

A power-on reset signal generator for outputting a power-on reset signal when the voltage level of the reference voltage input to the first node rises above the set voltage in response to the power supply voltage input to the semiconductor device; A power-on reset circuit including a discharge portion to occupy and a discharge control portion to output a discharge control signal in response to a voltage level of the power-on reset signal to control the discharge portion; And an internal circuit of the semiconductor device that performs an initial operation by the power on reset signal.

The power on reset signal generator is connected between a power supply voltage input terminal and a second node, and is connected between a first type P transistor that operates in response to a voltage level of the first node, and between the second node and a ground node. And an N-type second transistor operating in response to the voltage level of the first node, and outputting a power-on reset signal from the second node.

The apparatus may further include an output unit including first to 2N (N is a natural number) inverters for delaying the power-on reset signal.

The discharge unit may include a first switching device connected between the first node and a ground node and operated in response to the discharge control signal.

The discharge controller may include: a second switching element connected between the power supply voltage input terminal and a third node and operating in response to a voltage level of an output terminal of the 2N-1 inverter; A third switching element connected between the power supply voltage input terminal and a fourth node and operating in response to a voltage level of an output terminal of the second N inverter; And a latch circuit connected to the third and fourth nodes, wherein the discharge control signal is output from the third node.

The discharge controller generates and outputs the discharge control signal for turning on the first switching element for a predetermined time.

As described above, the power-on reset circuit according to the present invention and the semiconductor device having the same may be output after the power-on reset signal for initializing the semiconductor device is stabilized regardless of the voltage level rising rate of the power supply voltage. The semiconductor device can be assisted by preventing an error during the initialization operation.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3A illustrates a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, the semiconductor device 300 includes a power on reset (POR) circuit 310 and an internal circuit 320. The internal circuit 320 briefly illustrates circuits for the operation of the semiconductor device 300.

The POR circuit 310 outputs a power-on reset signal VPOR, and the internal circuit 320 performs an initialization operation when a power-on reset signal VPOR is changed from a high level to a low level. . After the initialization operation, the operation status is maintained until the operation command is input.

FIG. 3B shows the POR circuit of FIG. 3A.

Referring to FIG. 3, the POR circuit 310 may include a reference voltage generator 311, a power-on reset signal generator 312, an output unit 313, a voltage discharger 314, and a discharge controller 315. ).

The reference voltage generator 311 generates the reference voltage Vref by distributing the power supply voltage VDD. The power on reset signal generator 312 outputs a voltage Vref_inverse according to the voltage level of the reference voltage Vref. The voltage Vref_inverse is output as a power on reset signal.

The output unit 313 delays and outputs the voltage Vref_inverse which is a power-on reset signal.

The voltage discharge unit 314 discharges the reference voltage Verf for a predetermined time so that the reference voltage Verf does not rise too quickly.

The discharge controller 315 controls the discharge operation by controlling the voltage discharge unit 314.

The reference voltage generator 311 includes a first PMOS transistor PM1 and a first resistor R10, and the power-on reset signal generator 312 includes a second PMOS transistor PM2 and first and second NMOS. Transistors NM1 and NM2.

The output unit 313 includes first to fourth inverters IN10 to IN40, and the voltage discharge unit 314 includes a third NMOS transistor NM3.

The discharge controller 315 includes third and fourth PMOS transistors PM3 and PM4 and fifth and sixth inverters IN50 and IN60.

The first PMOS transistor PM1 is connected between the node D1 and the node D2, and the gate of the first PMOS transistor PM1 is connected to the ground node. The first PMOS transistor PM1 is always turned on.

The first resistor R10 is connected between the node D2 and the ground node. The voltage at the node D2 is the reference voltage Vref.

The second PMOS transistor PM2 is connected between the node D1 and the node D3, and the first and second NMOS transistors NM1 and NM2 are connected in series between the node D3 and the ground node. The gate of the first NMOS transistor NM1 and the gate of the second PMOS transistor PM2 are commonly connected to the node D2. The gate of the second NMOS transistor NM2 is connected to the drain terminal in common and is connected in the form of a diode.

Meanwhile, the second PMOS transistor PM2 and the first NMOS transistor NM1 are inverter circuits that invert the reference voltage Vref of the node D2 and output the inverted voltage Vref_inverse.

The first to fourth inverters IN10 to IN40 are connected in series between the node D3 and the node D5. The voltage at the node D5 is the power on reset signal VPOR.

The third NMOS transistor NM3 is connected between the node D2 and the ground node, and the gate of the third NMOS transistor NM3 is connected to the node D7.

The third PMOS transistor PM3 is connected between the node D6 and the node D7, and the gate of the third PMOS transistor PM3 is connected to the node D4. The node D4 is a connection point at which an output terminal of the third inverter IN30 and an input terminal of the fourth inverter IN40 are connected.

The fourth PMOS transistor PM4 is connected between the node D6 and the node D8, and the gate of the fourth PMOS transistor PM4 is connected to the node D5.

The fifth and sixth inverters IN50 and IN60 are connected as the latch circuit L between the node D7 and the node D8.

The operation of the POR circuit 310 is as follows.

When the power supply voltage VDD is input, the current Iref flows to the node D2 of the reference voltage generator 311. If the ramping-up time when the power supply voltage VDD rises is long, it may be said that the power supply is slow and thus operates in a low frequency region.

When the power supply voltage VDD is inputted, the current Iref flows to the first resistor R10, and the voltage level of the node D2 rises rapidly.

In the initial operation, the reference voltage Vref is at a voltage level low enough to turn on the second PMOS transistor PM2. Node D4 is therefore low level and node D5 is high level.

When the node D4 is at the low level, the third PMOS transistor PM3 is turned on to connect the power supply voltage VDD to the node D7. Therefore, the node D7 of the latch circuit L is at the high level, and the node D8 is maintained at the low level.

When the node D7 is at the high level, the third NMOS transistor NM3 is turned on.

Therefore, it is possible to prevent the reference voltage Vref of the node D2 from being discharged to the ground node and rising rapidly.

However, when the power supply voltage VDD rises above the predetermined voltage, the voltage flowing into the third PMOS transistor PM3 gradually rises. That is, even though the voltage is discharged through the third NMOS transistor NM3, when the voltage level of the reference voltage Vref is increased to turn on the first NMOS transistor NM1, the voltage of the node D3 is discharged. It begins to slow down.

The third PMOS transistor PM3 is turned off when the voltage of the node D4 connected to the gate of the third PMOS transistor PM3 is gradually increased to decrease the voltage difference from the node D6 as the source terminal. When the voltage level of the node D4 increases, the voltage level of the node D5 gradually decreases. Therefore, the fourth PMOS transistor PM4 is turned on.

Therefore, the node D7 of the latch circuit L goes low and the node D8 goes high.

When the node D7 becomes low level, the third NMOS transistor N3 is turned off. Therefore, the reference voltage Vref is no longer discharged.

Meanwhile, the internal circuit 320 starts an initialization operation by the power-on reset signal VPOR in which the node D5 is changed from the high level to the low level.

4A and 4B illustrate a power on reset signal output according to a voltage level rising rate of a power supply voltage in a power on reset circuit according to an exemplary embodiment of the present invention.

4A shows a ramping-up time when the power supply voltage VDD is increased to 0.1u second, and FIG. 4B shows a ramping-up time when the power supply voltage VDD is raised to 1mu second.

Referring to FIG. 4A, when the power supply voltage VDD rises rapidly, the power-on reset signal VPOR changes to a low level after a certain amount of delay after the power is completely raised.

4B, even when the power supply voltage VDD is gradually increased, the reference voltage Vref is discharged through the third NMOS transistor NM3 in the middle of the power-up, so that the reference voltage Vref increases rapidly. To prevent

If the reference voltage Vref is prevented from increasing rapidly, the time for changing the power-on reset signal VPOR to the low level can be delayed. As shown in FIG. 4B, when the voltage level of the normally stable power supply voltage VDD is 2V, the power-on reset signal VPOR is changed to the low level after the power supply voltage VDD is raised to about 1.8V.

Therefore, since the internal circuit 320 of the semiconductor device 300 is initialized by using a stable power supply voltage VDD, the internal circuit 320 may be protected to prevent malfunction.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 shows a power on reset circuit.

2A and 2B show the output of the power on reset signal when the power ramping up time is different.

3A illustrates a semiconductor device according to an embodiment of the present invention.

FIG. 3B shows the POR circuit of FIG. 3A.

4A and 4B illustrate a power on reset signal output according to a voltage level rising rate of a power supply voltage in a power on reset circuit according to an exemplary embodiment of the present invention.

* Brief description of the main parts of the drawings *

300: semiconductor device 310: POR circuit

320: internal circuit 311: reference voltage generator

312: voltage sensing unit 313: output unit

314: voltage discharge unit 315: discharge control unit

Claims (12)

A power on reset signal generator for outputting a power on reset signal when the voltage level of the reference voltage input to the first node rises above the set voltage; A discharge unit for discharging the reference voltage for a predetermined time; And A discharge controller for controlling the discharge unit by outputting a discharge control signal in response to the operation of the discharge unit in response to a voltage level of the power-on reset signal; Power on reset circuit comprising a. The method of claim 1, And a reference voltage generator configured to generate the reference voltage in response to a power supply voltage and output the reference voltage to the first node.  3. The method of claim 2, And an output unit including first to 2N (N is a natural number) inverters for delaying outputting the power on reset signal. The method of claim 3, wherein The discharge unit, And a first switching element connected between the first node and a ground node, the first switching element operating in response to the discharge control signal. The method of claim 4, wherein The discharge control unit, A second switching element connected between a power supply voltage input terminal and a second node and operating in response to a voltage level of an output terminal of the 2N-1 inverter; A third switching element connected between the power supply voltage input terminal and a third node and operating in response to a voltage level of an output terminal of the second N inverter; And A latch circuit connected to the second and third nodes, And the discharge control signal is output from the third node. The method of claim 5, The discharge control unit, And a power on reset circuit configured to generate and output the discharge control signal for turning on the first switching element for a set time. A power-on reset signal generator for outputting a power-on reset signal when the voltage level of the reference voltage input to the first node rises above the set voltage in response to the power supply voltage input to the semiconductor device; A discharge unit for discharging the reference voltage for a predetermined time period, and A power on reset circuit including a discharge controller to control the discharge unit by outputting a discharge control signal in response to an operation of the discharge unit in response to a voltage level of the power on reset signal; And An internal circuit of the semiconductor device performing an initial operation by the power on reset signal A semiconductor device comprising a. The method of claim 7, wherein The power on reset signal generator, A first type transistor (P type) connected between a power supply voltage input terminal and a second node, the first transistor being operated in response to a voltage level of the first node; A second transistor of an N type connected between the second node and a ground node and operating in response to a voltage level of the first node; And a power-on reset signal is output from the second node.  The method of claim 8, And an output unit including first to 2N (N is a natural number) inverters for delaying the power-on reset signal. The method of claim 9, The discharge unit, And a first switching element connected between the first node and a ground node and operating in response to the discharge control signal. The method of claim 10, The discharge control unit, A second switching element connected between the power supply voltage input terminal and a third node and operating in response to a voltage level of an output terminal of the second N-1 inverter; A third switching element connected between the power supply voltage input terminal and a fourth node and operating in response to a voltage level of an output terminal of the second N inverter; And A latch circuit connected to the third and fourth nodes, And the discharge control signal is outputted from the third node. The method of claim 11, The discharge control unit, And generating and outputting the discharge control signal for turning on the first switching element for a predetermined time.

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