KR20100126061A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to prevent a side effect at the interface between lamp blocks by reducing the number of a transformer in comparison with the number of a lamp block. CONSTITUTION: An LCD panel is divided into a first display area and a second display area to be driven. A gate driving circuit alternately supplies a scan pulse to the first display area and the second display area. A data driving circuit supplies display data to data lines. A backlight unit radiates light on an LCD panel. A light source control circuit use a light source sync signal and generates a light scan signal. A light source driving circuit comprises a first transformer and a second transformer. The first transformer simultaneously drives a first upper light block and lower light block. The second transformer drives the second block.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device capable of improving moving picture response time (MPRT) performance.

An active matrix liquid crystal display device displays a moving image using a thin film transistor (“TFT”) as a switching element. This liquid crystal display device is thinner and higher resolution than cathode ray tube ("CRT"), so it is applied to display in portable information equipment, office equipment, computer, etc., and is rapidly replacing CRT. .

However, in the liquid crystal display device, the moving picture response time characteristic (MPRT) is worse than the CRT in view of its driving characteristics. As shown in FIG. 1A, the CRT is an impulse type that emits a fluorescent material only for an initial very short time of one frame period to display an image, and maintains a non-display state for the rest of one frame period. Driven. The perceived image of the moving image felt by the viewer in the CRT becomes clear as shown in FIG. 1 (b) due to the driving of the impulse type. On the other hand, as shown in FIG. 2A, the liquid crystal display supplies data to the liquid crystal cell during the scanning period during one frame period, and holds the data to display an image even during the non-scanning period, which is the remaining time of one frame period. It is driven by a hold-type. As a result, in the liquid crystal display, due to the hold type characteristic, a motion blurring phenomenon in which a screen is not clear and blurry in a video as shown in FIG. 2 (b) or an afterimage of a previous screen remains on the current screen Due to the tailing phenomenon, MPRT performance is reduced.

In order to improve MPRT, a technique of driving an impulse driving the liquid crystal display by sequentially turning on the backlight in synchronization with video data displayed on the screen, that is, a scanning backlight driving method has been proposed.

Referring to FIG. 3, a liquid crystal display device driven by a scanning backlight method includes lamps sequentially driven in units of blocks and an inverter 1 for applying driving power to the lamps. The lamps are electrically connected to the balance patterns 4 formed on the balance board 3 and are driven in a plurality of blocks BL1, BL2, BL3. The inverter 1 includes the number of transformers 2 corresponding to the lamp blocks BL1, BL2, and BL3 to sequentially operate the transformers 2 in response to the lamp scan signal SS input from the outside. . The transformers 2 are each electrically connected to the balance patterns 4 to apply lamp driving power to the corresponding lamp blocks. The liquid crystal display turns on the lamps of the corresponding lamp block at the optimal light source sink point in consideration of the state of charge of the display data Vdata on the corresponding display surface of the corresponding lamp block as shown in FIG. 4. Since the display data Vdata is sequentially charged from the top to the bottom of the display surface, the lamps are sequentially turned on in block units correspondingly. Normally, the optimum light source sink timing is determined when the display data Vdata is charged in the middle portion of the corresponding display surface. Considering the relationship with the charging timing of the display data, as the number of lamp blocks is increased to decrease the display area that one lamp block is responsible for, that is, as the number of light source sync points for determining the light source sink timing increases, the light source sync timing Can be synchronized more precisely at the time of charging the display data. However, in the above-described scanning backlight method, since the transformer 2 is required as much as the number of ramp blocks increased, it is difficult to meet the slimming trend and manufacturing cost of the liquid crystal display device.

Therefore, recently, the scanning backlight method as shown in FIG. 5 has been proposed by the present applicant. In the scanning backlight method of FIG. 5, lamps are physically divided into three lamp blocks BL1 (A), BL2, and BL1 (B), and the upper and lower lamp blocks BL1 (A) and BL1 (B) are electrically connected to each other. By connecting, the number of transformers 5 is reduced compared to the physical number of lamp blocks. 5, the backlight scanning effect can be seen at three points more than the number of transformers (two).

However, this method has a problem in that it is difficult to obtain an optimal light source sink point in the electrically connected upper and lower lamp blocks BL1 (A) and BL1 (B) as shown in FIG. 6. Since the upper and lower lamp blocks BL1 (A) and BL1 (B) are driven simultaneously by the same transformer 5, their light source sync points are the same. However, since the display data Vdata is sequentially charged from the top to the bottom of the display surface, when the light source sync time is set based on any one of the upper and lower ramp blocks BL1 (A) and BL1 (B), In the lamp block, the set light source sync time point is greatly shifted in relation to the completion time of charging the display data Vdata on the corresponding display surface. For example, in FIG. 6, when the light source sync point is set based on the upper lamp block BL1 (A), the lamps are turned on in advance before the display data Vdata is charged in the lower lamp block BL1 (B). Will be.

In addition, since the display surface corresponding to the intermediate lamp block BL2 is twice as wide as the display surface of the other blocks BL1 (A) and BL1 (B), the light source sync point is displayed in the middle portion of the corresponding display surface. Even when the data Vdata is determined to be charged, the light source sync point may be shifted from the data charge point at upper and lower portions of the corresponding display surface.

In this way, when the light source sync timing is not synchronized with the completion of charging of the display data, light leakage occurs in the charging transient period of the display data synchronized with the turn-on state of the lamp, resulting in double lines or blurring at the interface between the lamp blocks. The side effect gets worse.

Accordingly, an object of the present invention is to provide a liquid crystal display device which prevents side effects occurring at the interface between lamp blocks while reducing the number of transformers compared to the number of lamp blocks.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel in which a plurality of gate lines and a plurality of gate lines intersect and are divided and driven to a first display surface and a second display surface; The scan pulse is sequentially supplied to the gate lines of the first display surface in a first direction, and the scan pulse is sequentially supplied to the gate lines of the second display surface in a second direction opposite to the first direction. A gate driving circuit for supplying the scan pulse alternately to the first display surface and the second display surface at regular intervals; A data driving circuit supplying display data to the data lines to charge the liquid crystal cells to which the scan pulse is applied; A backlight unit for irradiating light to the liquid crystal display panel including a first upper light source block, a first lower light source block, and a second light source block disposed between the first upper light source block and the first lower light source block; A light source control circuit configured to generate a light source scan signal using the input light source sink signal; And a light source driving circuit including a first transformer for simultaneously driving the first top light source block and the first bottom light source block and a second transformer for driving the second light source block in response to the light source scan signal. .

The gate driving circuit may include: a first gate driver configured to generate scan pulses shifted by two horizontal periods in the first direction with a pulse width of one horizontal period and to supply the gate lines to the first display surface; And a second gate driver configured to generate scan pulses shifted by two horizontal periods in the second direction with a pulse width of one horizontal period and to supply the gate lines to the second display surface; The scan pulses generated by the first gate driver and the scan pulses generated by the second gate driver are adjacent to each other by one horizontal period.

The liquid crystal display further includes a timing controller for controlling driving timing of the first and second gate drivers.

The timing controller may include a data storage unit for storing one frame of digital video data input from the outside; A data alignment unit for rearranging the digital video data in the order of supply of the scan pulses and then supplying the rearranged digital video data to the data driving circuit; And a control signal generator for generating a first gate timing control signal for controlling the driving timing of the first gate driver and a second gate timing control signal for controlling the driving timing of the second gate driver.

The first gate timing control signal includes a first gate shift clock signal having a pulse width of two horizontal periods and being generated at four horizontal periods; The second gate timing control signal has a phase delayed by one horizontal period compared to the first gate shift clock signal, and includes a second gate shift clock signal generated at four horizontal periods with a pulse width of two horizontal periods. .

The light source sync signal is a timing signal for controlling the light source turn-on time of the corresponding light source block to be synchronized with the completion time of charging the display data; The light source turn-on time of the light source block is determined when the display data is completely charged in the middle horizontal line portion of the display surface corresponding to the light source block.

The light source sync signal is applied to the middle horizontal line portion of the display surface corresponding to the first upper light source block when the display data is completed and to the middle horizontal line portion of the display surface corresponding to the first lower light source block. Any one of when the display data is charged; When the display data is completed in the middle horizontal line portion of the display surface corresponding to the upper half of the second light source block, and the display data is displayed in the middle horizontal line portion of the display surface corresponding to the lower half of the second light source block. When charging is completed, either of them is set as a reference.

A light source turn-on time of the first and second light source blocks is determined as a first time point; The light source turn-on time of the second light source block is determined to be a second time later than the first time point.

The light source control circuit further uses a pulse width modulated signal input from the outside in generating the light source scan signal; The light source turn-off time point of the light source blocks depends on the duty ratio of the pulse width modulated signal.

In the liquid crystal display according to the present invention, by driving 2k-1 lamp blocks that are physically divided using k (k is a natural number of 2 or more) transformers, the number of transformers can be reduced compared to the number of physical light source blocks. By increasing the light source sink points for setting the optimal light source sync signal to 2k, the light source turn-on time in the light source blocks can be effectively synchronized with the charging time of the display data on the corresponding display surface. As a result, side effects occurring at the interface between the lamp blocks due to a mismatch between the light source turn-on time and the charging time point of the display data can be effectively prevented.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 15.

7 shows a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 7, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a data driving circuit 12 for driving data lines DL of the liquid crystal display panel 10, and a liquid crystal display. Including a gate driver circuit 13 for driving the gate lines GL of the panel 10, a timing controller 11 for controlling the data driver circuit 12 and the gate driver circuit 13, and a plurality of light sources. A backlight unit 16 for irradiating light to the liquid crystal display panel 10, a light source control circuit 14 for generating a light source scanning signal SS, and a light source driving circuit for driving the light sources in accordance with the light source scanning signal SS (15) is provided. The gate driving circuit 13 includes a first gate driver 13A and a second gate driver 13B.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. A plurality of data lines DL and a plurality of gate lines GL cross on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are arranged in a matrix form on the liquid crystal display panel 10 due to the cross structure of the data lines DL and the gate lines GL. In addition, a thin film transistor TFT, a pixel electrode 1 of a liquid crystal cell Clc connected to the thin film transistor TFT, a storage capacitor Cst, and the like are formed on a lower glass substrate of the liquid crystal display panel 10.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting a pretilt angle of the liquid crystal is formed on an inner surface of the liquid crystal display panel 10 in contact with the liquid crystal.

As illustrated in FIG. 8, the timing controller 11 includes a data storage 111, a data alignment unit 112, and a control signal generator 113.

The data storage unit 111 stores a frame of digital video data RGB input from a system board including an external video source including a frame memory.

The data alignment unit 112 rearranges the digital video data RGB of one frame from the data storage unit 111 in the panel scan order. The panel scan according to the present invention is performed along the Y direction on the upper display surface 10A and the Y 'direction on the lower display surface 10B of the liquid crystal display panel 10, as shown in FIG. It is made up alternately on the upper display surface 10A and the lower display surface 10B. Accordingly, the data aligning unit 112 may include data to be charged in the first horizontal line (RGB (H1))-> data to be charged in the nth horizontal line (RGB (Hn))-> data to be charged in the second horizontal line ( RGB (H2))-> Data to be charged to the n-1th horizontal line (RGB (Hn-1))-> Data to be charged to the 3rd horizontal line (RGB (H3))-> To the n-2th horizontal line The digital video data RGB for one frame is rearranged in order of data to be charged (RGB (Hn-2)). The data aligning unit 112 supplies the rearranged digital video data RGB to the data driving circuit 12.

The control signal generator 113 controls the operation timing of the data driver 12 and the first and second gate drivers 13A and 13B based on the timing signals Vsync, Hsync, DE, and DCLK from the system board. Generate timing control signals DDC, GDC1, and GDC2 for control.

The data timing control signal DDC for controlling the operation timing of the data driving circuit 12 is a source start pulse (SSP) indicating the position of the liquid crystal cell Clc to which valid data is applied in one horizontal period. , A source sampling clock (SSC) for instructing latching of data in the data driving circuit 13 based on a rising or falling edge, and an output of the data driving circuit 13. A source output enable signal SOE, and a polarity control signal POL indicating the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 10.

The first gate timing control signal GDC1 for controlling the operation timing of the first gate driver 13A indicates a start horizontal line at which scanning of the upper display surface 10A starts in one vertical period in which one screen is displayed. The first gate start pulse GSP1 is input to the shift register in the first gate driver 13A and the TFT is turned on as a timing control signal for sequentially shifting the first gate start pulse GSP1. A first gate shift clock signal GSC1 generated at a pulse width approximately twice that corresponding to the period, and a first gate output enable signal indicating output of the first gate driver 13A. Enable: GOE1).

The second gate timing control signal GDC2 for controlling the operation timing of the second gate driver 13B indicates a starting horizontal line at which scanning of the lower display surface 10B starts in one vertical period in which one screen is displayed. The second gate start pulse GSP2 generated later than the first gate start pulse GSP1 is input to the shift register in the second gate driver 13B, and the second gate start pulse GSP2 is sequentially shifted. A second gate shift clock signal (Gate Shift) that is generated with a pulse width approximately twice that corresponding to the ON period of the TFT and is delayed by one horizontal period than the first gate shift clock signal GSC1 as a timing control signal for controlling the TFT. Clock: GSC2), and a second gate output enable signal GOE2 indicating the output of the second gate driver 13B.

Meanwhile, the timing controller 11 inserts an interpolation frame between the frames of the input video signal input at a frame frequency of 60 Hz, multiplies the data timing control signal DDC and the gate timing control signals GDC1 and GDC2 by 60 ×. The operation of the data driving circuit 12 and the first and second gate drivers 13A and 13B may be controlled at a frame frequency of N (N is a positive integer of 2 or more) Hz.

The data driving circuit 12 stores a shift line for sampling a clock signal, a register for temporarily storing digital video data (RGB), and one line for storing data in response to a clock signal from the shift register. Latch for outputting data at the same time, digital / analog converter for selecting positive / negative gamma voltage under reference to gamma reference voltage corresponding to digital data value from latch, conversion by positive / negative gamma voltage A plurality of data drive integrated circuits each include a multiplexer for selecting a data line DL to which analog data is supplied, and an output buffer connected between the multiplexer and the data line DL. The data driving circuit 12 latches the digital video data RGB in response to the data timing control signal DDC from the timing controller 11, and the latched digital video data RGB is positive / negative polarity gamma. The compensation voltage is converted into the positive / negative analog data voltage and then supplied to the data lines DL.

The first gate driver 13A includes a plurality of gate drive integrated circuits each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of a liquid crystal cell, and an output buffer. do. In response to the first gate timing control signal GDC1 from the timing controller 11, the first gate driver 13A sequentially outputs scan pulses (or gate pulses) having a pulse width of approximately one horizontal period, thereby providing liquid crystal. The gate lines GL are formed on the upper display surface 10A of the display panel 10. Specifically, as shown in FIG. 10, the first gate driver 13A has a pulse width of approximately 2 horizontal periods 2H and a rising edge of the first gate shift clock signal GSC1 generated at approximately 4 horizontal periods 4H. And in synchronization with the falling edge, scan pulses SP1, SP2, SP3 ... are shifted by approximately two horizontal periods 2H along the Y direction with a pulse width of approximately one horizontal period 1H.

The second gate driver 13B includes a plurality of gate drive integrated circuits each including a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of a liquid crystal cell, and an output buffer. do. In response to the second gate timing control signal GDC2 from the timing controller 11, the second gate driver 13B sequentially outputs scan pulses (or gate pulses) having a pulse width of approximately one horizontal period, thereby providing liquid crystal. The gate line GL is formed on the lower display surface 10B of the display panel 10. Specifically, the second gate driver 13B is delayed in phase by approximately one horizontal period 1H relative to the first gate shift clock signal GSC1 as shown in FIG. 10 and has a pulse width of approximately two horizontal periods 2H. Approximately 2 horizontally along the Y 'direction with a pulse width of approximately 1 horizontal period (1H) in synchronization with the rising edge and the falling edge of the second gate shift clock signal GSC2 generated at approximately 4 horizontal periods 4H. Scan pulses SPn, SPn-1, SPn-2 ... are shifted by period 2H.

The backlight unit 16 includes light sources, a diffuser plate disposed on the light sources, and a plurality of optical sheets stacked between the diffuser plate and the liquid crystal display panel 10. As the light source, a cold cathode fluorescent lamp (hereinafter referred to as "CCFL") or an external electrode fluorescent lamp (hereinafter referred to as "EEFL") may be used. Since the EEFL projects external electrodes at both ends of the lamps, it is easy to drive the lamps in blocks. In the CCFL, since electrodes are formed inside the glass tube, a plurality of balance patterns connected to each of the lamps 120 through a connector and a balance board on which the balance patterns are formed are required to drive the lamps in blocks. Balance patterns may be implemented with balance capacitors. The balance capacitors serve as external electrodes, and each of them is connected to each other on a balance board in units of light blocks. Meanwhile, in the case of EEFL, the common electrode connection pattern may be used instead of the balance pattern, and the common electrode board may be used instead of the balance board. However, since the functions are the same in that they are only difference in terminology and are lamp connection means for driving lamps in units of blocks, the following will be collectively referred to as a balance pattern and a balance board regardless of the type of lamp. As illustrated in FIG. 11, the light sources are electrically connected to the balance patterns 154 formed on the balance board 153 and physically divided into three light source blocks BL1 (A), BL2, and BL1 (B).

The light source control circuit 14 generates a light source scan signal SS by using a pulse width modulation (PWM) signal and a light source sync signal Lsync. The PWM signal may be input at a duty ratio of 40% to 60% fixed in advance by the user, and may be input at a duty ratio that is variable according to the attribute of the display data. That is, the PWM signal may be input at a first duty ratio corresponding to display data of a relatively bright image, and may be input at a second duty ratio smaller than the first duty ratio corresponding to display data of a relatively dark image. The light source sync signal Lsync is a timing signal for controlling the light source turn-on time in the corresponding light source block to be synchronized with the completion time of charging the display data, and is normally set in advance by the user. The optimum light source turn-on time in the light source block may be determined when the display data is completely charged in the middle horizontal line portion of the display surface corresponding to the light source block. The light source turn off timing depends on the duty ratio of the PWM signal.

The light source driving circuit 15 includes an inverter 151 for mounting the transformers 152 and a balance board 153 on which the balance patterns 154 are formed, as shown in FIG. 11, to generate a light source driving signal LDS for each block. do. The light source driving signal LDS is applied to the lamps. The balance patterns 154 may include a first balance pattern electrically connecting lamps disposed in the first upper and lower light source blocks BL1 (A) and BL1 (B), and lamps disposed in the second light source block BL2. And a second balance pattern electrically connected. The first balance pattern is connected to the first transformer of the two transformers 152 and the second balance pattern is connected to the second transformer. The transformers 152 are sequentially operated in response to the light source scan signal SS. As a result, the light source turn-on time of the first upper and lower light source blocks BL1 (A) and BL1 (B) receiving the light source driving signal LDS through the first transformer is the same as the first time point as shown in FIG. 13. The light source turn-on time of the second light source block BL2 receiving the light source driving signal LDS through the second transformer becomes a second time later than the first time point as shown in FIG. 13.

Through this connection configuration of the light source driving circuit 15 and the lamps, the present invention can divide the lamps into three light source blocks BL1 (A), BL2, and BL1 (B), but the first upper and lower light source blocks BL1 ( By electrically connecting A) and BL1 (B), the number of transformers 152 can be reduced compared to the number of physical light source blocks. However, in this case, as shown in FIG. 6, since the light source turn-on time is inconsistent with the completion time of charging the display data in the light source blocks BL1 (A), BL1 (B), and BL2, the present invention is to solve the problem. The invention changes the charging order of the display data by applying the above-described panel scanning method.

12 and 13 show that the light source turn-on time in the light source blocks is synchronized with the charging time of the display data using the panel scan method according to the present invention.

12 and 13, the present invention does not sequentially charge the display data Vdata from the top to the bottom of the display surface 10 (in the Y direction), and in the upper display surface 10A in the Y direction and displays the lower display. The surface 10B is charged in the Y 'direction, but alternately charges the upper display surface 10A and the lower display surface 10B alternately every 1 horizontal period 1H.

As a result, the charging time of the display data Vdata corresponding to the first lower light source block BL1 (B) is lower than the charging time of the display data Vdata corresponding to the first upper light source block BL1 (A). Since only one horizontal period 1H is different, the light source turn-on time may be set by simply setting the light source turn-on time based on one of the first upper and lower light source blocks BL1 (A) and BL1 (B). May be easily synchronized with the charging time of the display data Vdata corresponding to the other light source block. In other words, this means that the light source sync point for setting the optimal light source sync signal Lsync is increased to two.

In addition, the light source sync point for setting the optimal light source sync signal Lsync also increases in the second light source block BL2 by the display data Vdata charging method. By the display data Vdata charging method, the second light source block BL2 may be divided into a second upper light source block BL2 (A) and a second lower light source block BL2 (B). The charging time of the display data Vdata corresponding to the second lower light source block BL2 (B) is one horizontal period compared to the charging time of the display data Vdata corresponding to the second upper light source block BL2 (A). Since only 1H is different, the light source turn-on time may be set based on one of the second upper and lower light source blocks BL2 (A) and BL2 (B). The timing of charging the display data Vdata corresponding to the light source block may be easily synchronized. This is a light source sink for setting an optimal light source sync signal Lsync, compared with the conventional one having a light source sync point at a portion corresponding to the boundary surface of the second upper and lower light source blocks BL2 (A) and BL2 (B). This means that the points will increase to two.

As a result, according to the present invention, the number of light source sync points is increased to four while reducing the number of transformers (two) compared to the number of physical light source blocks (three), so that the light source turn-on timings in the light source blocks are displayed on the corresponding display surface. It is possible to effectively synchronize at the time of charging the display data.

14 and 15 show an extension example of the present invention when the number of transformers and the number of physical light source blocks are increased.

Referring to FIG. 14, three transformers 152 are configured to scan physically divided light source blocks BL1 (A), BL2 (A), BL3, BL2 (B), and BL1 (B). It is provided. The first balance pattern of the balance patterns 154 electrically connects the lamps disposed in the first upper and lower light source blocks BL1 (A) and BL1 (B) to the first transformer of the transformers 152, and the second balance pattern. The balance pattern electrically connects the lamps disposed in the second upper and lower light source blocks BL2 (A) and BL2 (B) to the second transformer, and the third balance pattern connects the lamps disposed in the third light source block BL3. Electrically connect to the third transformer.

When the connection configuration of the light source driving circuit and the lamps is applied to the display data charging method, the present invention can reduce the number of transformers (three) and the light source sink point while reducing the number of physical light source blocks (five) as shown in FIG. 15. 6 can be increased to effectively synchronize the light source turn-on time in the light source blocks with the charging time of the display data on the corresponding display surface.

In other words, the present invention can implement scanning backlight driving by driving 2k-1 lamp blocks that are physically divided using k (k is a natural number of two or more) transformers, and particularly for setting an optimal light source sync signal. By increasing the light source sync point to 2k, it is possible to effectively prevent side effects generated at the interface between the lamp blocks due to a mismatch between the light source turn-on time and the charging time of the display data.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 shows an example of driving an impulse type.

2 shows an example of driving of a hold type;

3 is a view showing a light source connection configuration in driving a conventional general scanning backlight;

4 is a view showing display data charging timing and light source sync timing according to FIG. 3;

5 is a view showing a configuration to reduce the number of transformers compared to the number of physical light source blocks in the conventional scanning backlight driving.

FIG. 6 is a diagram illustrating display data charging timing and light source sink timing according to FIG. 5; FIG.

7 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

8 is a block diagram illustrating in detail the timing controller of FIG. 7.

9 is a view for explaining the operation of the data alignment unit of FIG.

FIG. 10 is a waveform diagram illustrating the operation of the gate driving circuit of FIG. 7. FIG.

FIG. 11 is a view showing a connection configuration of a light source driving circuit and light sources of FIG. 7; FIG.

12 and 13 illustrate synchronizing light source turn-on times in light source blocks with charging time of display data using a panel scan method according to the present invention.

14 and 15 are views showing an extension example of the present invention when the number of transformers and the number of physical light source blocks are increased.

<Description of Symbols for Main Parts of Drawings>

10 liquid crystal display panel 11 timing controller

12: data driving circuit 13: gate driving circuit

14 light source control circuit 15 light source driving circuit

16: backlight unit

Claims (9)

A liquid crystal display panel in which a plurality of gate lines and a plurality of gate lines cross each other, and are divided and driven to a first display surface and a second display surface; The scan pulse is sequentially supplied to the gate lines of the first display surface in a first direction, and the scan pulse is sequentially supplied to the gate lines of the second display surface in a second direction opposite to the first direction. A gate driving circuit for supplying the scan pulse alternately to the first display surface and the second display surface at regular intervals; A data driving circuit supplying display data to the data lines to charge the liquid crystal cells to which the scan pulse is applied; A backlight unit for irradiating light to the liquid crystal display panel including a first upper light source block, a first lower light source block, and a second light source block disposed between the first upper light source block and the first lower light source block; A light source control circuit configured to generate a light source scan signal using the input light source sink signal; And And a light source driving circuit including a first transformer for simultaneously driving the first top light source block and the first bottom light source block and a second transformer for driving the second light source block in response to the light source scan signal. A liquid crystal display device. The method of claim 1, The gate driving circuit, A first gate driver configured to generate scan pulses shifted by two horizontal periods in the first direction with a pulse width of one horizontal period and to supply the gate lines to the first display surface; And A second gate driver configured to generate a scan pulse shifted by two horizontal periods in the second direction with a pulse width of one horizontal period and to supply the gate lines to the second display surface; And a scan pulse generated by the first gate driver and a scan pulse generated by the second gate driver have a phase difference from each other by one horizontal period. The method of claim 2, And a timing controller for controlling driving timing of the first and second gate drivers. The method of claim 3, wherein The timing controller, A data storage unit for storing one frame of digital video data input from the outside; A data alignment unit for rearranging the digital video data in the order of supply of the scan pulses and then supplying the rearranged digital video data to the data driving circuit; And And a control signal generator configured to generate a first gate timing control signal for controlling driving timing of the first gate driver and a second gate timing control signal for controlling driving timing of the second gate driver. Liquid crystal display device. The method of claim 4, wherein The first gate timing control signal includes a first gate shift clock signal having a pulse width of two horizontal periods and being generated at four horizontal periods; The second gate timing control signal has a phase delayed by one horizontal period compared to the first gate shift clock signal, and includes a second gate shift clock signal generated at four horizontal periods with a pulse width of two horizontal periods. Liquid crystal display device characterized in that. The method of claim 1, The light source sync signal is a timing signal for controlling the light source turn-on time of the corresponding light source block to be synchronized with the completion time of charging the display data; And a light source turn-on time point in the corresponding light source block is determined when the display data is completely charged in the middle horizontal line portion of the display surface corresponding to the light source block. The method of claim 6, The light source sync signal, When the display data is charged in the middle horizontal line portion of the display surface corresponding to the first upper light source block, and the display data is charged in the middle horizontal line portion of the display surface corresponding to the first lower light source block. Any one of when; When the display data is completed in the middle horizontal line portion of the display surface corresponding to the upper half of the second light source block, and the display data is displayed in the middle horizontal line portion of the display surface corresponding to the lower half of the second light source block. The liquid crystal display device, characterized in that the reference is set to any one of when the charge is completed. The method of claim 7, wherein A light source turn-on time of the first and second light source blocks is determined as a first time point; And a light source turn-on time point of the second light source block is determined as a second time point later than the first time point. The method of claim 8, The light source control circuit further uses a pulse width modulated signal input from the outside in generating the light source scan signal; And a light source turn-off time point of the light source blocks depends on a duty ratio of the pulse width modulation signal.

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