KR20100109786A - Method of manufacturing a memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a memory device is provided to secure a trapping film for electric charges with a uniform thickness by eliminating the exposed part of a pre-trapping film for electric charges through an isotropic etching process. CONSTITUTION: A tunnel insulating film(140) is formed on a substrate(100). A pre-trapping film for electric charges(154) is formed on the tunnel insulating film. An etching stop film is formed to expose a part of the pre-trapping film for the electric charges. The exposed part of the pre-trapping film for the electric charges is eliminated to form a trapping film for the electric charges with a uniform thickness. A dielectric film is formed on the trapping film for the electric charges. A gate is formed on the dielectric film.

Description

Manufacturing method of memory device {METHOD OF MANUFACTURING A MEMORY DEVICE}

The present invention relates to a method of manufacturing a memory device. More specifically, the present invention relates to a method of manufacturing a flash memory device including a charge trap film.

The present application corresponds to an improved invention of a memory device and a method of manufacturing the same as Korean Patent No. 10-0869232.

In general, a flash memory device may be classified into a floating gate type non-volatile memory device and a charge trap type non-volatile memory device according to an operating principle. Can be. The non-volatile semiconductor memory device of the charge trap type uses a charge trap layer instead of the floating gate, unlike the nonvolatile semiconductor memory device that introduces the floating gate.

In general, a charge trap type flash memory device has a structure in which a charge trap film, a dielectric film, and a control gate are stacked on a tunnel insulating film. Charges tunneling the tunnel insulating film are trapped in the charge trap film, and the charge is prevented from moving to the control gate by the dielectric film. It is important to form a flash memory device having a charge trap film having a uniform thickness because charge is trapped and escaped in the charge trap film.

One object of the present invention is to provide a method of manufacturing a memory device including a charge trap film having a uniform thickness.

A method of manufacturing a memory device according to an embodiment of the present invention for achieving the above object is provided. A tunnel insulating film is formed on a substrate. A preliminary charge trap film is formed on the tunnel insulating film. An etch stop layer is formed to partially expose the preliminary charge trap layer. A portion of the exposed preliminary charge trap film is removed to form a charge trap film having a uniform thickness. A dielectric film is formed on the charge trap film. A gate is formed on the dielectric film.

In one embodiment of the present invention, the removing of the preliminary charge trap layer may include removing using an isotropic etching process. After removing a portion of the preliminary charge trap layer, the method may further include removing the etch stop layer.

In one embodiment of the present invention, before forming the tunnel insulating film, a pad film pattern and a mask may be formed on the substrate. By removing the upper portion of the substrate by using the pad layer pattern and the mask as an etching mask, a trench defining an active region protruding from the plane on which the substrate is placed may be formed. A device isolation layer may be formed to fill the trench. The opening may be formed to expose the active region by removing the mask and the pad layer pattern. The tunnel insulating layer may be formed on the exposed active region.

In example embodiments, the forming of the opening exposing the active region by removing the mask and the pad layer pattern may include a wet etching process, and the device isolation layer may be partially removed.

In one embodiment of the present invention, the preliminary charge trap layer may be formed on the bottom and sidewalls of the opening.

In some embodiments, after the forming of the etch stop layer pattern, the method may further include removing an upper portion of the device isolation layer to expose a part of the preliminary charge trap layer.

In one embodiment of the present invention, the upper portion of the isolation layer may be removed until the height of the isolation layer is the same height as the lowest point of the etch stop layer pattern.

In an exemplary embodiment, the upper portion of the isolation layer may be removed to a point where the height of the isolation layer is equal to or higher than the lowest point of the preliminary charge trap layer.

A method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object is provided. A mask is formed on the substrate. The mask is used as an etch mask to remove a portion of the upper portion of the substrate, thereby forming a trench defining an active region protruding in a direction perpendicular to the plane on which the substrate is placed. An isolation layer is formed to fill the trench. The mask is removed to form an opening that exposes the active region. A continuous preliminary charge trap layer is formed on the sidewalls, the bottom surface of the opening, and the device isolation layer. An etch stop layer is formed on the preliminary charge trap layer. The charge trap layer is formed by removing the preliminary charge trap layer formed on the etch stop layer and the device isolation layer. The upper portion of the device isolation layer is removed. A portion of the charge trap film is removed to form a charge trap film pattern having a uniform thickness on the active region. A dielectric layer is formed on the charge trap layer pattern. A control gate is formed on the dielectric layer.

According to the present invention, when the charge trap layer is formed, an upper part of the preliminary device isolation layer is removed to expose a part of the preliminary charge trap layer, and then the exposed part of the preliminary charge trap layer is removed through an isotropic etching process. Accordingly, the charge trap layer may have a uniform thickness, and the nonvolatile memory device including the charge trap layer may have a uniform operating characteristic.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In each of the drawings of the present invention, the dimensions of the structures are shown in an enlarged scale than actual for clarity of the invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, each layer (film), region, electrode, pattern or structures is formed on, "on" or "bottom" of the object, substrate, each layer (film), region, electrode or pattern. When referred to as being meant that each layer (film), region, electrode, pattern or structure is formed directly over or below the substrate, each layer (film), region or patterns, or other layer (film) Other regions, different electrodes, different patterns, or different structures may be additionally formed on the object or the substrate. In addition, where materials, layers (films), regions, electrodes, patterns or structures are referred to as "first", "second" and / or "preliminary", it is not intended to limit these members, but only to each material, To distinguish between layers (films), regions, electrodes, patterns or structures. Thus, "first", "second" and / or "spare" may be used selectively or interchangeably for each layer (film), region, electrode, pattern or structure, respectively.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

That is, the present invention may be modified in various ways and may have various forms. Specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

1 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.

Referring to FIG. 1, the nonvolatile memory device includes a tunnel insulating layer 140, a first charge trap layer 154, a dielectric layer 180, and a control gate 190 formed on a substrate 100.

The substrate 100 may include silicon, germanium, silicon-germanium, silicon on insulator (SOI), germanium on insulator (GOI), or the like. The substrate 100 is divided into an active region and a field region, and the active region has a shape protruding in a direction substantially perpendicular to the plane on which the substrate 100 is placed.

The tunnel insulating layer 140 is formed on the active region. The tunnel insulating layer 1240 may be formed by oxidizing an upper portion of the active region of the substrate 100 by a thermal oxidation process.

Meanwhile, a first device isolation layer 134 is formed on the field region formed between the active regions. The first isolation film (134) comprises a USG (Undoped Silicate Glass) _{oxide, O 3 -TEOS USG (O 3} -Tetra Ethyl Ortho Silicate Undoped Silicate Glass) oxide or HDP (High Density Plasma) oxide. For example, the first device isolation layer 134 may be formed by filling trenches formed on the substrate 100.

An oxide film 102 is formed on sidewalls of the active region in contact with the first device isolation layer 134. The oxide film 102 may be formed by oxidizing sidewalls of the active region by a thermal oxidation process. The oxide film 102 may not be formed in some cases. The oxide film 102 may be formed on sidewalls of the trench. The oxide film 102 may cure the damage generated in the trench forming process.

The first charge trap layer 154 is formed on the tunnel insulating layer 140 and the oxide layer 102. In addition, the first charge trap layer 154 may be formed on a portion of the first device isolation layer 134. According to the exemplary embodiment of the present invention, the height of the edge portion of the first charge trap layer 154 is lower than that of the center portion on the substrate 100. The first charge trap layer 154 includes silicon nitride. Alternatively, when the present invention is applied to a charge trap type flash memory device, the first charge trap layer 154 is used as a floating gate, wherein the floating gate includes polysilicon or polysilicon doped with impurities. do.

The first charge trap layer 154 has a substantially uniform thickness. Unit cells of the nonvolatile memory device including the first charge trap layer 154 may have uniform operating characteristics.

The dielectric layer 180 is formed on the first charge trap layer 154 and the first device isolation layer 134. The dielectric layer 180 includes a high dielectric material and may be formed of a composite dielectric layer including an oxide film, a nitride film, and an oxide film.

The control gate 190 is formed on the dielectric layer 180. The control gate 190 includes polysilicon or metal silicide doped with impurities. The metal silicide includes, for example, tungsten silicide (WSix), titanium silicide (TiSix), cobalt silicide (CoSix), tantalum silicide (TaSix), and the like.

2 is a cross-sectional view illustrating a nonvolatile memory device in accordance with some example embodiments of the present invention. The nonvolatile memory device shown in FIG. 2 is different from the nonvolatile memory device shown in FIG. 1 only in that it has a second charge trap film 156 instead of the first charge trap film 154. Therefore, only the second charge trap film 156 will be described to avoid repetition of the description.

Referring to FIG. 2, the second charge trap layer 156 is formed on the tunnel insulating layer 140 and the oxide layer 102, and is not formed on the first device isolation layer 134. According to the exemplary embodiment of the present invention, the second charge trap layer 156 has a lower height of the edge portion of the substrate 100 than the center portion thereof. The second charge trap layer 156 includes silicon nitride.

Like the first charge trap layer 154, the second charge trap layer 156 has a substantially uniform thickness. Accordingly, unit cells of the nonvolatile memory device including the second charge trap layer 156 may have uniform operating characteristics.

3A to 3M are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with some embodiments of the present invention.

Referring to FIG. 3A, a pad film and a mask film are formed on the substrate 200. The substrate 200 may include silicon, germanium, silicon-germanium, silicon on insulator, germanium on insulator, or the like. The pad layer may be formed by oxidizing an upper portion of the substrate 200 by a thermal oxidation process. The pad layer is formed to suppress crystal defects on the upper surface of the substrate 200 and to reduce stress generated as the mask layer formed thereon directly contacts the upper surface of the substrate 200. The mask layer may be formed by performing a low pressure chemical vapor deposition (LPCVD) process using nitride. In this case, an anti-reflection film (not shown) may be further formed on the mask to prevent the sidewall profile of the photoresist pattern (not shown) from being poor due to diffuse reflection in a subsequent photolithography process.

The photoresist pattern is formed on the mask layer to cover the active area of the substrate 200 and expose the field area. The mask layer and the pad layer are etched using the photoresist pattern as an etch mask to form a pad layer pattern 210 and a mask 220 sequentially stacked on the active region of the substrate 200. The photoresist pattern can then be removed using an ashing and / or strip process.

Referring to FIG. 3B, the trench 205 is formed by dry etching the upper portion of the field region of the substrate 200 using the mask 220 and the pad layer pattern 210 as an etching mask.

Referring to FIG. 3C, an oxide film 202 is formed on the sidewalls of the trench 205 to cure damages on the sidewalls of the trenches 205 generated during the dry etching. The oxide film 202 can be formed by thermally oxidizing the sidewalls of the trench 205. In some cases, the oxide film 202 forming process may be omitted.

Meanwhile, a liner (not shown) may be further formed on the bottom of the trench 205, the oxide film 202, the pad film pattern 210, and the mask 220. The liner may be formed using silicon nitride. The liner enhances adhesion to the device isolation layer formed in a subsequent process and prevents leakage current from flowing to the substrate 200.

Referring to FIG. 3D, a first preliminary isolation layer 230 is formed on the substrate 200 to fill the trench 205. The first preliminary isolation layer 230 may be formed by performing a chemical vapor deposition (CVD) process on a USG oxide, an O ₃ -TEOS USG oxide, or an HDP oxide having excellent gap filling properties. In addition, the annealing process may be further performed under a high temperature and inert gas atmosphere of about 800 to 1050 ° C. in order to densify the first preliminary device isolation layer 230 to lower the wet etching rate for the subsequent cleaning process. It may be.

Meanwhile, the upper portion of the preliminary isolation layer 230 is planarized by using a chemical mechanical polishing (CMP) process and / or an etch back process to expose the mask 220.

Referring to FIG. 3E, the mask 220 is removed using a strip process or a wet etching process. The stripping process or the wet etching process may be performed using a phosphoric acid solution. In addition, the pad film pattern 210 is removed using a wet etching process. The wet etching process may be performed using hydrofluoric acid solution. Accordingly, the opening 235 exposing the active region of the substrate 200 is formed. The stripping process and the wet etching process are performed in an isotropic direction, and thus portions of the first preliminary device isolation layer 230 and the oxide layer 202 are also removed, so that the opening 235 is formed at the edge thereof. The depth is formed larger than the depth in the middle.

Referring to FIG. 3F, a tunnel insulating layer 240 is formed on the active region of the substrate 200 exposed by the opening 235. The tunnel insulating layer 240 may be formed by oxidizing the upper portion of the substrate 200 by a thermal oxidation process. In addition, the preliminary charge trap layer 250 is formed on the bottom and sidewalls of the opening 235 and the preliminary device isolation layer 230. The preliminary charge trap layer 250 may include silicon nitride. The preliminary charge trap layer 250 may be formed by depositing a silicon oxide layer and then performing plasma treatment using a gas containing nitrogen. Alternatively, the preliminary charge trap layer 250 may be formed by depositing silicon nitride. Alternatively, when the present invention is applied to a charge trap type flash memory device, the preliminary charge trap layer 250 is used to form a floating gate, wherein the floating gate is formed of polysilicon or polysilicon doped with impurities. It may include. In this case, the floating gate may be formed by depositing polysilicon or amorphous silicon by a low pressure chemical vapor deposition method, and then doping impurities.

Referring to FIG. 3G, an etch stop layer 260 is formed on the preliminary charge trap layer 250. The etch stop layer 260 fills the opening 235 and is formed on the preliminary charge trap layer 250. The etch stop layer 260 may be formed using polysilicon or amorphous silicon. The etch stop layer 260 serves to prevent a portion of the charge trap layer 252 (see FIG. 3I) formed on the active region from being etched when the first charge trap layer 254 (see FIG. 3J) is formed. Perform. Alternatively, the etch stop layer 260 may be formed by depositing BSG (Boron Silicate Glass) oxide, USG oxide, Middle Temperature Oxide (MTO), or the like by a chemical vapor deposition method.

Referring to FIG. 3H, upper portions of the etch stop layer 260 and the preliminary charge trap layer 250 are removed to expose the first preliminary device isolation layer 230. Accordingly, the etch stop layer 260 and the preliminary charge trap layer 250 are converted into the etch stop layer pattern 262 and the charge trap layer 252, respectively. Meanwhile, in order to prevent the exposed charge trap layer 252 from falling as a portion of the first preliminary device isolation layer 230 is removed in a subsequent process, the sacrificial layer 270 may have a minimum height of the preliminary charge trap layer 250. ), The upper portions of the first preliminary isolation layer 230 as well as the upper portions of the etch stop layer 260 and the preliminary charge trap layer 250 may be removed. Each of the upper portions of the etch stop layer 260 and the preliminary charge trap layer 250 and the upper portion of the first preliminary isolation layer 230 may be removed using a chemical mechanical polishing process and / or an etch back process.

Referring to FIG. 3I, an upper portion of the first preliminary device isolation layer 230 is removed to form a second preliminary device isolation layer 232. That is, the upper portion of the first preliminary element isolation layer 230 is removed to expose the upper portion of the charge trap layer 252 so that the second preliminary isolation layer 232 has the same height as the lowest point of the etch stop layer pattern 262. . Accordingly, the first preliminary isolation layer 230 is converted into a second preliminary isolation layer 232. The upper portion of the first preliminary isolation layer 230 may be removed through a dry etching process.

Referring to FIG. 3J, the upper portion of the exposed charge trap layer 252 is removed to form the first charge trap layer 254. The removal process may include an isotropic etching process. For example, the isotropic etching process may include a wet etching process or a chemical dry etching process. An upper portion of the exposed charge trap layer 252 may be etched in a direction parallel to the substrate as well as in a direction perpendicular to the substrate. Accordingly, the portion of the charge trap layer 252 positioned lower than the surface of the second preliminary isolation layer 232 may be removed. Therefore, the first charge trap layer 254 may have a uniform thickness regardless of the position. Meanwhile, the portion of the charge trap layer 252 covered by the etch stop layer pattern 262 is not etched.

Referring to FIG. 3K, an oxide film covering the etch stop layer pattern 262, the first charge trap layer 254, and the second preliminary isolation layer 232 is formed to form a first isolation layer 234. According to an embodiment of the present invention, the oxide film and the first device isolation layer 234 are formed of the same material as the second preliminary device isolation layer 232, so that the first device isolation layer 234 is the second preliminary element. The separator 232 will be included. That is, the oxide film and the first device isolation layer 234 may be formed by performing a chemical vapor deposition process on USG oxide, O ₃ -TEOS USG oxide or HDP oxide. Alternatively, this process can be omitted.

Referring to FIG. 3L, the upper portion of the first isolation layer 234 is removed to form the isolation layer 235. An upper portion of the first device isolation layer 234 is removed to expose a portion of the upper surface of the first charge trap layer 254. The upper portion of the first isolation layer 234 is removed until the height of the isolation layer 235 is equal to the height of the top surface of the edge portion of the first charge trap layer 254. An upper portion of the first device isolation layer 234 may be removed through a dry etching process. When the oxide formation process described with reference to FIG. 3K is omitted, the second preliminary element isolation layer until the height of the second preliminary element isolation layer 232 is the same as the top surface of the edge portion of the first charge trap layer 254. An upper portion of the portion 232 is removed to form the device isolation layer 235.

Referring to FIG. 3M, the etch stop layer pattern 262 is removed. The etch stop layer pattern 262 may be removed by a wet etching process. Meanwhile, an isotropic etching process may be further performed to smooth the surface of the first charge trap layer 254. Alternatively, the removal of the etch stop layer pattern 262 may be performed after the process illustrated in FIG. 3J or 3K.

Referring to FIG. 3N, a dielectric film 280 is formed on the device isolation layer 235 and the first charge trap layer 254. The dielectric layer 280 may be formed by a chemical vapor deposition process or an atomic layer deposition (ALD) process using a high dielectric material. The dielectric film 280 may be formed of a composite dielectric film including an oxide film, a nitride film, and an oxide film. Thereafter, the control gate 290 is formed on the dielectric layer 280. The control gate 290 may be formed by singly or mixing polysilicon or metal silicide doped with impurities. The metal silicide includes, for example, tungsten silicide (WSix), titanium silicide (TiSix), cobalt silicide (CoSix), tantalum silicide (TaSix), and the like.

A flash memory device in which the tunnel insulating layer 240, the first charge trap layer 254, the dielectric layer 280, and the control gate 290 are stacked is formed.

4A through 4F are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with some example embodiments of the present invention.

First, the processes substantially the same as those described with reference to FIGS. 3A to 3H are performed, and then the processes described with reference to FIGS. 4A to 4F are performed.

Referring to FIG. 4A, an upper portion of the first preliminary device isolation layer 230 is removed to form a third preliminary device isolation layer 236. That is, the upper part of the charge trap layer 252 is removed by removing the upper portion of the first preliminary element isolation layer 230 so that the third preliminary isolation layer 236 has a height higher than or equal to the lowest point of the charge trap layer 252. Expose As a result, the first preliminary isolation layer 230 is converted into a third preliminary isolation layer 236. The upper portion of the first preliminary isolation layer 230 may be removed through a dry etching process.

Referring to FIG. 4B, a portion of the exposed charge trap layer 252 is removed to form a second charge trap layer 256. The removal process may include an isotropic etching process. For example, the isotropic etching process may include a wet etching process or a chemical dry etching process. An upper portion of the exposed charge trap layer 252 may be etched in a direction parallel to the substrate as well as in a direction perpendicular to the substrate. Accordingly, a part of the edge of the second preliminary isolation layer 232 may be removed. That is, since the charge trap layer 252 is etched together not only in the vertical direction but also in the horizontal direction, all portions exposed to the outside without being covered by the etch stop layer pattern 262 of the charge trap layer 252 are etched. Therefore, the second charge trap layer 256 may have a uniform thickness regardless of the position. Meanwhile, the portion of the charge trap layer 252 covered by the etch stop layer pattern 262 is not etched.

3J illustrates a portion of the first charge trap layer 254 that is not covered by the etch stop layer pattern 262 and is exposed to the outside, whereas the second charge trap layer 256 has an etch stop layer pattern 262. The difference is that all parts which are not covered by) and are exposed to the outside are etched.

Referring to FIG. 4C, an oxide layer covering the etch stop layer pattern 262, the second charge trap layer 256, and the second preliminary element isolation layer 232 is formed to form a second element isolation layer 238. According to one embodiment of the present invention, the oxide film and the second device isolation layer 238 is formed of the same material as the second preliminary device isolation layer 232, so that the second device isolation layer 238 is a second preliminary device isolation layer And (232). That is, the oxide film and the second device isolation layer 238 may be formed by performing a chemical vapor deposition process on USG oxide, O ₃ -TEOS USG oxide or HDP oxide. Otherwise,

Referring to FIG. 4D, the upper portion of the second device isolation layer 238 is removed to form the device isolation layer 235. The upper portion of the second isolation layer 238 is removed until the height of the isolation layer 235 is equal to the height of the top surface of the edge portion of the second charge trap layer 256. The upper portion of the second device isolation layer 238 may be removed through a dry etching process.

Referring to FIG. 4E, the etch stop layer pattern 262 is removed. The etch stop layer pattern 262 may be removed by a wet etching process. Meanwhile, an isotropic etching process may be further performed to smooth the surface of the second charge trap layer 256. The order of the process shown in FIG. 4D and the process shown in FIG. 4E may be reversed. That is, the order of removing the etch stop layer pattern 262 and removing the upper portion of the second device isolation layer 238 may be performed in any order.

Referring to FIG. 4F, a dielectric film 280 is formed on the device isolation layer 235 and the second charge trap layer 256. The dielectric layer 280 may be formed by a chemical vapor deposition process or an atomic layer deposition (ALD) process using a high dielectric material. The dielectric film 280 may be formed of a composite dielectric film including an oxide film, a nitride film, and an oxide film. Thereafter, the control gate 290 is formed on the dielectric layer 280. The control gate 290 may be formed by singly or mixing polysilicon or metal silicide doped with impurities. The metal silicide includes, for example, tungsten silicide (WSix), titanium silicide (TiSix), cobalt silicide (CoSix), tantalum silicide (TaSix), and the like.

When the charge trap layer is formed, an upper part of the preliminary device isolation layer is removed to expose a part of the preliminary charge trap layer, and then the exposed part of the preliminary charge trap layer is removed through an isotropic etching process. Accordingly, the charge trap layer may have a uniform thickness, and the nonvolatile memory device including the charge trap layer may have a uniform operating characteristic.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. It will be appreciated that it can be changed.

1 is a cross-sectional view illustrating a nonvolatile memory device according to example embodiments.

2 is a cross-sectional view illustrating a nonvolatile memory device in accordance with some example embodiments of the present invention.

3A to 3N are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with embodiments of the present invention.

4A through 4F are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with some example embodiments of the present invention.

<Explanation of symbols for the main parts of the drawings>

200: substrate 205: trench

202: oxide film 210: pad film pattern

220: mask 234, 238: first and second device isolation film

254, 256: first and second charge trap films

Claims (10)

Forming a tunnel insulating film on the substrate; Forming a preliminary charge trap layer on the tunnel insulating layer; Forming an etch stop layer exposing the preliminary charge trap layer partially; Removing a portion of the exposed preliminary charge trap layer to form a charge trap layer having a uniform thickness; Forming a dielectric film on the charge trap film; And Forming a gate on the dielectric layer. The method of claim 1, wherein removing the portion of the preliminary charge trap layer comprises removing the isotropic etching process. The method of claim 2, further comprising removing the etch stop layer after removing a portion of the preliminary charge trap layer. The method of claim 1, wherein prior to forming the tunnel insulating film,  Forming a pad layer pattern and a mask on the substrate; Removing a portion of the upper portion of the substrate by using the pad layer pattern and the mask as an etching mask to form a trench defining an active region protruding in a plane on which the substrate is placed; Forming a device isolation layer filling the trench; And Removing the mask and the pad layer pattern to form an opening exposing the active region; And the tunnel insulating film is formed on the exposed active region. The method of claim 4, wherein the forming of the opening to expose the active region by removing the mask and the pad layer pattern includes a wet etching process and partially removes the device isolation layer. Way. The method of claim 5, wherein the preliminary charge trap layer is formed on a bottom surface and a sidewall of the opening. The method of claim 6, further comprising, after forming the etch stop layer pattern, removing the upper portion of the device isolation layer to expose a portion of the preliminary charge trap layer. The method of claim 7, wherein the upper portion of the isolation layer is removed until the height of the isolation layer is equal to the lowest point of the etch stop layer pattern. The method of claim 7, wherein the upper portion of the isolation layer is removed to a point at which the height of the isolation layer is equal to or higher than the lowest point of the preliminary charge trap layer. Forming a mask on the substrate; Removing the upper portion of the substrate using the mask as an etch mask to form a trench defining an active region protruding in a direction perpendicular to the plane on which the substrate is placed; Forming a device isolation layer filling the trench; Removing the mask to form an opening exposing the active region; Forming a continuous preliminary charge trap layer on the sidewalls, the bottom surface of the opening, and the device isolation layer; Forming an etch stop layer on the preliminary charge trap layer; Forming a charge trap layer by removing the preliminary charge trap layer formed on the etch stop layer and the device isolation layer; Removing an upper portion of the device isolation layer; Removing a portion of the charge trap layer to form a charge trap layer pattern having a uniform thickness on the active region; Forming a dielectric layer on the charge trap layer pattern; And Forming a control gate on the dielectric layer.

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