KR20100093182A - Nonvolatile memory device having nano particle and method for fabricating the same - Google Patents

Abstract

PURPOSE: A nonvolatile memory device including nano particles and a manufacturing method thereof are provided to improve charge storage density by arranging and distributing nano particles to a multilayer on the lower side of a control insulation layer. CONSTITUTION: A semiconductor layer(11s,11d) including conductive impurities is formed on a semiconductor substrate(10). A tunneling insulation layer(12) comprises a lower silicon oxide layer(12a), a silicon nitride layer(12b) and an upper silicon oxide layer(12c). A control insulation layer(13a) is positioned on the tunneling insulation layer. Nano particles(NP) of a multilayer is positioned on the lower region of the control insulation layer. A gate electrode(15) is positioned on the control insulation layer.

Description

Nonvolatile memory device having nanoparticles and method for manufacturing the same {Nonvolatile memory device having nano particle and method for fabricating the same}

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a nonvolatile memory device having nanoparticles as a charge storage body.

A floating gate type nonvolatile memory device, which is a type of nonvolatile memory device, uses a floating gate as a charge storage body. Specifically, the floating gate type nonvolatile memory device includes a tunneling insulating film, a floating gate, a control insulating film, and a control gate. However, in the floating gate type device, leakage of charge stored in the floating gate may occur when a defect occurs in the tunneling insulating layer. Therefore, in order to maintain device reliability, the tunneling insulating layer must be formed to have a thickness greater than or equal to a predetermined thickness. Accordingly, it may be difficult to lower the device operating voltage. In addition, the floating gate type device has a disadvantage in that it is difficult to increase the degree of integration due to the intercell interference effect.

In order to solve this problem, researches on a memory device using nanoparticles as a charge storage body, that is, a nano floating gate memory device (NFGM) has been started. Since the nano floating gate memory device stores charges in nanoparticles electrically separated from each other, all stored charges do not leak even when a defect occurs in the tunneling oxide layer. Therefore, the thickness of the tunneling oxide film can be reduced, thereby reducing the operating voltage.

However, in accordance with the demand for lowering power of the device, it is required to further reduce the operating voltage, and even if the operating voltage is decreased, the leakage current is not required to be increased.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a nonvolatile memory device having a reduced operating voltage without increasing leakage current and a method of manufacturing the same.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the present invention to achieve the above object provides a nonvolatile memory device. The nonvolatile memory device includes a tunneling insulating layer disposed on a substrate. The tunneling insulating film includes a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film. A control insulating film is disposed on the tunneling insulating film. Multi-layered nanoparticles are located in the lower region of the control insulating film. A gate electrode is disposed on the control insulating film.

The lower silicon oxide layer may have a thickness of 0.5 nm to 2 nm, the silicon nitride layer may have a thickness of 2 nm to 7.8 nm, and the upper silicon oxide layer may have a thickness of 0.5 nm to 2 nm. Further, the lower silicon oxide layer may have a thickness of 0.5 nm to 1.5 nm, the silicon nitride layer may have a thickness of 3.9 nm to 7.8 nm, and the upper silicon oxide layer may have a thickness of 0.5 nm to 1.5 nm.

The control insulating layer may include a lower control insulating layer and an upper control insulating layer, and the multilayer nanoparticles may be positioned in the lower control insulating layer. The nanoparticles may be silicon carbide nanoparticles.

In order to achieve the above object, an aspect of the present invention provides a method of manufacturing a nonvolatile memory device. The manufacturing method includes forming a tunneling insulating film including a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film on a substrate. A nanoparticle forming film is formed on the tunneling insulating film. A control insulating film is formed on the nanoparticle forming film. The substrate on which the control insulating film is formed is heat-treated to form multilayer nanoparticles in the control insulating film. A gate electrode film is formed on the control insulating film.

The control insulating layer may be a lower control insulating layer. In this case, the upper control insulating film may be formed on the lower control insulating film on which the multi-layered nanoparticles are formed before forming the gate electrode film. The nanoparticle forming film may be a silicon carbide film.

According to the present invention, since the charges are stored in the nanoparticles spaced apart from each other, the device using the nanoparticles as the charge storage body or the quantum dot can prevent the leakage of charges at the same time even if a defect occurs in the tunneling insulating film. In addition, by forming the thickness of the tunneling insulating film to the extent that can be directly tunneled, it is possible to significantly lower the device operating voltage. In addition, even when the charge write and erase operations are repeated, stress of the tunneling insulating layer can be reduced, durability can be increased, and operation speed can be improved.

The tunneling insulating film is formed to include a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film that are sequentially stacked, thereby exhibiting a low leakage current in a low electric field region, thereby improving charge sustainable voltage, and a high operating current in a high field region. It is possible to lower the programmable voltage, that is, the operating voltage.

In addition, when the nanoparticles are silicon carbide nanoparticles, the silicon carbide nanoparticles have a relatively large work function and have a deep quantum well, thereby improving data retention characteristics of the device. In addition, the nanoparticles may be dispersed in multiple layers within a portion of the lower portion of the control insulating layer, thereby increasing the charge storage density compared to the case where the nanoparticles are positioned in a single layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. In the figures, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween.

1A to 1G are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a semiconductor substrate 10 is provided. The semiconductor substrate 10 may be a silicon substrate or a silicon on insulator (SOI) substrate. The SOI substrate is a substrate including a base substrate, an insulating film, and a silicon layer, and has an advantage of reducing leakage current.

A semiconductor film 11 containing conductive impurities, for example, a silicon film doped with impurities, for example, an amorphous silicon film doped with phosphorus or a polycrystalline silicon film doped with phosphorus may be formed on the semiconductor substrate 10. have. The semiconductor film 11 may be formed on the substrate 10 by using a deposition method. However, the present invention is not limited thereto and may be formed by doping impurities entirely in the substrate 10.

Referring to FIG. 1B, the photoresist pattern PR may be formed on the semiconductor film 11, and the semiconductor film 11 may be etched using the photoresist pattern PR as a mask. In this case, an upper portion of the substrate 10 under the semiconductor film 11 may also be etched. As a result, a channel recess portion R may be formed in the semiconductor film 11, or in the semiconductor film 11 and the substrate 10. Regions of the semiconductor film 11 disposed on both sides of the channel recess R may be defined as a source region 11s and a drain region 11d.

Referring to FIG. 1C, the photoresist pattern (PR of FIG. 1B) is removed. The natural oxide layer formed in the channel recess R may be removed simultaneously with or separately from the photoresist pattern PR. When removing the natural oxide film, it is possible to improve the quality of the tunneling insulating film to be described later and the thickness control can be easy.

Thereafter, the tunneling insulating layer 12 is formed on the substrate including the channel recess R. Referring to FIG. The tunneling insulating layer 12 may have a thickness capable of direct tunneling, that is, an equivalent oxide thickness (EOT) of about 3 nm to about 6 nm. When the tunneling insulating layer 12 has the thickness range, direct tunneling of electrons is possible, and the dielectric layer may not be destroyed even when continuous electric stress occurs during device operation.

The tunneling insulating layer 12 may include a lower silicon oxide layer 12a, a silicon nitride layer 12b, and an upper silicon oxide layer 12c that are sequentially stacked. In this case, a low leakage current may be exhibited in the low electric field to improve the charge sustainable voltage, and a high operating current may be exhibited in the high electric field to reduce the programmable voltage, that is, the operating voltage. To this end, the lower silicon oxide film 12a may have a thickness of about 0.5 nm to about 2 nm, and the silicon nitride film 12b may have a thickness of about 2 nm to about 7.8 nm, and the upper silicon oxide film ( 12c) may have a thickness of about 0.5 nm to about 2 nm. Specifically, the lower silicon oxide film 12a may have a thickness of about 0.5 nm to about 1.5 nm, and the silicon nitride film 12b may have a thickness of about 3.9 nm to about 7.8 nm, and the upper silicon oxide film 12c may have a thickness of about 0.5 nm to about 1.5 nm.

The lower silicon oxide layer 12a may be formed by chemical vapor deposition (CVD) such as atomic layer deposition (ALD), in-situ steam generation (ISSG), wet oxidation (Wet Oxidation), or dry oxidation ( The film may be formed using a dry oxide method, and the silicon nitride film 12b and the upper silicon oxide film 12c may be formed using chemical vapor deposition (CVD), such as atomic layer deposition (ALD).

Referring to FIG. 1D, a nanoparticle forming film SC is formed on the tunneling insulating film 12. The nanoparticle forming film SC may be a silicon carbide film. The nanoparticle forming film SC may be formed by physical vapor deposition (PVD), specifically, by sputtering, and may have a thickness of about 5 nm to about 8 nm. When the nanoparticle forming film SC has a thickness in the above range, nanoparticles electrically separated from each other may be formed at an appropriate density in a subsequent process, and the nanoparticles may maintain good charge. It can be made to have a diameter enough.

A lower control insulating layer 13a is formed on the nanoparticle forming layer SC. The lower control insulating layer 13a may be a silicon oxide layer. The lower control insulation layer 13a may be formed to a thickness of 10 nm to 50 nm by using physical vapor deposition or chemical vapor deposition. When the lower control insulating layer 13a has the thickness in the above range, nanoparticles NP formed in a subsequent heat treatment process without causing a large increase in operating voltage are independently formed in the lower control insulating layer 13a. Can be dispersed.

Referring to FIG. 1E, the substrate on which the lower control insulating layer 13a is formed is heat treated. In this case, a material forming the nanoparticle forming layer MS, for example, silicon carbide, is diffused into the lower control insulating layer 13a and partially agglomerated to form dispersed nanoparticles NP. The nanoparticles NP may be formed in a multilayer, not a single layer, and may be electrically separated from each other by a material forming the lower control insulating layer 13a. The nanoparticles NP may be about 2 nm to about 10 nm, which is very small, thereby miniaturizing the nonvolatile memory device, thereby improving device integration. In addition, the multi-layered nanoparticles (NP) can improve the charge storage density compared to the nanoparticles of a single layer. The nanoparticles may be formed at a density of 1 × 10 ¹¹ to 1 × 10 ¹² per unit area (1 cm ² ).

The heat treatment may be performed in an inert gas atmosphere, for example, nitrogen (N ₂ ) atmosphere, and may be performed by using Rapid Thermal Annealing (RTA) or a furnace. The heat treatment may be generated by dispersing the nanoparticles NP in multiple layers, may be formed in a uniform size, and may be 700 ° C. to 900 ° C. so as not to break down the lower control insulating layer 13a. Can be carried out at a temperature. When the heat treatment is carried out in a rapid heat treatment equipment, it may be performed for 3 minutes to 5 minutes to supply sufficient thermal energy to form a multi-layer nanoparticles and to uniformly form the nanoparticles.

Referring to FIG. 1F, an upper control insulating layer 13b is formed on the lower control insulating layer 13a. The upper control insulating layer 13b and the lower control insulating layer 13a form a control insulating layer 13, and the nanoparticles NP are dispersed in multiple layers in a lower portion of the control insulating layer 13. Can be. The upper control insulating layer 13b is a silicon oxide film, or a film having a higher dielectric constant than the tunneling insulating film 12, for example, a hafnium oxide film (HfO ₂ ), a zirconium oxide film (ZrO ₂ ), or an aluminum oxide film (Al ₂ O _3). May be).

The upper control insulating layer 13b may have an equivalent oxide film thickness (EOT) of 10 nm to 20 nm. When the thickness of the upper control insulating layer 13b is less than 10 nm, a leakage current may flow in the upper control insulating layer 13b. In addition, when the thickness of the upper control insulating layer 13b exceeds 20 nm, the device operating voltage may increase. The upper control insulating layer 13b may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

Referring to FIG. 1F, a gate electrode film 15 is formed on the upper control insulating film 13b. The gate electrode film 15 may be aluminum (Al), gold (Au), platinum (Pt), copper (Cu), or an alloy film thereof, or may be a laminated film of a polysilicon film or a polysilicon film and a metal silicide film. .

Referring to FIG. 1G, a photoresist pattern (not shown) is formed on the gate conductive layer 15, and the gate conductive layer 15 is patterned using the photoresist pattern as a mask to form a gate electrode. Using the gate electrode as a hard mask, the control insulating layer 13 and the tunneling insulating layer 12 are sequentially patterned to form a gate structure S. FIG. The channel length of the nonvolatile memory device having the gate structure S may be defined as the distance L _CH between the source / drain regions 11s and 11d. As such, by forming the gate structure S in the channel recess R, the channel length may be increased as compared with a conventional planar type nonvolatile memory device. As a result, the short channel effect due to the decrease in the channel length can be reduced.

As such, when the device using the nanoparticles NP as a charge storage body or a quantum dot, charges are stored in the nanoparticles NP spaced apart from each other, even when a defect occurs in the tunneling insulating layer 12, the charges leak at once. The phenomenon can be prevented. In addition, by forming the thickness of the tunneling insulating layer 12 to a thickness such that direct tunneling is possible, it is possible to significantly lower the device operating voltage. In addition, even when the charge write and erase operations are repeated, the stress of the tunneling insulating layer 12 can be reduced, durability can be increased, and operation speed can be improved.

Since the silicon carbide nanoparticles (NP) have a relatively large work function and have a deep quantum well, data retention characteristics may be excellent. In addition, the nanoparticles NP may be dispersed in multiple layers in a portion of the lower portion of the control insulating layer 13, and thus the charge storage density may be improved as compared with the case where the nanoparticles NP are positioned in a single layer.

2 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device according to another exemplary embodiment of the present invention. The method of manufacturing the nonvolatile memory device according to the present embodiment is similar to the method of manufacturing the nonvolatile memory device described with reference to FIGS. 1A to 1G except as described below.

Referring to FIG. 2, the gate structure S is formed on the semiconductor substrate 10 using the method described with reference to FIGS. 1B through 1G. The semiconductor substrate 10 may be a substrate on which a semiconductor film 11 of FIG. 1A is not formed. Using the gate structure S as a mask, conductive impurities are implanted into the substrate 10 to form a source region 12s and a drain region 12d. The channel length L _CH of such a device may be defined as the distance between the source / drain regions 12s and 12d.

Hereinafter, preferred examples are provided to aid the understanding of the present invention. However, the following experimental examples are only for helping understanding of the present invention, and the present invention is not limited to the following experimental examples.

<Gate Capacitor Manufacturing Example 1>

Thermal Oxidation at 700 ° C on Silicon Substrate After forming a 0.5 nm silicon oxide film, using a LP-Nitride method at 720 ℃ to form a silicon nitride film of 7.8 nm, using a LP-TEOS method at 620 ℃ to form a 0.5 nm silicon oxide film A tunnel insulating film having a three-layer structure was formed. An 8 nm silicon carbide film was formed on the tunnel insulating film having the three-layer structure by using a sputtering method (Radio-frequence magnetron sputter). A 50 nm silicon oxide film was formed on the silicon carbide film. The resultant was heat-treated at 900 ° C. for 3 minutes using Rapid Thermal Annealing (RTA). At this time, the silicon oxide film formed on the silicon carbide film was reduced to about 30nm and the multilayer silicon carbide nanoparticles were formed therein.

Thereafter, a 20 nm silicon oxide film was further formed on the resultant. A 150 nm aluminum layer was formed on the silicon insulating layer using a thermal deposition method, and then patterned to form a gate electrode, and then the lower layers were patterned using the gate electrode as a hard mask to form a gate structure. The substrate and the gate structure constitute a gate capacitor.

<Gate Capacitor Manufacturing Example 2>

A gate capacitor was manufactured in the same manner as in Production Example 1, except that a tunnel insulating film having a three-layer structure was formed by sequentially forming a 1 nm silicon oxide film, a 5.8 nm silicon nitride film, and a 1 nm silicon oxide film.

<Gate Capacitor Manufacturing Example 3>

A gate capacitor was manufactured in the same manner as in Production Example 1, except that a tunnel insulating film having a three-layer structure was formed by sequentially forming a 1.5 nm silicon oxide film, a 3.9 nm silicon nitride film, and a 1.5 nm silicon oxide film. .

<Gate Capacitor Manufacturing Example 4>

A gate capacitor was manufactured in the same manner as in Production Example 1, except that a tunnel insulating film having a three-layer structure was formed by sequentially forming a 2 nm silicon oxide film, a 2 nm silicon nitride film, and a 2 nm silicon oxide film.

<Gate Capacitor Comparative Example 1>

A gate capacitor was manufactured in the same manner as in Production Example 1, except that a 9.8 nm silicon nitride film was formed to form a tunnel insulating film having a single layer structure.

<Gate Capacitor Comparative Example 2>

A gate capacitor was manufactured in the same manner as in Preparation Example 1, except that a 5 nm silicon oxide film was formed to form a tunnel insulating film having a single layer structure.

3 is a FE-TEM (Field-Emission Transmission Electron Microscope) photograph of a part of a cross section of the gate capacitor according to Preparation Example 1. FIG.

Referring to FIG. 3, it can be seen that the tunnel insulating film has a three-layer structure of silicon oxide film / silicon nitride film / silicon oxide film. In addition, it can be seen that the silicon carbide nanoparticles are separated from each other and uniformly distributed in multiple layers on the tunnel insulating film. The silicon carbide nanoparticles were found to have an average diameter of about 7 nm.

4A is a graph illustrating flat voltages according to applied voltages in gate capacitor structures according to Preparation Example 1 and Comparative Example 2. FIG. Specifically, the substrate voltages of the gate capacitors according to Preparation Example 1 and Comparative Example 2 were grounded, and the voltage applied to the gate electrode was varied as shown in the graph, but the pulse applied voltage was fixed at 500 ms. In addition, 1-MHz C-V measurement equipment was used to measure this.

Referring to FIG. 4A, in the case of Preparation Example 1 (three-layer tunnel insulating film), the change in the flat voltage was shown at a lower voltage (absolute value basis) than in Comparative Example 2 (single layer tunnel insulating film). From this, it can be seen that in the case of Preparation Example 1 (three-layer tunnel insulating film), the charge is stored in the silicon carbide nanoparticles even at a lower voltage than in Comparative Example 2 (single layer tunnel insulating film).

4B is a graph showing flat band voltages according to write / erase operation cycles in the gate capacitor structures according to Preparation Example 1 and Comparative Example 2. FIG. Specifically, while applying a voltage of 10 V as a write voltage and a voltage of −10 V as an erase voltage to the gate electrode, the flat band voltage was measured while changing the period of the write pulse and the erase pulse.

Referring to FIG. 4B, it can be seen that the gate capacitor according to Preparation Example 1 had a flat voltage difference of about 0.5 V, that is, a memory window even when the write / erase pulse period, that is, the write / erase period was 1 ms. However, in the gate capacitor according to Comparative Example 2, when the write / erase period is 1ms, the memory window is hardly seen, and thus the charge storage in the nanoparticles is hardly achieved.

From this, it can be seen that the gate capacitor according to Preparation Example 1 has an improved operation speed compared to other gate capacitors in Comparative Example 2.

4C is a graph showing data retention characteristics of the gate capacitor structures according to Preparation Example 1 and Comparative Example 2. FIG. Specifically, in the case of the gate capacitor according to Preparation Example 1, a voltage of 10 V was applied to the gate electrode for 500 ms for a write voltage, and then the flat band voltage was measured for 1000 seconds, which is a holding time, and -10 to the erase voltage for the gate electrode. After applying a voltage of V for 500ms, the flat band voltage was measured for 1000 seconds, which is a holding time. In the case of the gate capacitor according to Comparative Example 2, a voltage of 28 V was applied to the gate electrode for 500 ms and a flat band voltage was measured for 1000 seconds as a holding time. After applying for 500ms, the flat band voltage was measured for 1000 seconds, the retention time.

Referring to FIG. 4C, when the state in which the data is written and the erased state is continued for 1000 seconds in the gate capacitors according to Preparation Example 1 and Comparative Example 2, ΔV _FB of 2.5 V or more was confirmed. However, the gate capacitor according to Comparative Example 2 has a very high write voltage and erase voltage of 28V. Therefore, it can be seen that the nonvolatile memory characteristics of the gate capacitor according to Preparation Example 1 were further improved.

FIG. 5 is a graph showing gate currents according to gate voltages of gate capacitors according to Preparation Examples 1 to 4 and Comparative Examples 1 and 2. FIG.

From FIG. 5, the programmable voltage and the charge maintainable voltage were extracted and shown in Table 1 below. Specifically, the programmable voltage was extracted based on the gate voltage when the gate current was 10 ^-2 A / um ² , and the charge maintainable voltage was based on the gate voltage when the gate current was 10 ^-16 A / um ^2. Extracted with.

TABLE 1

Comparative Example 1 Preparation Example 1 Production Example 2 Production Example 3 Preparation Example 4 Comparative Example 2 Bottom silicon oxide thickness (nm) 0 0.5 One 1.5 2 2.5 Silicon nitride film thickness (nm) 9.8 7.8 5.8 3.9 2 0 Bottom silicon oxide thickness (nm) 0 0.5 One 1.5 2 2.5 Total thickness of tunnel insulation film (nm) 9.8 8.8 7.8 6.9 6 5 EOT 5 5 5 5 5 5 Programmable Voltages (Vprg, V) 6.18 4.48 4.49 4.04 3.89 4.08 Chargeable Voltages (Vret, V) 2.74 2.41 2.41 2.11 1.47 0.15 Vprg / Vret 2.26 1.86 1.86 1.91 2.65 27.20

Referring to FIG. 5 and Table 1, in the case of using the tunnel insulating film having a triple structure (Manufacturing Examples 1 to 4), the lower leakage in the low electric field region compared to the case of using the silicon insulating film single structure tunnel insulating film (Comparative Example 2) The current can be improved by showing the current, and the charge holding voltage can be improved, and the programmable voltage, that is, the operating voltage can be lowered by exhibiting a higher operating current in the high field region than when the tunnel insulating film having the silicon nitride film single structure is used (Comparative Example 1). It can be seen.

Particularly, in Examples 1 to 3, the charge-maintainable voltage was 2V or more, which is higher than that of Preparation Example 4, but the programmable voltage was 4V, indicating excellent device characteristics.

From this, the lower silicon oxide film constituting the tunnel insulating film may have a thickness of about 0.5 nm to about 2 nm, the silicon nitride film may have a thickness of about 2 nm to about 7.8 nm, and the upper silicon oxide film is about 0.5 nm to about It can be seen that it can have a thickness of 2nm. Further, the lower silicon oxide film may have a thickness of about 0.5 nm to about 1.5 nm, the silicon nitride film may have a thickness of about 3.9 nm to about 7.8 nm, and the upper silicon oxide film may have a thickness of about 0.5 nm to about 1.5 nm. It can be seen that having a.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention. This is possible.

1A to 1G are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a method of manufacturing a nonvolatile memory device according to another exemplary embodiment of the present invention.

3 is a FE-TEM (Field-Emission Transmission Electron Microscope) photograph of a part of a cross section of the gate capacitor according to Preparation Example 1. FIG.

4A is a graph illustrating flat voltages according to applied voltages in gate capacitor structures according to Preparation Example 1 and Comparative Example 2. FIG.

4B is a graph showing flat band voltages according to write / erase operation cycles in the gate capacitor structures according to Preparation Example 1 and Comparative Example 2. FIG.

4C is a graph showing data retention characteristics of the gate capacitor structures according to Preparation Example 1 and Comparative Example 2. FIG.

FIG. 5 is a graph showing gate currents according to gate voltages of gate capacitors according to Preparation Examples 1 to 4 and Comparative Examples 1 and 2. FIG.

Claims (10)

A tunneling insulating film including a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film disposed on the substrate; A control insulating film disposed on the tunneling insulating film; Multilayer nanoparticles positioned in a lower region of the control insulating layer; And And a gate electrode disposed on the control insulating layer. The method of claim 1, The lower silicon oxide film has a thickness of 0.5 nm to 2 nm, The silicon nitride film has a thickness of 2nm to 7.8nm, The upper silicon oxide layer has a thickness of 0.5 nm to 2 nm. The method of claim 2, The lower silicon oxide film has a thickness of 0.5 nm to 1.5 nm, The silicon nitride film has a thickness of 3.9nm to 7.8nm, The upper silicon oxide layer has a thickness of 0.5 nm to 1.5 nm. The method of claim 1, The control insulating film includes a lower control insulating film and an upper control insulating film, The multilayer nanoparticles are located in the lower control insulating layer. The method of claim 1, The nanoparticles are silicon carbide nanoparticles. Forming a tunneling insulating film including a lower silicon oxide film, a silicon nitride film, and an upper silicon oxide film on a substrate; Forming a nanoparticle forming film on the tunneling insulating film; Forming a control insulating film on the nanoparticle forming film; Heat treating the substrate on which the control insulating film is formed to form multilayer nanoparticles in the control insulating film; And And forming a gate electrode film on the control insulating film. The method of claim 6, The lower silicon oxide film is formed to a thickness of 0.5nm to 2nm, The silicon nitride film is formed to a thickness of 2nm to 7.8nm, And forming the upper silicon oxide layer to a thickness of 0.5 nm to 2 nm. The method of claim 7, wherein The lower silicon oxide film is formed to a thickness of 0.5nm to 1.5nm, The silicon nitride film is formed to a thickness of 3.9nm to 7.8nm, And forming the upper silicon oxide layer to a thickness of 0.5 nm to 1.5 nm. The method of claim 6, The control insulating film is a lower control insulating film, And forming an upper control insulating film on the lower control insulating film on which the multi-layered nanoparticles are formed before forming the gate electrode film. The method of claim 6, The nanoparticle forming film is a silicon carbide film manufacturing method of a nonvolatile memory device.

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