KR100455365B1 - Method for forming inter-polysilicon dielectric layer of non-volitile memory device - Google Patents

Method for forming inter-polysilicon dielectric layer of non-volitile memory device Download PDF

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KR100455365B1
KR100455365B1 KR1019970017398A KR19970017398A KR100455365B1 KR 100455365 B1 KR100455365 B1 KR 100455365B1 KR 1019970017398 A KR1019970017398 A KR 1019970017398A KR 19970017398 A KR19970017398 A KR 19970017398A KR 100455365 B1 KR100455365 B1 KR 100455365B1
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oxide film
film
tantalum oxide
forming
gate electrode
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KR19980082470A (en
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김영대
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

PURPOSE: A method for forming a polysilicon interlayer dielectric of an NVM(non-volatile memory) device is provided to prevent the oxygen in a tantalum oxide layer from being diffused to conductive layers for a floating gate electrode and a control gate electrode in a heat treatment process by forming the first and second nitride layers under and on the tantalum oxide layer, respectively. CONSTITUTION: A rapid thermal process using ammonia gas is performed on a conductive layer for a floating gate to sequentially form the first nitride layer(7) with a thickness of 5-20 angstroms and the first oxide layer(9). A tantalum oxide layer is formed on the first oxide layer. A rapid thermal process using ammonia gas is performed on the tantalum oxide layer to sequentially form the second nitride layer(13) with a thickness of 5-20 angstroms and the second oxide layer(15).

Description

비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법{Method for forming inter-polysilicon dielectric layer of non-volitile memory device}Method for forming inter-polysilicon dielectric layer of non-volitile memory device

본 발명은 반도체소자에 사용되는 유전체막 형성방법에 관한 것으로, 특히 비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a dielectric film for use in semiconductor devices, and more particularly, to a method of forming a polysilicon interlayer dielectric film of a nonvolatile memory device.

일반적으로, 비휘발성 기억소자의 메모리 셀은 전하를 저장시키는 플로팅 게이트 및 원하는 메모리 셀을 선택하기 위한 콘트롤 게이트 전극이 차례로 적층된 구조를 갖는다. 플로팅 게이트는 메모리 셀 트랜지스터의 채널영역 상에 터널산화막에 의해 이격되어 형성되고, 콘트롤 게이트 전극 및 폴로팅 게이트 사이에는 폴리실리콘층간 유전체막이 개재되어 있다. 이와 같은 구조를 갖는 비휘발성 기억소자의 셀에 정보를 저장시키기 위한 프로그램 동작은 상기 콘트롤 게이트 전극에 12V 내지 15V의 고전압을 인가하여 채널영역으로부터 플로팅 게이트로 전자를 주입시킴으로써 이루어진다. 이때, 콘트롤 게이트 전극에 고전압, 즉 프로그램 전압을 인가하게 되면, 플로팅 게이트에 소정의 전압이 유기되어 터널산화막을 가로지르는 전계가 형성된다. 이에 따라, 채널영역의 전자가 터널산화막을 통과하여 플로팅 게이트로 주입된다. 결과적으로, 비휘발성 메모리 소자의 셀을 효율적으로 프로그램시키기 위해서는 콘트롤 게이트 전극에 소정의 프로그램 전압이 인가된 상태에서 플로팅 게이트에 유기되는 전압을 최대한 높여야 한다. 이를 위해서는 터널산화막에 의한 커패시턴스(Ctox)와 폴리실리콘층간 유전체막에 의한 커패시턴스(Cipo)로 표현되는 커플링 비율(coupling ratio;C.R.)을 증가시켜야 한다. 여기서, 커플링 비율(C.R.)을 수식으로 나타내면 다음과 같다.In general, a memory cell of a nonvolatile memory device has a structure in which a floating gate for storing charge and a control gate electrode for selecting a desired memory cell are sequentially stacked. The floating gate is formed on the channel region of the memory cell transistor by a tunnel oxide film, and a polysilicon interlayer dielectric film is interposed between the control gate electrode and the floating gate. A program operation for storing information in a cell of a nonvolatile memory device having such a structure is performed by injecting electrons from a channel region into a floating gate by applying a high voltage of 12V to 15V to the control gate electrode. At this time, when a high voltage, that is, a program voltage is applied to the control gate electrode, a predetermined voltage is induced in the floating gate to form an electric field crossing the tunnel oxide film. Accordingly, electrons in the channel region pass through the tunnel oxide film and are injected into the floating gate. As a result, in order to program the cell of the nonvolatile memory device efficiently, the voltage induced in the floating gate should be increased as much as possible while a predetermined program voltage is applied to the control gate electrode. To this end, the coupling ratio (C.R.) expressed by the capacitance (Ctox) by the tunnel oxide film and the capacitance (Cipo) by the polysilicon interlayer dielectric film should be increased. Here, the coupling ratio (C.R.) is expressed by the following formula.

[수학식][Equation]

C.R.=Cipo/(Cipo+Ctox)C.R. = Cipo / (Cipo + Ctox)

상기 수학식으로부터 커플링 비율(C.R.)을 증가시키기 위해서는 폴리실리콘층간 커패시턴스(Cipo)를 증가시켜야 함을 알 수 있다. It can be seen from the above equation that in order to increase the coupling ratio C.R., it is necessary to increase the polysilicon interlayer capacitance Cipo.

상술한 폴리실리콘층간 커패시턴스(Cipo)를 증가시키기 위한 방법으로 플로팅 게이트 및 콘트롤 게이트 전극 사이의 유전체막을 유전상수가 높은 탄탈륨 산화막으로 형성하는 방법이 제안된 바 있다. 그러나, 탄탈륨 산화막을 유전체막으로 사용할 경우에 후속 열처리공정시 탄탈륨 산화막 내의 산소가 폴리실리콘막으로 형성된 플로팅 게이트 및 콘트롤 게이트 전극으로 확산되는 환원반응이 발생한다. 이러한 환원반응이 발생하면, 탄탈륨 산화막 내의 산소가 결핍되어 탄탈륨 산화막 내에 산소공공(oxygen vacancy)이 생성되고, 이에 따라 탄탈륨 산화막의 막질이 저하되어 플로팅 게이트 및 콘트롤 게이트 전극 사이에 누설전류가 증가한다.As a method for increasing the above-described polysilicon interlayer capacitance (Cipo), a method of forming a dielectric film between a floating gate and a control gate electrode as a tantalum oxide film having a high dielectric constant has been proposed. However, when the tantalum oxide film is used as the dielectric film, a reduction reaction occurs in which oxygen in the tantalum oxide film diffuses to the floating gate and the control gate electrode formed of the polysilicon film during the subsequent heat treatment process. When such a reduction reaction occurs, oxygen in the tantalum oxide film is deficient and oxygen vacancies are generated in the tantalum oxide film. As a result, the film quality of the tantalum oxide film is degraded to increase the leakage current between the floating gate and the control gate electrode.

본 발명의 목적은 커플링 비율을 증가시킬 수 있는 불휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법을 제공하는 데 있다.An object of the present invention is to provide a method for forming a polysilicon interlayer dielectric film of a nonvolatile memory device capable of increasing the coupling ratio.

상기 목적을 달성하기 위하여 본 발명은 플로팅 게이트용 도전막 상에 제1 질화막 및 제1 산화막을 차례로 형성하는 단계와, 상기 제1 산화막 상에 탄탈륨 산화막을 형성하는 단계와, 상기 탄탈륨 산화막 상에 제2 질화막 및 제2 산화막을 차례로 형성하는 단계와, 상기 제2 산화막 상에 콘트롤 게이트 전극용 도전막을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention comprises the steps of sequentially forming a first nitride film and a first oxide film on a conductive film for a floating gate, forming a tantalum oxide film on the first oxide film, and a first on the tantalum oxide film And sequentially forming a second nitride film and a second oxide film, and forming a conductive film for a control gate electrode on the second oxide film.

여기서, 상기 플로팅 게이트용 도전막 및 콘트롤 게이트 전극용 도전막은 도우핑된 폴리실리콘막으로 형성하는 것이 바람직하다.The floating gate conductive layer and the control gate electrode conductive layer may be formed of a doped polysilicon layer.

본 발명에 의하면, 상기 탄탈륨 산화막의 하부 및 상부에 각각 제1 및 제2 질화막을 형성함으로써, 후속 열공정시 탄탈륨 산화막 내의 산소가 플로팅 게이트용 도전막 또는 콘트롤 게이트 전극용 도전막으로 확산되는 현상을 방지할 수 있다. 이에 따라, 탄탈륨 산화막 내에 산소공공이 생성되는 것을 억제시킬 수 있으므로 막질이 우수한 폴리실리콘층간 유전체막을 형성할 수 있다.According to the present invention, the first and second nitride films are formed on the lower and upper portions of the tantalum oxide film, respectively, to prevent the diffusion of oxygen in the tantalum oxide film into the conductive film for the floating gate or the conductive film for the control gate electrode during the subsequent thermal process. can do. As a result, the generation of oxygen vacancies in the tantalum oxide film can be suppressed, so that a polysilicon interlayer dielectric film having excellent film quality can be formed.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1은 플로팅 게이트용 도전막(5) 및 탄탈륨 산화막(11)을 형성하는 단계를 설명하기 위한 단면도이다. 구체적으로 설명하면, 반도체기판(1) 상에 60Å 내지 100Å의 터널산화막(3)을 열산화막으로 형성하고, 상기 터널산화막(3) 상에 플로팅 게이트용 도전막(5), 예컨대 폴리실리콘막을 형성한다. 이어서, 상기 플로팅 게이트용 도전막(5) 상에 5Å 내지 20Å의 두께를 갖는 제1 질화막(7)을 형성한다. 바람직하게는, 상기 제1 질화막(7)은 암모니아 가스를 사용하는 급속열처리 공정으로 형성한다. 다음에, 상기 제1 질화막(7) 상에 산소 가스를 사용하는 급속열처리 공정으로 제1 산화막(9)을 형성한다. 상기 제1 질화막(7) 및 제1 산화막(9)은 급속열처리 장비 내에서 반응 가스만을 바꾸어줌으로써, 인시투 방식으로 차례로 형성할 수 있다. 계속해서, 상기 제1 산화막(9) 상에 화학기상증착 방법으로 탄탈륨 산화막(11)을 100Å 내지 1000Å의 두께로 형성한다. 1 is a cross-sectional view for explaining a step of forming a conductive film 5 and a tantalum oxide film 11 for a floating gate. Specifically, a 60 to 100 터널 tunnel oxide film 3 is formed as a thermal oxide film on the semiconductor substrate 1, and a floating gate conductive film 5, for example, a polysilicon film is formed on the tunnel oxide film 3. do. Subsequently, a first nitride film 7 having a thickness of 5 GPa to 20 GPa is formed on the conductive film 5 for floating gate. Preferably, the first nitride film 7 is formed by a rapid heat treatment process using ammonia gas. Next, the first oxide film 9 is formed on the first nitride film 7 by a rapid heat treatment process using oxygen gas. The first nitride film 7 and the first oxide film 9 may be sequentially formed in an in-situ manner by changing only the reaction gas in the rapid heat treatment equipment. Subsequently, a tantalum oxide film 11 is formed on the first oxide film 9 in a thickness of 100 kPa to 1000 kPa by chemical vapor deposition.

도 2는 제2 질화막(13), 제2 산화막(15), 및 콘트롤 게이트 전극용 도전막(17)을 형성하는 단계를 설명하기 위한 단면도이다. 상세히 설명하면, 상기 탄탈륨 산화막(11) 내에 존재하는 산소공공을 감소시키기 위하여 상기 탄탈륨 산화막(11)이 형성된 결과물을 자외선 오존 분위기에서 어닐링시킴으로써, 산소공공이 감소된 탄탈륨 산화막(11a)을 형성한다. 상기 자외선 오존 어닐링 공정은 필요에 따라 생략할 수도 있다. 이어서, 상기 자외선 오존 어닐링된 탄탈륨 산화막(11a) 상에 제1 질화막(7) 형성방법과 동일한 방법으로 제2 질화막(13)을 형성한다. 다음에, 상기 제2 질화막(13)이 형성된 결과물을 800℃ 내지 900℃의 온도에서 건식 산화공정으로 열산화시킴으로써 제2 질화막(13) 표면에 제2 산화막(15)을 형성한다. 계속해서, 상기 제2 산화막(15) 상에 콘트롤 게이트 전극용 도전막(17)을 형성한다. 상기 콘트롤 게이트 전극용 도전막(17)은 폴리실리콘막으로 형성하는 것이 바람직하다. 이와 같이 형성된 제1 및 제2 질화막(7, 13)은 후속열공정시 탄탈륨 산화막(11a) 내의 산소가 플로팅 게이트용 도전막(5) 및 콘트롤 게이트 전극용 도전막으로 확산되는 현상을 억제시킴으로써 이들 도전막이 산화되는 것을 방지한다. 또한, 제1 및 제2 산화막은 탄탈륨 산화막의 누설전류 특성을 향상시킨다.2 is a cross-sectional view for explaining a step of forming the second nitride film 13, the second oxide film 15, and the conductive film 17 for the control gate electrode. In detail, the tantalum oxide film 11a having the reduced oxygen pores is formed by annealing a resultant in which the tantalum oxide film 11 is formed in an ultraviolet ozone atmosphere in order to reduce the oxygen pores existing in the tantalum oxide film 11. The ultraviolet ozone annealing step may be omitted as necessary. Subsequently, a second nitride film 13 is formed on the ultraviolet ozone annealed tantalum oxide film 11a in the same manner as the first nitride film 7 formation method. Next, the second oxide film 15 is formed on the surface of the second nitride film 13 by thermally oxidizing the resultant product in which the second nitride film 13 is formed by a dry oxidation process at a temperature of 800 ° C to 900 ° C. Subsequently, a control gate electrode conductive film 17 is formed on the second oxide film 15. The control gate electrode conductive film 17 is preferably formed of a polysilicon film. The first and second nitride films 7 and 13 formed as described above are subjected to these conductivity by suppressing the diffusion of oxygen in the tantalum oxide film 11a into the floating gate conductive film 5 and the control gate electrode conductive film during the subsequent thermal process. Prevents the membrane from oxidizing. In addition, the first and second oxide films improve leakage current characteristics of the tantalum oxide film.

다음에, 도시하지는 않았지만, 상기 콘트롤 게이트 전극용 도전막(17), 제2 산화막(15), 제2 질화막(13), 자외선 오존 어닐링된 탄탈륨 산화막(11a), 제1 산화막(9), 제1 질화막(7), 및 플로팅 게이트용 도전막(5)을 연속적으로 패터닝하여 플로팅 게이트, 제1 질화막 패턴, 제1 산화막 패턴, 탄탈륨 산화막 패턴, 제2 질화막 패턴, 제2 산화막 패턴, 및 콘트롤 게이트 전극을 형성한다. 여기서, 상기 제2 질화막 패턴, 제2 산화막 패턴, 탄탈륨 산화막 패턴, 제1 질화막 패턴, 제1 산화막 패턴은 폴리실리콘층간 유전체막을 구성한다. Next, although not shown, the control film 17 for the control gate electrode, the second oxide film 15, the second nitride film 13, the ultraviolet ozone annealed tantalum oxide film 11a, the first oxide film 9, and the first The first nitride film 7 and the floating gate conductive film 5 are successively patterned to form a floating gate, a first nitride film pattern, a first oxide film pattern, a tantalum oxide film pattern, a second nitride film pattern, a second oxide film pattern, and a control gate. Form an electrode. Here, the second nitride film pattern, the second oxide film pattern, the tantalum oxide film pattern, the first nitride film pattern, and the first oxide film pattern constitute a polysilicon interlayer dielectric film.

본 발명은 상기 실시예에 한정되지 않고 당업자의 수준에서 그 변형 및 개량이 가능하다.The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.

상술한 바와 같이 본 발명의 바람직한 실시예에 의하면, 탄탈륨 산화막의 하부 및 상부에 각각 제 질화막 및 제2 질화막을 형성함으로써, 열처리 공정시 탄탈룸 산화막 내의 산소가 플로팅 게이트 전극용 도전막 및 콘트롤 게이트 전극용 도전막 내로 확산되는 현상을 방지할 수 있다. 이에 따라, 플로팅 게이트 전극용 도전막 또는 콘트롤 게이트 전극이 산화되어 폴리실리콘층간 유전체막의 유효 두께가 증가하여 커플링 비율이 감소하는 문제점을 개선시킬 수 있다. 또한, 탄탈륨 산화막의 하부 및 상부에 각각 제1 산화막 및 제2 산화막을 형성함으로써, 탄탈륨 산화막의 누설전류 특성을 개선시킬 수 있다. 결과적으로, 비휘발성 기억소자의 폴리실리콘층간 유전체막에 의한 커패시턴스를 증가시키어 커플링 비율을 증가시킬 수 있다.According to a preferred embodiment of the present invention as described above, by forming the first nitride film and the second nitride film on the lower and upper portions of the tantalum oxide film, the oxygen in the tantalum oxide film during the heat treatment process for the conductive film and the control gate electrode for the floating gate electrode The phenomenon of spreading into the conductive film can be prevented. As a result, the conductive film or the control gate electrode for the floating gate electrode may be oxidized to increase the effective thickness of the polysilicon interlayer dielectric film, thereby reducing the coupling ratio. In addition, by forming the first oxide film and the second oxide film on the lower and upper portions of the tantalum oxide film, the leakage current characteristics of the tantalum oxide film can be improved. As a result, the capacitance by the polysilicon interlayer dielectric film of the nonvolatile memory device can be increased to increase the coupling ratio.

도 1 및 도 2는 본 발명에 따른 폴리실리콘층간 유전체막 형성방법을 설명하기 위한 단면도들이다.1 and 2 are cross-sectional views illustrating a method for forming a polysilicon interlayer dielectric film according to the present invention.

Claims (8)

플로팅 게이트용 도전막 상에 암모니아 가스를 사용하는 급속열처리 공정을 이용하여 5Å 내지 20Å의 두께의 제1 질화막 및 제1 산화막을 차례로 형성하는 단계;Sequentially forming a first nitride film and a first oxide film having a thickness of 5 GPa to 20 GPa on a floating gate conductive film using a rapid heat treatment process using ammonia gas; 상기 제1 산화막 상에 탄탈륨 산화막을 형성하는 단계; 및Forming a tantalum oxide film on the first oxide film; And 상기 탄탈륨 산화막 상에 암모니아 가스를 사용하는 급속열처리 공정을 이용하여 5Å 내지 20Å의 두께의 제2 질화막 및 제2 산화막을 차례로 형성하는 단계를 포함하는 것을 특징으로 하는 비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법.And forming a second nitride film and a second oxide film, each having a thickness of 5 GPa to 20 GPa, on the tantalum oxide layer by using a rapid heat treatment process using ammonia gas. Film formation method. 제1항에 있어서, 상기 제2 산화막 상에 콘트롤 게이트 전극용 도전막을 형성하는 단계를 더 구비하는 것을 특징으로 하는 비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법.The method of claim 1, further comprising forming a conductive film for a control gate electrode on the second oxide film. 제1항에 있어서, 상기 탄탈륨 산화막을 형성하는 단계 이후에The method of claim 1, wherein after forming the tantalum oxide film 상기 탄탈륨 산화막을 열처리하는 단계를 더 구비하는 것을 특징으로 하는 비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법.And heat-treating the tantalum oxide film. 12. The method of claim 1, further comprising heat treating the tantalum oxide film. 제3항에 있어서, 상기 열처리하는 단계는 자외선-오존 열처리 공정으로 실시하는 것을 특징으로 하는 비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법.4. The method of claim 3, wherein the heat treatment is performed by an ultraviolet-ozone heat treatment process. 제2항에 있어서, 상기 플로팅 게이트용 도전막 및 상기 콘트롤 게이트 전극용 도전막은 폴리실리콘막으로 형성하는 것을 특징으로 하는 비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법.3. The method of claim 2, wherein the floating gate conductive film and the control gate electrode conductive film are formed of a polysilicon film. 제1항에 있어서, 상기 제1 산화막은 산소 가스를 사용하는 급속열처리 공정으로 형성하는 것을 특징으로 하는 비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법.The method of claim 1, wherein the first oxide film is formed by a rapid heat treatment process using oxygen gas. 제1항에 있어서, 상기 탄탈륨 산화막은 100Å 내지 1000Å의 두께로 형성하는 것을 특징으로 하는 비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법.The method of claim 1, wherein the tantalum oxide film is formed to a thickness of 100 kHz to 1000 kHz. 제1항에 있어서, 상기 제2 산화막은 800℃ 내지 900℃의 온도에서 건식산화방식으로 형성하는 것을 특징으로 하는 비휘발성 기억소자의 폴리실리콘층간 유전체막 형성방법.The method of claim 1, wherein the second oxide film is formed by dry oxidation at a temperature of 800 ° C to 900 ° C.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267684A (en) * 1992-03-18 1993-10-15 Rohm Co Ltd Nonvolatile storage element
JPH06275840A (en) * 1993-03-22 1994-09-30 Rohm Co Ltd Nonvolatile storage element
JPH08264667A (en) * 1995-03-24 1996-10-11 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH098152A (en) * 1995-06-20 1997-01-10 Sony Corp Manufacture of semiconductor memory device
KR970018530A (en) * 1995-09-11 1997-04-30 김광호 Capacitor Manufacturing Method of Semiconductor Memory Device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267684A (en) * 1992-03-18 1993-10-15 Rohm Co Ltd Nonvolatile storage element
JPH06275840A (en) * 1993-03-22 1994-09-30 Rohm Co Ltd Nonvolatile storage element
JPH08264667A (en) * 1995-03-24 1996-10-11 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH098152A (en) * 1995-06-20 1997-01-10 Sony Corp Manufacture of semiconductor memory device
KR970018530A (en) * 1995-09-11 1997-04-30 김광호 Capacitor Manufacturing Method of Semiconductor Memory Device

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