JPH06275840A - Nonvolatile storage element - Google Patents

Abstract

PURPOSE:To improve performance of a nonvolatile storage element with a floating gate and a control gate and to make the geometry finer. CONSTITUTION:In a capacitor insulation film 15 which is included between a floating gate 14 and a control gate 16, an oxide film 15a, a nitride film 15b, and a ferroelectric film 15c are successively laminated. Therefore, since the flow of holes from the control gate 16 into the nitride film 15b is prevented, the holes from the control gate 16 do not combine with electrons from the floating gate 14 again in the nitride film 15b. Also, it is not necessary to apply a large heat stress when a ferroelectric film is loaded, thus responding to the request for reducing heat budget.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory element having a floating gate and a control gate, and information is stored in the floating gate by injecting or extracting electric charge, and more particularly to a floating gate. And a control gate, and relates to a structure of a capacitor insulating layer for confining charges in a floating gate for a long time.

[0002]

2. Description of the Related Art Conventionally, a nonvolatile memory element having a floating gate and a control gate has been used in a flash memory, an EPROM (Erasable Programmable Read On Me).
mory), EEPROM (Electrically Erasable Programmable R
ead On Memory) and DRAM (Dynamic Random Access Me)
mory) etc. This nonvolatile memory element is shown in FIG. The nonvolatile memory element shown in FIG. 11 includes a P-type silicon substrate 1, an N-type source region 1b and an N-type drain region 1c formed on the surface layer of the silicon substrate 1 with a predetermined space, and a source region 1b. And a tunnel oxide film 2 formed on the channel region 1a that is sandwiched between the drain region 1c and the drain region 1c, a floating gate 3 formed on the tunnel oxide film 2, and a capacitor insulating film 4 formed on the floating gate 3. And a control gate 5 formed on the capacitor insulating film 4, an interlayer insulating film 6 covering the tunnel oxide film 2, the floating gate 3, the capacitor insulating film 4 and the control gate 5.
It has and.

That is, the floating gate 3 has a tunnel oxide film 2, a capacitor insulating film 4 and an interlayer insulating film 6.
It is surrounded by and is not connected to the outside. Then, the floating gate 3 accumulates the charges that have passed through the tunnel oxide film 2. Therefore, this nonvolatile memory element is called a stack gate type or a floating gate type.

In the above nonvolatile memory element, for example, information is written by applying a positive high electric field between the drain region 1c and the control gate 5. That is, due to the positive high electric field applied between the drain region 1c and the control gate 5, electrons having high energy, so-called hot electrons are generated at the boundary between the drain region 1c and the channel region 1a. This hot electron causes tunnel oxide film 2 to pass through FN (Fowler-Nordheim).
It is tunneled and injected into the floating gate 3.
The electrons injected into the floating gate 3 are
The floating gate 3 is formed by the capacitor insulating film 4.
Be trapped inside for a long time.

In order to improve the performance and miniaturization of the stack gate type non-volatile memory element, the thinning of the capacitor insulating film interposed between the floating gate and the control gate is the most important issue. That is, in the stack gate nonvolatile memory element, the potential of the control gate can be efficiently transmitted to the floating gate by thinning the capacitor insulating film. As a result, high-speed writing and reading of information are achieved, and miniaturization is possible. On the other hand, in order to satisfy the requirement of nonvolatility, it is necessary to confine the charges injected into the floating gate for a long time. Therefore, extremely high quality is required for the capacitor insulating film.

By the way, in the stack gate type nonvolatile memory element shown in FIG. 11, polysilicon is used for the floating gate 3, and this polysilicon is thermally oxidized to grow a SiO ₂ film to grow a capacitor insulating film. 4 are formed. That is, in the capacitor insulating film 4, S
An iO ₂ film is used. When the thinning of the capacitor insulating film 4 which is the SiO ₂ film is pursued, the defects of the film increase. As a result, the electrons accumulated in the floating gate flow into the control gate and recombine with the holes in the control gate. for that reason,
Leakage current occurs and the specifications required by the device cannot be met. That is, the charge retention characteristic is deteriorated and the requirement for nonvolatility is not satisfied.

In order to deal with the above, a stack gate type nonvolatile memory element as shown in FIG. 12 has been proposed.
The capacitor insulating film 4 of this nonvolatile memory element is a so-called ONO (oxi (oxi) which sandwiches films having different conduction mechanisms.
de-nitride-oxide) structure. That is, the capacitor insulating film 4 has a structure in which the bottom oxide film 4a made of SiO ₂ and the top oxide film 4c sandwich the trap nitride film 4b made of Si ₃ N ₄ . The capacitor insulating film 4 is formed on the oxide film 4a obtained by thermally oxidizing polysilicon by CVD (chemical vapor deposition).
n) method, the nitride film 4b is deposited, and the nitride film 4b is further thermally oxidized to grow the oxide film 4c on the nitride film 4b. Therefore, in this nonvolatile memory element,
Even if the electrons in the floating gate 3 tunnel through the bottom oxide film 4a, they are captured by the trap nitride film 4b. Therefore, electrons do not flow out to the control gate 5.

[0008]

In the stack gate type non-volatile memory element shown in FIG. 12, the electron leakage from the floating gate to the control gate is suppressed by the electron trap effect of the nitride film 4b, and the charge retention characteristic is reduced. However, in order to realize a large-capacity nonvolatile memory of 16 Mbits or more, it is necessary to further thin the capacitor insulating film 4.

However, in the above nonvolatile memory element, when the capacitor insulating film is further thinned, the electrons from the floating gate and the holes from the control gate are recombined in the trap nitride film, Leak current is generated. As a result, the stored information is destroyed and incorrect information is read. That is, the charge retention characteristic is deteriorated and the reliability is poor.

FIG. 13 shows the mechanism of deterioration of the charge retention characteristic in the above nonvolatile memory element. 13 is O
FIG. 6 is an energy band diagram of a capacitor insulating film having an NO structure. In the figure, E _FF is the Fermi level of the floating gate, E _FC is the Fermi level of the control gate, B
_BO is a potential barrier of the bottom oxide film, B _TN is potential barrier trapping nitride film, B _TO are respectively the potential barrier of the top oxide film.

Referring to FIG. 13, when a positive electric field is applied to the control gate, an electric field is applied between the control gate and the floating gate, and the Fermi level E _FF of the floating gate and the Fermi level E _{FC of the} control gate are applied. Are shifted in a predetermined direction. As a result, the energy band structure of the capacitor insulating film is deformed. That is, the width W _BO through which electrons of the potential barrier B _BO of the bottom oxide film pass and the width W _TO through which holes of the potential barrier B _TO of the top oxide film pass are narrowed. In the trap nitride film, holes easily flow on the low electric field side. Therefore, the amount of holes injected from the control gate depends on the thickness of the top oxide film.
Therefore, if the thickness of the top oxide film is reduced to, for example, 3 nm or less with the speeding up and miniaturization of the device, holes tunnel into the trap oxide film and flow into the trap nitride film. The holes flowing into the trap nitride film are recombined with the electrons tunneling through the bottom oxide film and flowing into the trap nitride film to generate a leak current.

The bottom oxide film is thin,
It is customary that the ratio of the capacitor insulating film having the ONO structure to the effective film thickness is the largest. Therefore, it is difficult for holes to flow in the bottom oxide film. Therefore, the holes injected into the trap nitride film are accumulated near the interface between the bottom oxide film and the trap nitride film. The holes accumulated near the interface between the bottom oxide film and the trap nitride film consequently enhance the electric field of the bottom oxide film. Then, as shown by the alternate long and short dash line in FIG. 13, the width W _BO through which the electrons of the potential barrier B _BO of the bottom oxide film pass becomes narrower, and the FN tunnel current J _o is increased. As the FN tunnel current J _o increases, the amount of electrons that tunnel through the bottom oxide film and flow into the trap nitride film increases. As a result, the amount of leak current increases.

Further, with the miniaturization of elements, there is a demand for reduction of thermal stress that may be applied to a finished product, that is, so-called thermal padding. However, in the above nonvolatile memory element, when the capacitor insulating film is formed,
2 for growing bottom oxide and top oxide
Two thermal oxidation steps are required. Therefore, it was not possible to meet the demand for reduction of thermal padit, and it was not possible to contribute much to further miniaturization of the device.

That is, the non-volatile memory element is unsuitable for further improvement in performance and miniaturization of the element in terms of both charge retention characteristics and thermal padding. Therefore,
There is a demand for a non-volatile memory element that enables higher performance and miniaturization of the element. In the first place, the reason why the charge retention characteristic is deteriorated is that the relative permittivity of the top oxide film is low, and when the film thickness is made thin, holes flow into the nitride film. Therefore, the applicant of the present invention, if a film having a high dielectric constant that can sufficiently block the inflow of holes into the trap nitride film even if the film thickness is thin is deposited on the nitride film, the electrons and holes are nitrided. We thought that it could prevent recombination in the film. Further, it was found that it is possible to meet the demand for reduction of thermal padit by selecting a film that can be grown without applying heat as a film having a high dielectric constant.

In view of the above, it is an object of the present invention to provide a non-volatile memory element which enables higher performance and miniaturization of the element.

[0016]

Means for Solving the Problems A means for solving the problems according to the present invention is to store information by injecting and extracting charges, and a semiconductor substrate having a predetermined first conductivity type, It is formed at a predetermined interval on the surface layer of the semiconductor substrate and is sandwiched by a source region and a drain region having a second conductivity type opposite to the first conductivity type and the source region and the drain region. A tunnel insulating film formed on the resulting channel region and capable of passing the charges generated in the channel region, a floating gate formed on the tunnel insulating film for accumulating the charges passing through the tunnel insulating film, and a floating gate on the floating gate An oxide film, a nitride film, and an oxide film are provided for confining charges formed and injected into the floating gate for a long time. Dielectric film sequentially laminated capacitor insulating film, and is formed on the capacitor insulating film,
It includes a control gate to which a predetermined voltage is applied.

[0017]

In the above means for solving the problems, since the high dielectric film is used as the uppermost layer of the capacitor insulating film, when a positive electric field is applied to the control gate, most of the voltage is applied to the oxide film having a low relative dielectric constant. , The electric field strength in the high dielectric film becomes very weak. Therefore, the width of the potential barrier of the high dielectric film through which the charges pass does not change much. As a result, the potential barrier of the high-dielectric film prevents the charge from flowing from the control gate into the nitride film. As a result, in the nitride film, charges having different polarities flowing from the control gate and the floating gate do not recombine, and a leak current does not occur. Therefore, the charge retention characteristics are improved.

The high dielectric film is formed by sputtering, C
It can be loaded on the nitride film by the IB, sol-gel method or the like. Therefore, it is not necessary to apply a large thermal stress when the high-dielectric film is stacked, and it is possible to meet the demand for reduction of the thermal budget.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.
Based on. FIG. 1 is a schematic cross-sectional view showing the structure of a nonvolatile memory element according to an embodiment of the present invention. The structure of the nonvolatile memory element according to the present embodiment will be described with reference to FIG.

The nonvolatile memory element of this embodiment is of a stack gate type and is element-isolated by a field oxide film 11 formed relatively thick on the surface layer of a P-type silicon substrate 10. Then, in the element isolation region formed by the field oxide film 11, the N-type source region 12a formed in the surface layer of the silicon substrate 10 at a predetermined interval.
A tunnel oxide film 13 formed on the N-type drain region 12b, the channel region 12a formed so as to be sandwiched between the source region 12a and the drain region 12b, a floating gate 14 formed on the tunnel oxide film 13, and a floating state. The capacitor insulating film 15 formed on the gate 14 and the control gate 16 formed on the capacitor insulating film 15 are provided.

The tunnel oxide film 13 is formed in the channel region 12
The electrons generated in a can be tunneled. The tunnel oxide film 13 is made of SiO ₂ , and its film thickness is set relatively thin so that electrons can be tunneled. The floating gate 14 is for accumulating electrons that have tunneled through the tunnel oxide film 13. The floating gate 14 is made of, for example, polysilicon which is doped with phosphorus at a high concentration to reduce its resistance.

The capacitor insulating film 15 keeps the electrons accumulated in the floating gate 14 for a long time. This capacitor insulating film 15
Is a so-called FNO (ferro) in which an oxide film 15a, a nitride film 15b and a ferroelectric film 15c are sequentially stacked from the floating gate 14 to the control gate 16.
electric-nitride-oxide) structure. Oxide film 1
5a is made of SiO ₂ , and its film thickness is set to about 10 nm. The nitride film 15b is made of Si ₃ N ₄ , and its film thickness is set to about 15 nm. The ferroelectric film 15c is made of a ferroelectric material such as BSN, PZT, and strontium titanate, and its thickness is set to about 50 nm. Since the ferroelectric substance is not used for the purpose of reversing its polarization, it can be selected without considering the orientation.

The control gate 16 is for applying a predetermined control voltage when writing, erasing and reading information. This control gate 16
Is made of, for example, polysilicon in which phosphorus is doped at a high concentration to reduce resistance. Further, the entire surface of the silicon substrate 10 is covered with the interlayer insulating film 17. This interlayer insulating film 1
7 is P-doped SiO ₂ PSG (phospho-silic)
BPSG (boron-phospho-s) with B mixed in ate glass)
ilicate glass) etc. As a result, floating gate 14 is surrounded by tunnel oxide film 13, capacitor insulating film 15 and interlayer insulating film 17 and is not connected to the outside. Further, a gate contact hole 18a is opened in a portion of the interlayer insulating film 17 corresponding to the control gate 16, and the contact hole 18a is formed.
The gate electrode 19a is formed so as to come into contact with the control gate 16. Similarly, source region 1
The source contact hole 18 is formed in the portion corresponding to 2b.
b is opened, and the source electrode 19b is formed so as to contact the source region 12b through the contact hole 18b. Further, a drain contact hole 18c is opened in a portion corresponding to the drain region 12c, and a drain electrode 19c is formed so as to contact the drain region 12c through the contact hole 18c. Therefore, the gate electrode 19a, the source electrode 19b, and the drain electrode 19c are insulated from each other by the interlayer insulating film 17. In addition, each electrode 19
a, 19b and 19c are made of a conductive material such as Al.

Further, the entire surface of the interlayer insulating film 17 is covered with the passivation film 20. The passivation film 20 is for protecting the surface of the nonvolatile memory element and for preventing contaminants from entering from the outside, and is made of PSG, a silicon nitride film deposited by a plasma CVD method, or the like. There is. 2 to 4 are schematic cross-sectional views showing a method of manufacturing a nonvolatile memory element in the order of steps. A method of manufacturing the nonvolatile memory element will be described with reference to FIGS.

First, element isolation is performed. That is, the P-type silicon substrate 10 is thermally oxidized at 900 to 1000 ° C. to form a pad oxide film. Then, a silicon nitride film is formed by the CVD method. Subsequently, a resist pattern is formed on the silicon nitride film. This resist pattern becomes a pattern that defines the transistor formation region to be formed. Then, the silicon nitride film is etched using the resist pattern as a mask. At this point, the resist pattern used as the mask is used up, so the resist is removed by O ₂ plasma treatment. Then, the silicon substrate 10 is oxidized in a water vapor (H ₂ O) atmosphere at about 1000 ° C. for a predetermined time. Then, the SiO ₂ film grows on the surface of the silicon substrate 10 which is not covered with the silicon nitride film. This SiO ₂ film is the field oxide film 11 shown in FIG. Above LOCOS (loacal oxid
After the field oxide film 11 is formed by the cation of silicon) method, the silicon nitride film is used and is ashed.

When the element isolation process is completed, a tunnel oxide film is formed. That is, the silicon substrate 10 is
Thermally oxidize at 0 to 1000 ° C. Then, the SiO ₂ film grows, and as shown in FIG.
A tunnel oxide film 13 is formed on top. When the tunnel oxide film forming step is completed, as shown in FIG.
Form a floating gate. That is, LPCV
Polysilicon is deposited by the D (low pressure chemical vapor deposition) method, and the polysilicon is doped with a conductive material such as phosphorus at a high concentration to form a tunnel oxide film 1.
The floating gate 14 is formed on the upper surface 3.

When the floating gate forming process is completed, a capacitor insulating film is formed as shown in FIGS. That is, as shown in FIG.
By thermal oxidation at about 850 ° C., SiO ₂ is grown on the floating gate 14 to form an oxide film 15a. Subsequently, Si ₃ N ₄ is deposited by the CVD method to form a nitride film 15b on the oxide film 15a. Further, as shown in FIG. 2C, sputtering, CIB
(cluster ion beam), sol-gel method, BSN, P
A ferroelectric such as ZT or strontium titanate is deposited to form a ferroelectric film 15c on the nitride film 15b. At this point, the capacitor insulating film 15 having the FNO structure is completed.

When the capacitor insulating film forming process is completed, a control gate is formed as shown in FIG. That is, polysilicon is deposited by the LPCVD method, and a conductive material such as phosphorus is doped in the polysilicon at a high concentration to form the control gate 16 on the capacitor insulating film 15. When the control gate forming step is completed, a source region and a drain region are formed as shown in FIGS. That is, as shown in FIG. 3B, the control gate 16
The resist 30 is applied onto a predetermined area of the above. After that, the control gate 16, the capacitor insulating film 15, the floating gate 14 and a part of the tunnel oxide film 13 protruding from the resist 30 are removed by isomer etching to expose the surface of the silicon substrate 10. Then, as shown in FIG. 3C, the resist 30 and the remaining control gate 16, the capacitor insulating film 15,
Using the floating gate 14 and the tunnel oxide film 13 as a mask, N-type impurities such as phosphorus are ion-implanted into the silicon substrate 10 by implantation or the like, and the N-type source region 12b and the N-type drain region 12c are removed. Form in a self-aligned manner.

When the source region and drain region forming steps are completed, an interlayer insulating film is formed and metallization is performed, as shown in FIG. That is, C
BPSG is deposited by the VD method, and the interlayer insulating film 17 is formed on the entire surface.
To form. Then, a resist is applied on the entire surface, and a hole is formed in the resist only at the wiring outlet. Next, using the resist as a mask, the interlayer insulating film 17 is subjected to RIE (reacitive).
Ion etching) to remove the control gate 16, the source region 12b, and the drain region 1
2c on the gate contact hole 18a, the source contact hole 18b and the drain contact hole 18
Open c. Subsequently, after removing the resist, Al or the like is deposited by, for example, sputtering, and the gate electrode 19a, the source electrode 19b, and the drain electrode 19c are formed by mask alignment and RIE.

After the formation of the interlayer insulating film and the metallization are completed, a passivation film is formed as shown in FIG. 4 (b). That is, P by the CVD method
A passivation film 20 is formed by depositing SG, a silicon nitride film or the like on the entire surface. By the way, in the step shown in FIG. 3A, when the ferroelectric film 15c is cut by anisotropic etching and the selection ratio between the ferroelectric film 15c and the film thereunder cannot be obtained, After dry etching the control gate 16 once, the ferroelectric film 15c is removed by wet etching containing HCl as a main component,
The ferroelectric film 15c and the film below it may be removed by etching.

Alternatively, as shown in FIGS. 5 and 6,
The first etching is performed when the nitride film is stacked, then the second etching is performed when the ferroelectric film is stacked,
Further, ion implantation may be performed after the third etching is performed at the stage where the control gate is stacked. That is, at the stage where the nitride film 15b is stacked in the same manner as in FIGS. 2A and 2B, as shown in FIG. 5A, the resist 41 is applied to the nitride film 15b to form the nitride film 15b and the oxide film 15a. ,
The protruding portions of the floating gate 14 and the tunnel oxide film 13 are removed by etching to expose the silicon substrate 10. In this state, as shown in FIG. 5B, the ferroelectric film 15c is stacked on the entire surface. Then, as shown in FIG. 5C, a resist 42 is applied on the ferroelectric film 15c, and a protruding portion of the ferroelectric film 15c is removed by etching to expose the silicon substrate 10. Furthermore, FIG.
As shown in (a), the control gate 16 is stacked on the entire surface. Then, as shown in FIG. 6B, a resist 43 is applied on the control gate 16 and the protruding portion of the control gate 16 is removed by etching to expose the silicon substrate 10. Subsequent steps are the same as those in FIGS. 3C and 4A and 4B, and thus description thereof will be omitted.

In the above manufacturing process, since the ferroelectric film 15c is used as the uppermost layer of the capacitor insulating film 15,
The ferroelectric film 15 can be stacked on the nitride film 15b by sputtering, CIB, sol-gel method, or the like. Therefore, when the ferroelectric film 15 is stacked, it is not necessary to apply a large thermal stress, and it is possible to meet the demand for reduction of the thermal budget. Therefore, it contributes to further miniaturization of the device.

FIG. 7 is a diagram showing an information writing operation in the nonvolatile memory element, FIG. 8 is a diagram showing an information erasing operation in the nonvolatile memory element, and FIG. 9 is a diagram showing an information reading operation in the nonvolatile memory element. It is a figure. Information writing, erasing, and reading operations in the nonvolatile memory element will be described with reference to FIGS. 7 to 9. Writing of information is accomplished by setting the source region 12b to the ground potential and applying a positive high electric field between the control gate 16 and the drain region 12c. That is, when a positive high electric field is applied between the control gate 16 and the drain region 12c, a saturated channel current flows between the source region 12b and the drain region 12c. As a result, as shown in FIG. 7, in the pinch off region near the drain region 12c, the electrons accelerated by the high electric field are ionized.
And hot electrons are generated. The hot electrons are injected into the floating gate 14 by FN tunneling through the tunnel oxide film 13. As a result, the information writing state is set. The electrons injected into the floating gate 14 are confined in the floating gate 14 for a long time by the capacitor insulating film 15. Further, since electrons are accumulated in the floating gate 14, near the interface between the control gate 16 and the capacitor insulating film 15,
The holes line up.

Information can be erased by setting the drain region 13c at the ground potential and applying a positive high electric field between the control gate 16 and the source region 12b. That is, the control gate 16 and the source region 12
When a positive high electric field is applied to the point b, as shown in FIG.
The electrons accumulated in the floating gate 14 are extracted into the source region 12b. As a result, the information is erased.

By the way, the gate voltage required for conducting between the source and the drain of the nonvolatile memory element changes depending on whether electrons are accumulated in the floating gate or not. That is, the threshold voltage V _TH for making the source-drain of the nonvolatile memory element conductive is high when the electrons are injected into the floating gate.
Therefore, a low threshold value V2 is set in a state where electrons have not been injected. Thus, by setting the threshold voltage V _TH to two types, binary data of “1” or “0” can be stored in the nonvolatile memory element.

To read information, the source region 12b is set to the ground potential and the drain region 12c is set to the source region 1.
This is achieved by applying a predetermined voltage capable of generating a current between the 2b-drain region 12c and applying a sense voltage, which is an intermediate voltage between the threshold voltages V1 and V2, to the control gate 16. That is, floating gate 1
When electrons are accumulated in the control gate 16, the influence of the holes in the control gate 16 is canceled out by the electrons accumulated in the floating gate 14 as shown in FIG. Does not reach the surface of the silicon substrate 10. Therefore, no channel is formed between the source region 12b and the drain region 12c, and no current flows from the drain region 12c to the source region 12b. On the other hand, when electrons are not accumulated in the floating gate 14, the holes of the control gate 16 affect the surface of the silicon substrate 10 as shown in FIG. 9C. Therefore, a channel is formed between the source region 12b and the drain region 12c, and a current flows from the drain region 12c to the source region 12b. If this state is sensed by a decoder and a sense amplifier (not shown), the information stored in the nonvolatile memory element is read.

In the description of the above operation, information is written by hot electron injection and electrons are discharged to the source side when erasing information. However, for example, a high voltage is applied between the gate and the substrate,
An FN tunnel current is generated between the gate and the substrate to cause electrons to pass through the band to band tunnel.
Injecting into a floating gate by ing), applying a reverse bias between the gate and the substrate at the time of erasing information, and extracting electrons to the substrate side by band-to-band tunneling. In erasing information, ultraviolet rays may be irradiated to dissipate the electrons in the floating gate.

By the way, in the above nonvolatile memory element, since the ferroelectric film is used as the uppermost layer of the capacitor insulating film, even if a positive electric field is applied to the control gate,
Holes are not injected from the control gate into the nitride film of the capacitor insulating film, and holes are not recombined with electrons from the floating gate in the nitride film.

FIG. 10 shows a mechanism in which electrons from the floating gate and holes from the control gate are not recombined in the nitride film of the capacitor insulating film. FIG. 10 is an energy band diagram of a capacitor insulating film having an FNO structure. In the figure, E _FF is the Fermi level of the floating gate, E _FC
Is the Fermi level of the control gate, B _O is the potential barrier of the oxide film, B _N is the potential barrier of the nitride film,
B _F indicates the potential barrier of the ferroelectric film, respectively.

Referring to FIG. 10, when a positive electric field is applied to the control gate, most of the voltage is applied to the oxide film having a low relative dielectric constant. Therefore, only the Fermi level E _FF of the floating gate shifts in the predetermined direction. As a result, the width W _O of the potential barrier B _O of the oxide film through which the electrons pass becomes narrow. Along with this, the electrons in the floating gate tunnel through the oxide film and flow into the nitride film. On the other hand, the electric field strength in the ferroelectric film is very weak. Therefore, the width W _F through which the holes of the potential barrier B _F of the ferroelectric film pass does not change much. as a result,
The potential barrier B _F of the ferroelectric film prevents the holes from flowing into the nitride film. Therefore, holes from the control gate and electrons from the floating gate are not recombined in the nitride film, and a leak current does not occur. That is, the charge retention characteristic is improved.

Further, since the holes injected into the nitride film are sufficiently blocked by the ferroelectric film, the holes injected into the nitride film do not increase the electric field of the oxide film. Therefore, the potential barrier B _O of the oxide film
The width W _O through which the electrons pass does not become narrower, and the FN tunnel current J _o need not be increased more than necessary. Therefore, the electrons are efficiently accumulated in the floating gate. That is, high speed operation of the device becomes possible.

Further, as described above, by using the ferroelectric film, most of the voltage is applied to the oxide film having a low relative dielectric constant, so that the program voltage can be lowered.
From the above, the nonvolatile memory element using the ferroelectric film as the uppermost layer of the above-mentioned capacitor insulating film is suitable for further high performance and miniaturization of the element. The present invention is not limited to the above embodiment, and many modifications and changes can be made within the scope of the present invention.

For example, in the above embodiment, the same effect can be obtained by using a high-dielectric film having a dielectric constant of 50 or more, such as Ta ₂ O ₅ or BSTO, instead of the ferroelectric film. . Further, an N-type silicon substrate may be used instead of the P-type silicon substrate. Further, the capacitor structure of the present invention may be applied to a DRAM capacitor.

[0044]

As is apparent from the above description, according to the present invention, it is possible to meet the demand for improving the charge retention characteristics and reducing the thermal padding. Therefore, there is an excellent effect that it can greatly contribute to higher performance and miniaturization of the element.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing the structure of a nonvolatile memory element according to an example of the present invention.

FIG. 2 is a schematic cross-sectional view showing a method of manufacturing a nonvolatile memory element in the order of steps.

FIG. 3 is a schematic cross-sectional view showing the method of manufacturing the nonvolatile memory element following FIG. 2 in step order.

FIG. 4 is a schematic cross-sectional view showing the method of manufacturing the nonvolatile memory element following FIG. 3 in step order.

FIG. 5 is a schematic cross-sectional view showing another manufacturing method of the nonvolatile memory element in the order of steps.

FIG. 6 is a schematic cross-sectional view showing another manufacturing method of the nonvolatile memory element following FIG. 5, in step order.

FIG. 7 is a diagram showing an information writing operation in a nonvolatile memory element.

FIG. 8 is a diagram showing an information erasing operation in a nonvolatile memory element.

FIG. 9 is a diagram showing an operation of reading information from a nonvolatile storage element.

FIG. 10 is an energy band diagram of a capacitor insulating film having an FNO structure.

FIG. 11 is a schematic cross-sectional view showing the structure of a conventional nonvolatile memory element.

FIG. 12 is a schematic cross-sectional view showing the structure of a conventional nonvolatile memory element having an ONO structure.

FIG. 13 is an energy band diagram of a capacitor insulating film having an ONO structure.

[Explanation of symbols]

 10 Silicon Substrate 12a Channel Region 12b Source Region 12c Drain Region 13 Tunnel Oxide Film 14 Floating Gate 15 Capacitor Insulation Film 15a Oxide Film 15b Nitride Film 15c Ferroelectric Film 16 Control Gate

Claims (1)

[Claims] 1. A semiconductor substrate which stores information by injecting and extracting electric charges and has a predetermined first conductivity type, and a predetermined interval is provided in a surface layer of the semiconductor substrate. Formed on the channel region formed between the source region and the drain region having a second conductivity type opposite to the first conductivity type and the source region and the drain region. A tunnel insulating film that allows the electric charges to pass therethrough; a floating gate that is formed on the tunnel insulating film and accumulates the electric charges that have passed through the tunnel insulating film; and a charge that is formed on the floating gate and that is injected into the floating gate. A capacitor insulating film for temporal confinement, in which an oxide film, a nitride film, and a high dielectric film are sequentially stacked. And it is formed on the capacitor insulating film, the nonvolatile memory element, characterized in that it comprises a control gate to which a predetermined voltage is applied.