KR20100079192A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR20100079192A KR20100079192A KR1020080137608A KR20080137608A KR20100079192A KR 20100079192 A KR20100079192 A KR 20100079192A KR 1020080137608 A KR1020080137608 A KR 1020080137608A KR 20080137608 A KR20080137608 A KR 20080137608A KR 20100079192 A KR20100079192 A KR 20100079192A
- Authority
- KR
- South Korea
- Prior art keywords
- drain
- semiconductor device
- poly gate
- ion implantation
- forming
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000005468 ion implantation Methods 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 17
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 230000004913 activation Effects 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 16
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- -1 spacer nitride Chemical class 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
The present invention relates to a semiconductor device manufacturing method. That is, the present invention provides semiconductor device integration by implanting ions for source / drain formation at a predetermined tilt angle in an ion implantation process for forming a source / drain such that a drain is formed at a predetermined interval away from the poly gate when fabricating a PMOS semiconductor device. It can effectively prevent the GIDL phenomenon.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a source in an ion implantation process for forming a source / drain such that a drain is formed at a predetermined distance from a gate poly when a PMOS semiconductor device is manufactured. The present invention relates to a method of manufacturing a semiconductor device, which can effectively prevent a gate induced drain leakage (GIDL) phenomenon caused by semiconductor device integration by implanting ions for forming a drain at a predetermined tilt angle.
In recent years, with the trend of high-capacity and high-density integration of semiconductor devices, semiconductor devices are increasingly required to be miniaturized. In other words, the higher the technology, the larger the wafer size, while the density of semiconductor devices in the chip increases, so that the effective channel length between source / drain decreases, and the effective channel length decreases as the chip density increases. There was a problem causing various short channel effects such as (tunneling), punch-through (punch-through).
As described above, GIDL, which is one of leakage currents due to the integration of semiconductor devices, is applied between the gate and the drain as a root cause that causes device degradation and causes standby current and off current. Voltage causes gate oxide degradation and leakage of the substrate (to the substrate).
On the other hand, such GIDL occurs a lot in PMOS especially. This is because electrons, which are minority carriers due to depletion, tunnel through the gate oxide layer due to the voltage applied between the poly gate and the drain, or trap in the oxide layer. This is because the deterioration of the oxide film quality (oxide quality). In this case, since the energy of the electrons of the PMOS is larger than that of holes, which are the minority carriers of the NMOS, the liquidity is also increased.
To this end, conventionally, as shown in FIG. 1, the thickness of the
In addition, one method of reducing GIDL is to thickly deposit a
Increasing the spacer thickness, however, reduces the contact area between the source / drain regions and the tungsten (W) metal line to be contacted in subsequent processes, thereby degrading device characteristics.
In addition, the method of increasing the thickness of the poly gate oxide film also causes the same problem as in the case of increasing the thickness of the spacer nitride film, and the problem of reducing the drain current by reducing overlap between the poly gate and the source / drain. There was this.
Accordingly, the present invention provides ion implantation for source / drain formation at a predetermined tilt angle in the ion implantation process for forming a source / drain such that a drain is formed at a predetermined interval away from the poly gate when fabricating a PMOS semiconductor device. An object of the present invention is to provide a method for manufacturing a semiconductor device that can effectively prevent the GIDL phenomenon.
According to the present invention, a method of manufacturing a semiconductor device includes forming a poly gate on a semiconductor substrate on which a device isolation layer is formed, and implanting ions into active regions on both semiconductor substrates of the poly gate. : Forming an LDD), forming an insulating film for forming a spacer on the entire surface of the semiconductor substrate, and removing impurities at a predetermined tilt angle such that drain junctions are shifted by a predetermined length in both activation regions of the poly gate. Implanting ions to form a source / drain; and etching the insulating layer to form spacers on both sidewalls of the poly gate to form a MOS device.
In the present invention, in the PMOS semiconductor device fabrication, by implanting the ions for source / drain formation at a predetermined tilt angle in the ion implantation process for forming the source / drain so that the drain is formed at a predetermined interval away from the poly gate, the GIDL according to the semiconductor device integration There is an advantage that can effectively prevent the phenomenon.
Hereinafter, with reference to the accompanying drawings will be described in detail the operating principle of the present invention. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the present invention, and may be changed according to intention or custom of a user or an operator. Therefore, the definition should be made based on the contents throughout the specification.
In view of the technical gist of the present invention, a technique of implanting ions for source / drain formation at a predetermined tilt angle in an ion implantation process for forming a source / drain such that a drain is formed at a predetermined interval away from the poly gate when manufacturing a PMOS semiconductor device Through it can be easily achieved to achieve in the present invention.
2A to 2F are process flowcharts illustrating a method of manufacturing a semiconductor device for preventing GIDL according to an embodiment of the present invention. Hereinafter, the semiconductor device manufacturing process of the present invention will be described in detail with reference to FIGS. 2A to 2F.
First, as shown in FIG. 2A, an
Subsequently, as shown in FIG. 2B, lightly doped drain (LDD) 208 is formed by ion implanting low concentration impurities into both semiconductor substrates of the
Then, as shown in FIG. 2C, ion implantation for source / drain formation such that drain junctions are shifted by a predetermined length in both activation regions of the
In this case, the ion implantation process may be performed by setting the tilt angle θ of the ion implantation to 7 to 10 ㅀ relative to the
In addition, in the ion implantation process for source / drain formation, ion implantation is performed to the semiconductor substrate using the
FIG. 2D shows that the drain junction is formed farther away from the source junction from the
As a result, the voltage between the poly gate and the drain decreases due to the distance between the poly gate and the drain junction, thereby preventing the GIDL phenomenon.
Subsequently, after forming the source /
As described above, in the method of manufacturing a semiconductor device of the present invention, in the manufacture of a MOS semiconductor device, the distance between the gate and the drain junction is injected into the semiconductor substrate in an ion implantation process for forming a source / drain so that the distance between the gate and the drain junction is formed by a predetermined distance or more. By implanting ions such that ions have a predetermined tilt angle, the voltage between the gate and the drain is lowered, thereby effectively preventing the GIDL phenomenon due to the integration of semiconductor devices.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should not be limited by the described embodiments but should be defined by the appended claims.
1 is an exemplary cross-sectional structure of a conventional MOS semiconductor device;
2A to 2F are cross-sectional views of a MOS semiconductor device forming process capable of preventing a GIDL phenomenon according to an embodiment of the present invention.
<Brief description of the major symbols in the drawings>
200: semiconductor substrate 202: STI
204: gate oxide film 206: poly gate
208: LDD 210: nitride film
210 ': spacer 212: source
214: drain
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080137608A KR20100079192A (en) | 2008-12-30 | 2008-12-30 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080137608A KR20100079192A (en) | 2008-12-30 | 2008-12-30 | Method for fabricating semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20100079192A true KR20100079192A (en) | 2010-07-08 |
Family
ID=42640315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020080137608A KR20100079192A (en) | 2008-12-30 | 2008-12-30 | Method for fabricating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20100079192A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9831240B2 (en) | 2013-07-12 | 2017-11-28 | Samsung Electronics Co., Ltd. | Elevated source drain semiconductor device with L-shaped spacers and fabricating method thereof |
-
2008
- 2008-12-30 KR KR1020080137608A patent/KR20100079192A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9831240B2 (en) | 2013-07-12 | 2017-11-28 | Samsung Electronics Co., Ltd. | Elevated source drain semiconductor device with L-shaped spacers and fabricating method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7192816B2 (en) | Self-aligned body tie for a partially depleted SOI device structure | |
| US9245975B2 (en) | Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length | |
| US9449826B2 (en) | Graded well implantation for asymmetric transistors having reduced gate electrode pitches | |
| JPH10150195A (en) | Mosfet and its manufacture | |
| US7419867B2 (en) | CMOS gate structure comprising predoped semiconductor gate material with improved uniformity of dopant distribution and method of forming the structure | |
| KR100801729B1 (en) | Transistor having a gate to be subsided into substrate and method of fabricating the same | |
| US10418461B2 (en) | Semiconductor structure with barrier layers | |
| US6455388B1 (en) | Method of manufacturing metal-oxide semiconductor transistor | |
| KR20010016838A (en) | Method of forming impurity doped region of MOS transistor | |
| KR20100079192A (en) | Method for fabricating semiconductor device | |
| KR100650900B1 (en) | Method for fabricating semiconductor device | |
| KR100485004B1 (en) | Soi semiconductor device and method for manufacturing the same | |
| KR100597462B1 (en) | Method for fabricating transistor of semiconductor device | |
| KR100269280B1 (en) | Manufacture method of ldd type mos transistor | |
| KR100271801B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR100596829B1 (en) | Method for forming transistor of semiconductor device | |
| KR100772115B1 (en) | Method of manufacturing mosfet device | |
| US20080003788A1 (en) | Method of manufacturing semiconductor device | |
| KR20060074242A (en) | Semiconductor device and method for manufacturing the same | |
| KR100973091B1 (en) | Method for manufacturing of mos transistor | |
| KR19980029591A (en) | Manufacturing Method of Dual Gate SeaMOS Transistor | |
| KR100778862B1 (en) | Semiconductor device and method for manufacturing the same | |
| KR100907900B1 (en) | Semiconductor device manufacturing method | |
| KR20080003954A (en) | Method for fabricating a semiconductor device | |
| KR20030087159A (en) | Semiconductor device and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |