KR20100079145A - Dummy pattern for preventing of dishing of overlay mark - Google Patents

Dummy pattern for preventing of dishing of overlay mark Download PDF

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Publication number
KR20100079145A
KR20100079145A KR1020080137560A KR20080137560A KR20100079145A KR 20100079145 A KR20100079145 A KR 20100079145A KR 1020080137560 A KR1020080137560 A KR 1020080137560A KR 20080137560 A KR20080137560 A KR 20080137560A KR 20100079145 A KR20100079145 A KR 20100079145A
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KR
South Korea
Prior art keywords
pattern
overlay mark
dummy pattern
box
overlay
Prior art date
Application number
KR1020080137560A
Other languages
Korean (ko)
Inventor
전영두
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080137560A priority Critical patent/KR20100079145A/en
Publication of KR20100079145A publication Critical patent/KR20100079145A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67282—Marking devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps

Abstract

PURPOSE: A dummy pattern for the dishing protecting of the overlay mark embodies orthogonally in the unit pattern comprising the box pattern and dummy pattern. The damage of the overlay mark pattern is prevented among the chemical mechanical polishing. CONSTITUTION: A dummy pattern(304) prevents the dishing of the overlay mark in the chemical mechanical polishing. The dummy pattern includes the unit pattern(306) expanded as the linear type to the same direction a plurality of letter. The unit pattern the array shape reiterating with the fixed pitch and is arranged. It is arranged in the up down left right 4 side of the overlay mark. It is expanded as the direction perpendicular to the unit pattern is the box pattern(302) of the overlay mark.

Description

Dummy pattern for preventing of dishing of overlay mark}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dummy pattern around an overlay mark of a semiconductor device and a method of forming the same. Particularly, the present invention relates to an overlay key pattern due to a difference in steps during chemical mechanical polishing (CMP). The present invention relates to a dummy pattern and a method of forming the same, which prevent damage and prevent interference of signals used in overlay measurement.

In general, a semiconductor device forms a specific pattern using a photolithography process on each layer while stacking a plurality of layers on a semiconductor substrate. At this time, the pattern formed on each layer should be exactly aligned with the pattern formed on the upper and lower patterns. In order to confirm whether the alignment of the two upper and lower patterns is accurately performed, an overlay mark formed in the scribe lane area of the semiconductor substrate is used.

1 illustrates a configuration of a general overlay mark. The overlay mark shown in FIG. 1 is a box-shaped overlay mark and is composed of a box pattern such as an outer box 102 formed in the previous step and an inner box 100 formed in the present step. In this case, as shown in FIG. 1, the outer box 102 and the inner box 100 may be in a form in which four sides are separated, or in some cases, all sides may be connected. The distance between the outer box 102 and the inner box 100 of the overlay mark, that is, the overlay value is measured to determine whether the alignment is correct or misaligned by whether the distance falls within a preset reference value range.

The box patterns such as the outer box 102 and the inner box 100 are generally etched in the form of trenches, and then the inside of the trenches are filled with a metal material, etc., followed by removal of the metal material, etc. on the upper part of the trench by chemical mechanical polishing. Form.

In this case, it is common not to form patterns around the overlay mark as described above to avoid interference of a signal input to measure the overlay value. 2 shows an example of how the conventional overlay mark 202 is configured in the scribe lane 200. As can be seen in FIG. 2, the distance between the overlay marks 202 is about 100 μm, and the distance from the left and right boundaries of the scribe lane 200 also reaches about 20 μm. In general, a pattern is not formed around the overlay mark in this space because such surrounding patterns cause interference of signals used for measuring the overlay value.

However, in such a configuration, when the chemical mechanical polishing process is applied to form an overlane mark, a difference in polishing characteristics occurs due to a significant difference in pattern density in a wide portion without a pattern and a portion where an overlay mark is formed. . Due to this difference in polishing characteristics, a step may occur during the polishing process between the wide part without the pattern and the part where the overlay mark is formed, and the dishing effect may be prevented during the overpolishing process to remove such a step. This may cause damage to the overlay marks.

If the overlay mark is damaged in this way, the exact overlay value may not be read correctly, thus providing a serious obstacle to the semiconductor manufacturing process.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dummy pattern and a method of forming the dummy pattern which can exclude the interference of signals during overlay measurement while preventing the overlay mark pattern from being damaged by dishing effect during the chemical mechanical polishing process as described above. will be.

In order to achieve the above object of the present invention, the present invention is a method of forming a dummy pattern on the side of the box-shaped overlay mark, wherein the dummy pattern has a plurality of linear unit patterns having a width smaller than the box width of the overlay mark It is characterized by including.

In this case, the linear unit pattern extends in a direction perpendicular to the box pattern of the overlay mark, and the effect of signal interference in the dummy pattern may be minimized due to the orthogonality of the unit pattern constituting the box pattern and the dummy pattern. In addition, in order to exclude the effect of signal interference in the dummy pattern, the width perpendicular to the linear extension direction of the unit pattern is preferably formed to be 0.25 times or less the width of the box pattern.

The dummy pattern having a plurality of such unit patterns may have an array form having a 1: 1 pitch, and may be disposed on four sides of the top, bottom, left, and right sides of the overlay mark.

According to the present invention, the overlay mark pattern formed on the scribe lane does not cause damage due to dishing due to the surrounding dummy pattern in the chemical mechanical polishing process, and at the same time excludes the effect of signal interference due to the surrounding dummy pattern. The overlay value of the mask can be measured more accurately.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

3 is a plan view of a dummy pattern of overlay marks according to the present invention. The overlay mark is a box-shaped overlay mark consisting of an outer box 300 and an inner box 302.

At this time, the dummy pattern 304 is formed on the top, bottom, left and right four sides of the overlay mark side, and has a plurality of unit patterns 306 extending in a straight line shape. In this case, the dummy pattern has a 1: 1 pitch, has a regular array shape, and may be disposed on four sides of the top, bottom, left, and right sides of the overlay mark.

On the other hand, the dummy pattern may be formed in a portion in which a straight line connecting the center of the overlay mark and the point at which the box pattern is orthogonal to each other extends, that is, not formed at the corner portion of the box pattern in terms of minimizing the interference effect of the signal. desirable. In other words, the dummy pattern formed in this portion may interfere with the signal when measuring the overlay, thereby providing an obstacle to measuring the overlay value more accurately. Therefore, it is preferable to arrange the dummy pattern only on four sides of the top, bottom, left and right sides of the overremy mark.

On the other hand, the dummy pattern is preferably configured in an array form having a plurality of linear unit patterns having a 1: 1 pitch. In this case, the linear unit pattern is preferable in that the extension component of the straight line is extended while being perpendicular to the box pattern of the overlay mark at 90 degrees to minimize the interference effect of the signal input for the measurement of the overlay value.

As an array in which the pitch is formed to be 1: 1, the distance between the unit pattern and the unit pattern, that is, the space can be equal to or different from the width in the direction perpendicular to the linear direction of the unit pattern. The distance between the unit pattern and the unit pattern can be adjusted in various forms according to the conditions of chemical mechanical polishing.

In addition, the width perpendicular to the linear direction of the unit pattern is preferably smaller than the width of the box pattern of the overlay mark. That is, when the unit pattern has a width smaller than the box pattern of the overlay mark, the interference effect of the signal due to the unit pattern can be excluded, and thus, the accurate overlay value can be measured.

At this time, more preferably, the width of the unit pattern is 0.25 times or less than the box pattern of the overlay mark. For example, when the width of the outer box pattern or the inner box pattern of the overlay mark is 1 μm, the unit pattern of the dummy pattern may be 0.25 μm.

4 illustrates a method of forming such a dummy pattern step by step.

First, as shown in FIG. 4A, a photosensitive film 402 is coated on a layer to form an outer box of an overlay mark as a layer formed on the semiconductor substrate 400. This may be, for example, an insulating film layer composed of an oxide film.

Next, as illustrated in FIG. 4B, an exposure step and a development step using a mask are performed. In this case, since the dummy pattern as shown in FIG. 3 is designed on the top, bottom, left, and right sides of the outer box on the scribe lane, the photoresist pattern 402 for the outer box and the dummy pattern is formed through the exposure and development steps. .

Next, as shown in FIG. 4C, an etching process is performed using the photoresist pattern as a mask to form an outer box pattern trench 404 and a trench 406 constituting a dummy pattern.

Next, as shown in FIG. 4D, the inside of the trench 406 may be coated with a material such as metal or polysilicon, and then filled and planarized by chemical mechanical polishing to form the outer box pattern 408 and the dummy pattern 410. At this time, due to the influence of the dummy pattern formed on the side of the outer box pattern 408, it is possible to prevent the phenomenon that the overlay mark itself is damaged by dishing in the chemical mechanical polishing process as in the prior art.

Next, the inner box pattern 412 is formed as shown in FIG. 4E through a photolithography process similar to the method described above using a mask on which the inner box pattern is designed.

In addition, in the chemical mechanical polishing process of forming the inner box pattern 412, the damage of the overlay mark due to dishing may be prevented due to the influence of the dummy pattern.

The above-mentioned embodiments are illustrative rather than limiting on the present invention, and those skilled in the art can design many other embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, it will be apparent that the technology of the present invention can be easily modified by those skilled in the art, such modified embodiments will be included in the technical spirit described in the claims of the present invention.

1 shows a boxed overlay mark.

2 shows the placement of overlay marks within the scribe lanes.

3 illustrates a dummy pattern around an overlay mark according to the present invention.

4 (a) to (e) illustrate a method of forming a dummy pattern according to the present invention.

<Brief description of the major symbols in the drawings>

300: outer box pattern # 302: inner box pattern

304: dummy pattern 306: unit pattern

Claims (4)

In the dummy pattern to prevent dishing of the overlay mark during chemical mechanical polishing, The dummy pattern includes a plurality of unit patterns extending in a straight line in the same direction, and the unit patterns are arranged in four, side, top, bottom, left, and right sides of the overlay mark as the unit pattern is repeatedly arranged with a constant pitch. . The method of claim 1, The unit pattern extends in a direction perpendicular to the box pattern of the overlay mark. The method of claim 1, A dummy pattern having a width perpendicular to the linear direction of the unit pattern is smaller than the width of the box pattern of the overlay mark. The method of claim 3, wherein The dummy pattern having a width perpendicular to the linear direction of the unit pattern is 0.25 times or less than the width of the box pattern of the overlay mark.
KR1020080137560A 2008-12-30 2008-12-30 Dummy pattern for preventing of dishing of overlay mark KR20100079145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080137560A KR20100079145A (en) 2008-12-30 2008-12-30 Dummy pattern for preventing of dishing of overlay mark

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KR1020080137560A KR20100079145A (en) 2008-12-30 2008-12-30 Dummy pattern for preventing of dishing of overlay mark

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104183573A (en) * 2013-05-24 2014-12-03 华邦电子股份有限公司 Lamination alignment mark and manufacturing method thereof
WO2015122932A1 (en) * 2014-02-12 2015-08-20 Kla-Tencor Corporation Metrology targets with filling elements that reduce inaccuracies and maintain contrast
US10002806B2 (en) 2014-02-12 2018-06-19 Kla-Tencor Corporation Metrology targets with filling elements that reduce inaccuracies and maintain contrast
US10825777B2 (en) 2018-05-28 2020-11-03 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor device with an overlay key pattern
CN113703278A (en) * 2021-07-14 2021-11-26 长鑫存储技术有限公司 Mask with overlay mark

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104183573A (en) * 2013-05-24 2014-12-03 华邦电子股份有限公司 Lamination alignment mark and manufacturing method thereof
WO2015122932A1 (en) * 2014-02-12 2015-08-20 Kla-Tencor Corporation Metrology targets with filling elements that reduce inaccuracies and maintain contrast
US10002806B2 (en) 2014-02-12 2018-06-19 Kla-Tencor Corporation Metrology targets with filling elements that reduce inaccuracies and maintain contrast
US10825777B2 (en) 2018-05-28 2020-11-03 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor device with an overlay key pattern
CN113703278A (en) * 2021-07-14 2021-11-26 长鑫存储技术有限公司 Mask with overlay mark

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