JP2014132605A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve both improvement in flatness and easiness of mark recognition.SOLUTION: A first region AR1 is recognized as an alignment mark AM, and a second region AR2 is located around the alignment mark AM. A first data rate that is a ratio of an area of a first layer LAY1 in the first region AR1 to an area of the first region AR1 is more than 0% and less than 100%. In addition, a second data rate that is a ratio of an area of a first layer LAY1 in the second region AR2 to an area of the second region AR2 is less than the first data rate and more than 0%.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a mark and a dummy pattern and a method for manufacturing the semiconductor device.

  One of the processes used in the semiconductor device manufacturing process is CMP (Chemical Mechanical Polishing). One of the characteristics required for CMP processing is flatness. In order to improve the flatness, it is necessary to provide a dummy pattern in an area where it is not necessary to provide a pattern.

  On the other hand, marks for aligning the reticle are formed in the manufacturing process of the semiconductor device. This mark is usually arranged in an area where it is not necessary to provide a pattern. If a dummy pattern is arranged around the mark, it becomes difficult to recognize the mark. For this reason, generally, no mark is arranged around the dummy pattern (for example, Patent Document 1).

  Note that Patent Document 1 and Patent Document 2 describe that a mark is formed by an aggregate of dots.

JP 2000-306822 A JP 2000-10254 A

  In recent years, the required level of flatness after CMP processing has increased. For this reason, it is preferable to provide a dummy pattern also around the mark. However, providing a dummy pattern around the mark makes it difficult to recognize the mark. Thus, it has been difficult to achieve both improvement in flatness and ease of mark recognition. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device has a first region and a second region. Each of the first region and the second region has a first layer and a second layer. The second area is located around the first area. In the first region and the second region, one of the first layer and the second layer is a dummy pattern. The data rates of the first area and the second area are both more than 0% and less than 100%. The data rate of the first area and the data rate of the second area are different from each other.

  According to the one embodiment, both improvement in flatness and ease of recognizing a mark can be achieved.

1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. It is a top view of the board | substrate before being separated into the semiconductor device. It is a figure which shows the modification of FIG. It is an enlarged view of an alignment mark and its circumference. It is AA 'sectional drawing of FIG. FIG. 5 is an enlarged view of FIG. 4. It is a top view which shows the structure of an overlap measurement mark. It is a figure which shows the modification of FIG. It is BB 'sectional drawing of FIG. It is a flowchart explaining the manufacturing method of the semiconductor device using an alignment mark and an overlay measurement mark. It is a figure which shows the reflection intensity of the light of a 1st layer and a 2nd layer when detecting the position of an alignment mark (or overlap measurement mark). (A) is a top view of the transistor which a circuit area | region has, (b) is CC 'sectional drawing of Fig.12 (a). It is a top view which shows the alignment mark which concerns on 2nd Embodiment, and the structure of the circumference | surroundings. It is a top view which shows the alignment mark which concerns on 3rd Embodiment, and the structure of the circumference | surroundings. It is a top view which shows the modification of FIG. It is AA 'sectional drawing of FIG.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a plan view showing the configuration of the semiconductor device SD according to the first embodiment. The semiconductor device SD is a semiconductor chip and has a rectangular shape. The semiconductor device SD has a guard ring GDL. The guard ring GDL is formed without gaps along the four sides of the semiconductor device SD in plan view, and surrounds the circuit region CR included in the semiconductor device SD. The outside of the guard ring GDL is a scribe line SCL. An alignment mark AM and an alignment mark PM are formed on the scribe line SCL. The alignment mark AM is used for aligning the reticle. The alignment mark PM is used to determine whether or not the relative position of the pattern formed on the substrate satisfies the standard. The overlay measurement mark PM is formed on each of the two layers on which the pattern is formed. In many cases, one of these two layers is formed immediately above the other layer.

  The alignment mark AM and the alignment mark PM may be formed in the same layer, or may be formed in different layers. Further, the alignment mark AM may be formed only in one layer, or may be formed in a plurality of layers. Further, there may be a plurality of combinations of two layers on which the overlay measurement mark PM is formed.

  The layer in which the alignment mark AM is formed (or the layer in which the alignment mark PM is formed) is formed using the CMP method. Therefore, a plurality of dummy patterns are formed on the scribe line SCL. The dummy pattern is, for example, a dot pattern. In this embodiment, the dummy pattern is also formed on the alignment mark AM (or the alignment mark PM) itself and its surroundings.

  FIG. 2 is a plan view of the substrate before being separated into semiconductor devices SD. This substrate has a plurality of semiconductor devices SD. The plurality of semiconductor devices SD are arranged in a matrix. A scribe line SCL is provided between two adjacent semiconductor devices SD. As described above, the alignment mark AM, the alignment mark PM, and the dummy pattern are arranged on the scribe line SCL. However, when the substrate is separated into a plurality of semiconductor devices SD, a part of the scribe line SCL is removed. For this reason, in the state shown in FIG. 1, the alignment marks AM and the alignment marks PM remaining on the edge of the semiconductor device SD are only a part in many cases.

  In the example shown in the figure, the alignment mark AM is a stripe pattern. However, the shape of the alignment mark AM is not limited to this. Further, the positions of the alignment mark AM and the overlay measurement mark PM are not limited to the example shown in FIG. For example, as shown in FIG. 3, the alignment mark AM may be provided on both the scribe line SCL extending in the x direction and the scribe line SCL extending in the y direction.

  FIG. 4 is an enlarged view of the alignment mark AM and its surroundings. The semiconductor device SD has a first area AR1 and a second area AR2. The first area AR1 and the second area AR2 are both located on the scribe line SCL. The first area AR1 is an area recognized as the alignment mark AM, and the second area AR2 is an area located around the alignment mark AM. Each of the first region AR1 and the second region AR2 has a first layer LAY1 and a second layer LAY2. The second layer LAY2 is exposed at a part of the surface of the first layer LAY1. In the first area AR1 and the second area AR2, one of the first layer LAY1 and the second layer LAY2 is a dummy pattern. In the example shown in the drawing, the dummy pattern in the first area AR1 is the second layer LAY2. The dummy pattern in the second area AR2 is the first layer LAY1. In the first region AR1, the second layer LAY2 is formed in a dot shape. Here, the dot shape does not require a portion corresponding to each dot to be circular, and may be a polygon such as a rectangle. In the second area AR2, the first layer LAY1 is formed in a dot shape in the second layer LAY2.

  In the first region AR1, the outer shape of the alignment mark AM is defined by the first layer LAY1. In the first region AR1, the second layer LAY2 is a dummy pattern and is formed in a dot shape in the first layer LAY1. The arrangement direction of the second layer LAY2 in the first area AR1 is the same as the arrangement direction of the first layer LAY1 in the second area AR2.

  Then, the first data rate that is the ratio of the area of the first layer LAY1 in the first area AR1 to the area of the first area AR1, and the area of the first layer LAY1 in the second area AR2 with respect to the area of the second area AR2 The second data rate, which is the ratio of the above, is more than 0% and less than 100%, and is different from each other. For example, one of the first data rate and the second data rate is more than 0% and less than 100%, preferably more than 10% and less than 90%. The other of the first data rate and the second data rate is lower than the other and is more than 0% (preferably more than 10%). In particular, one of the first data rate and the second data rate is preferably 60% to 80%, and the other is preferably 20% to 40%. The difference between the first data rate and the second data rate is preferably 20% or more and 60% or less.

  FIG. 5 is a cross-sectional view taken along the line AA ′ of FIG. In the example shown in the drawing, the second layer LAY2 is embedded in the surface of the first layer LAY1. The first layer LAY1 is, for example, a semiconductor substrate (for example, a silicon substrate), and the second layer LAY2 is an element isolation film such as STI, for example. Note that, as shown in the plan view of FIG. 15 and the cross-sectional view of FIG. 16, the plane layout of the first layer LAY1 and the second layer LAY2 may be reversed. The first layer LAY1 may be an interlayer insulating film, and the second layer LAY2 may be a metal pattern (for example, a copper film) having a damascene structure.

  FIG. 6 is an enlarged view of FIG. In the example shown in the drawing, the second layer LAY2 in the first area AR1 and the first layer LAY1 in the second area AR2 are both rectangular and have the same shape. However, these may have different shapes.

In the first region AR1, the width _{w 1} in the x direction of the second layer LAY2 first area AR1 is either equal to the width _{s 1} in the x direction of the first layer LAY1 located between the second layer LAY2 adjacent, Smaller than that. Similarly, the width _{w 2} in the y direction of the second layer LAY2 first area AR1, the same as the width _{s 2} of the y direction of the first layer LAY1 located between the second layer LAY2 adjacent, than small. For example, the width s ₁ is 1 or more times the width w ₁ and the width s ₂ is 1 or more times the width w ₂ .

Further, in the second area AR2, the first layer width _{w 3} in the x direction of the LAY1 of the second area AR2 is the same as x width _{s 3} of the second layer LAY2 located between the first layer LAY1 adjacent Or smaller. Similarly, the first layer width _{w 4} in the y direction LAY1 of the second area AR2 is the same as the second layer y direction width _{s 4} of LAY2 located between the first layer LAY1 adjacent, than small. The widths w ₁ , w ₂ , w ₃ , and w ₄ are all 1 μm or less, preferably 0.5 μm or less.

In the example shown in the figure, the second layer LAY2 in the first area AR1 and the first layer LAY1 in the second area AR2 are both square. Therefore, the second layer width in the x direction of the Lay2 _{w 1} and y-direction width _{w 2,} and the width _{w 3} and the y-direction width w of the x direction of the first layer LAY1 second area AR2 in the first region AR1 ₄ is the same. However, these corners may be rounded and close to a circle.

Further, the arrangement interval _{s 2} of the second layer x-direction arrangement interval _{s 1} and y LAY2 in the first region AR1, the arrangement interval _{s 3} and y directions in the x direction of the first layer LAY1 in the second region AR2 arrangement interval s ₄ are the same both. In particular, in the example shown in the figure, the widths w ₁ , w ₂ , w ₃ , w ₄ and the arrangement intervals s ₁ , s ₂ , s ₃ , s ₄ are all the same. In both the x direction and the y direction, the second layer LAY2 in the first region AR1 and the first layer LAY1 in the second region AR2 are arranged alternately. Further, the first layer LAY1 the first region AR1, spacing _s 5, _{s 6} of the first layer LAY1 the most close to the first area AR1 of the second area AR2 are both equal to _{s 1.} Then, by adjusting the widths w ₁ , w ₂ , w ₃ , w ₄ and the arrangement intervals s ₁ , s ₂ , s ₃ , s ₄ , s ₃ , s ₄ , the first data rate and the second data rate are set. Can be adjusted.

  FIG. 7 is a plan view showing the configuration of the overlay measurement mark PM. In the overlay measurement mark PM, whether or not the deviation amount between one of the first layer LAY1 and the second layer LAY2 and the third layer LAY3 formed on the first layer LAY1 and the second layer LAY2 is within the reference. It is used to determine whether. The configuration of the overlay measurement mark PM is the same as that of the alignment mark AM except for the outer peripheral planar shape. Similar to the alignment mark AM, a plurality of dummy patterns are formed on the overlay measurement mark PM (first area AR1) and its periphery (second area AR2).

  The shape of the overlap measurement mark PM is not limited to the example shown in FIG. For example, as shown in FIG. 8, the overlap measurement mark PM (first area AR1) may be provided along each of four sides of a rectangle (for example, a square). In this case, the third layer LAY3 is also provided along each of four sides of a rectangle (for example, a square). Note that the rectangle drawn by the overlay measurement mark PM and the rectangle drawn by the third layer LAY3 are similar to each other but have different sizes. Similarly, the periphery of the first area AR1 is the second area AR2.

  9 is a cross-sectional view taken along the line BB ′ of FIG. As described above, the second layer LAY2 is embedded in the surface of the first layer LAY1. The third layer LAY3 is formed on the first area AR1. When the first layer LAY1 is a semiconductor substrate and the second layer LAY2 is an element isolation film, the third layer LAY3 is a layer that becomes a gate electrode (for example, a polysilicon layer).

  FIG. 10 is a flowchart illustrating a method for manufacturing the semiconductor device SD using the alignment mark AM and the overlay measurement mark PM. First, a groove for embedding the second layer LAY2 is formed in the first layer LAY1. Next, a second layer LAY2 is formed on the groove and the first layer LAY1. Next, a portion of the second layer LAY2 located on the first layer LAY1 is removed using a CMP method. Thereby, the second layer LAY2 is embedded in the first layer LAY1 (step S10). At this time, an alignment mark AM, an overlay measurement mark PM, and a dummy pattern are formed.

  Next, a third layer LAY3 is formed on the first layer LAY1 and the second layer LAY2. Next, a resist film is formed on the third layer LAY3 (step S20).

  Next, the resist film is exposed using a reticle. At this time, alignment of the reticle is performed using the alignment mark AM. Thereafter, the resist film is developed (step S30).

  Next, using the overlay measurement mark PM and the resist film formed on the third layer LAY3, the positional accuracy (overlay accuracy) of the third layer LAY3 relative to the first layer LAY1 or the second layer LAY2 is determined (step). S40).

  Next, the third layer LAY3 is etched using the resist film as a mask. Thereby, the third layer LAY3 is selectively removed (step S50). At this time, the third layer LAY3 on the overlay measurement mark PM remains. Finally, the resist film is removed (step S60).

FIG. 11 is a diagram illustrating the light reflection intensities of the first layer LAY1 and the second layer LAY2 when the position of the alignment mark AM (or the overlay measurement mark PM) is detected. In the example shown in the figure, the (rectangular) dot pitch (s ₁ , s ₂ , s ₃ , s ₄ ) of the first area AR 1 and the second area AR 2 is 0.4 μm, and the (rectangular) dot size (w ₁ , W ₂ , w ₃ , w ₄ ) is 0.2 μm. As described above, in the first area AR1, the second layer LAY2 is arranged in a (rectangular) dot shape in the first layer LAY1. In the second area AR2, the first layer LAY1 is arranged in a (rectangular) dot shape in the second layer LAY2. The arrangement interval of these (rectangular) dots is equal to or less than the resolution of light used when detecting the position of the alignment mark AM (or the overlay measurement mark PM). For this reason, as shown in this figure, (rectangular) dots are not visible in both the first area AR1 and the second area AR2, and both the first area AR1 and the second area AR2 are recognized as one pattern. The In addition, the wavelength of this light is 0.5 micrometer or more and 1 micrometer or less, for example. Note that the width of the first region AR1 (lateral width in FIG. 11) is, for example, 3 μm or more and 10 μm or less, and the width of the space between the first regions AR1 is equal to or greater than the width of the first region AR1.

  FIG. 12A is a plan view of a transistor included in the circuit region CR. FIG.12 (b) is CC 'sectional drawing of Fig.12 (a). In the example shown in the drawing, the first layer LAY1 is the substrate SUB, and the second layer LAY2 is the element isolation film EI. This transistor has a gate insulating film GI, a gate electrode GT, a sidewall SW, an extension region EX, a source region SOU, and a drain region DR. The gate electrode GT corresponds to the third layer LAY3. An interlayer insulating film IL is formed on the element isolation film EI and the transistor. A contact CON is embedded in the interlayer insulating film IL. A wiring INC is formed on the surface layer of the interlayer insulating film IL. The wiring INC is connected to the source region SOU (or the drain region DR) via the contact CON.

  Next, the operation and effect of this embodiment will be described. According to the present embodiment, the first area AR1 functions as the alignment mark AM (or overlay measurement mark PM). A dummy pattern is formed in the first area AR1 and the second area AR2 located around the first area AR1. For this reason, the flatness of the first layer LAY1 and the second layer LAY2 after the second layer LAY2 is embedded in the first layer LAY1 using the CMP method is improved.

  Further, the first data rate that is the data rate of the first area AR1 is more than 0% and less than 100%, the second data rate that is the data rate of the second area AR2 is lower than the first data rate, and 0 More than%. For this reason, even if 1st area | region AR1 is used as alignment mark AM (or overlap measurement mark PM), alignment mark AM (or overlap measurement mark PM) can be recognized with high precision.

  As described above, according to the present embodiment, both the visibility of the alignment mark AM and the flatness of the first layer LAY1 and the second layer LAY2 can be achieved. This effect is obtained when the first data rate is 60% to 80% and the second data rate is 20% to 40%, or the difference between the first data rate and the second data rate is 20% to 60%. It becomes particularly noticeable when it is less than or equal to%.

  In addition, the size of the (rectangular) dots and the arrangement interval in the first area AR1 and the second area AR2 are less than the resolution of light used when detecting the position of the alignment mark AM (or the overlay measurement mark PM). . For this reason, the alignment mark AM is easily visually recognized. In particular, in the present embodiment, the width of the (rectangular) dots is the same as or narrower than the arrangement interval of the (rectangular) dots. In this way, when detecting the alignment mark AM (or the overlay measurement mark PM), the (rectangular) dots are particularly difficult to recognize, and the alignment mark AM is easily recognized as one mark.

(Second Embodiment)
FIG. 13 is a plan view showing the alignment mark AM according to the second embodiment and the surrounding structure, and corresponds to FIG. 6 in the first embodiment. In the semiconductor device SD according to the present embodiment, a space SPC is provided between the first region AR1 and the first layer LAY1 located in the second region AR2, that is, s ₅ , The configuration is the same as that of the semiconductor device SD according to the first embodiment except that s ₆ is larger than s ₁ to s ₄ . In the example shown in the figure, the space SPC is obtained by removing one column (or one row) of the first layer LAY1 located closest to the first area AR1 among the second areas AR2 shown in the first embodiment. Is formed.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. A space SPC is provided between the first area AR1 and the first layer LAY1 located in the second area AR2. For this reason, the first area AR1 is more easily recognized.

(Third embodiment)
FIG. 14 is a plan view showing the configuration of the alignment mark AM and its surroundings according to the third embodiment, and corresponds to FIG. 6 in the first embodiment. The semiconductor device SD according to the present embodiment is different from the first embodiment or the first embodiment except that the arrangement direction of the first layer LAY1 in the second area AR2 is different from the arrangement direction of the second layer LAY2 in the first area AR1. The configuration is the same as that of the semiconductor device SD according to the second embodiment. In addition, this figure has shown the case similar to 1st Embodiment. An angle θ formed by the arrangement direction of the second layer LAY2 in the first area AR1 and the arrangement direction of the first layer LAY1 in the second area AR2 is, for example, 15 ° or more and 30 ° or less.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. Further, the arrangement direction of the first layer LAY1 in the second area AR2 is different from the arrangement direction of the second layer LAY2 in the first area AR1. For this reason, the first area AR1 is more easily recognized.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

AM alignment mark AR1 first region AR2 second region CON contact CR circuit region DR drain region EI element isolation film EX extension region GDL guard ring GI gate insulating film GT gate electrode IL interlayer insulating film INC wiring LAY1 first layer LAY2 second layer LAY3 Third layer PM Alignment mark SCL Scribe line SD Semiconductor device SOU Source region SPC Space SUB Substrate SW Side wall

Claims (13)

A first region having a first layer and a second layer exposed on a portion of the surface of the first layer;
A second region located around the first region and having the first layer and the second layer;
With
In the first region and the second region, one of the first layer and the second layer is a dummy pattern,
A first data rate that is a ratio of the area of the first layer in the first region to an area of the first region; and a ratio of the area of the first layer in the second region to the area of the second region. The second data rates are both more than 0% and less than 100%, and are different semiconductor devices. The semiconductor device according to claim 1,
In one of the first region and the second region, the second layer is provided in a dot shape in the first layer,
In the other of the first region and the second region, the first layer is a semiconductor device provided in a dot shape in the second layer. The semiconductor device according to claim 2,
The width of the dot-like second layer on the one side is the same as or smaller than the width of the first layer located between the adjacent second layers,
The width of the dot-like first layer on the other side is the same as or smaller than the width of the second layer located between the adjacent first layers. The semiconductor device according to claim 2,
The width of the dot-shaped second layer on the one side is 3 μm or less, and the width of the dot-shaped first layer on the other side is 3 μm or less. The semiconductor device according to claim 2,
A semiconductor device in which the arrangement direction of the dot-shaped second layer on the one side is different from the arrangement direction of the dot-shaped first layer on the other side. The semiconductor device according to claim 5,
The difference between the arrangement direction of the dot-like second layer on the one side and the arrangement direction of the dot-like first layer on the other side is 15 ° or more and 30 ° or less. The semiconductor device according to claim 1,
One of the first data rate and the second data rate is 60% or more and 80% or less,
The other of the first data rate and the second data rate is 20% to 40%. The semiconductor device according to claim 1,
The difference between the first data rate and the second data rate is 20% or more and 60% or less. The semiconductor device according to claim 1,
The first region and the second region are semiconductor devices located on a scribe line. The semiconductor device according to claim 1,
One of the first layer and the second layer is a semiconductor substrate, and the other of the first layer and the second layer is an element isolation film. A first region having a first layer and a second layer exposed on a portion of the surface of the first layer;
A second region located around the first region and having the first layer and the second layer;
With
In the first region and the second region, one of the first layer and the second layer is a dummy pattern,
The first data rate, which is the ratio of the area of the first layer in the first region to the area of the first region, is more than 0% and less than 100%;
Preparing a semiconductor substrate in which a second data rate, which is a ratio of the area of the first layer in the second region to the area of the second region, is lower than the first data rate and greater than 0% When,
Performing alignment and processing with respect to the first region;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 11,
In one of the first region and the second region, the second layer is provided in a dot shape in the first layer,
In the other of the first region and the second region, the first layer is a method for manufacturing a semiconductor device in which dots are formed in the second layer. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the width and arrangement interval of the dot-like second layer on the one side and the width and arrangement interval of the dot-like first layer on the other side are the first region. The manufacturing method of the semiconductor device which is below the resolution of the light used in the process of aligning with reference to

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