KR101095081B1 - Overlay vernier and measuring overlay using the same - Google Patents

Abstract

The present invention relates to an overlay vernier of a semiconductor device and an overlay measurement method using the same. By forming an overlay vernier having a polygon shape and measuring the overlay value of a pattern formed in a diagonal direction as well as up and down, left and right directions, reliability and accuracy in overlay measurement. Disclosed a technique that can improve the.

Description

Overlay vernier and overlay measurement method using the same {OVERLAY VERNIER AND MEASURING OVERLAY USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of highly integrated semiconductor devices, and in particular, to reduce the alignment error of patterns by using overlay verniers in the manufacture of semiconductor memory devices in which a plurality of patterns are overlapped.

The semiconductor memory device includes various components including a plurality of unit cells for storing data, an input / output circuit for inputting and outputting data into the unit cells, and the like. In general, in the manufacturing process of a cell array including a plurality of unit cells in a semiconductor memory device, a gate is formed on a semiconductor substrate, a bit line is formed on the upper layer, a capacitor is formed on the upper layer of the bit line, and a capacitor is formed. The upper layer is formed in the order of forming the metal wiring.

In order to increase the degree of integration, the components included in the semiconductor memory device are not only arranged in a plane but also formed in a vertical stack structure. As described above, the components of the gate, the bit line, the capacitor, and the like are formed in different layers stacked vertically, and as a result, more components in the semiconductor memory device are stacked vertically to increase the degree of integration. In order to vertically arrange a plurality of components without errors, it is very important to eliminate alignment errors from the bottommost semiconductor substrate to the topmost layer, in which an overlay vernier is formed. The overlay vernier is generally formed in an extra space in which no components of the semiconductor device are formed on the wafer, and are mainly formed in the scribe lane region of the semiconductor substrate.

The overlay vernier includes a rectangular parent vernier formed in the lower layer and a rectangular vernier provided in the upper layer. The overlay vernier measures the positional information on which the mother vernier and the vernier overlap or are arranged during the manufacturing process of the semiconductor device. It is indirectly measured that the components included in the and top layer are aligned without error.

1 is a plan view illustrating an overlay vernier according to the prior art.

Referring to FIG. 1, as a general overlay vernier, there is a parent vernier 100 having a rectangular frame shape and a vernier 110 having a rectangular shape inside the parent vernier 100. In some cases, as indicated by the dotted line, the parent vernier 100 may be formed such that four bar patterns are arranged in a rectangular shape rather than a rectangular frame shape. Hereinafter, an overlay measuring method using the overlay vernier shown in FIG. 1 during the manufacturing process of a semiconductor device will be described.

First, an overlay scan is performed on a substrate equipped with the overlay vernier of FIG. 1 in a measurement device. Overlay values of the parent vernier 100 formed in the previous layer and the child vernier 110 formed in the current layer through the overlay measurement signal (Signal) obtained by the overlay scan is measured from the top, bottom, left and right. Comparing the measurement results, it is possible to measure the degree to which the parent vernier 100 and the child vernier 110 are out of the center, it is possible to control the degree of alignment of the upper layer with respect to the lower layer by reflecting this as an overlay misalignment value.

By comparing the top, bottom, left and right, respectively, using the parent vernier 100 and the child vernier 110 of the conventional overlay vernier can measure the overlay value in the X, Y direction shown in FIG. However, recently, as a method of increasing the degree of integration in order to increase the number of net dies of the device, the cell structure of the semiconductor memory device is modified to manufacture components through a diagonal pattern that has not existed before.

For example, as the size of the unit cell included in the semiconductor memory device changes from 8F2 to 6F2, the shape of the active region may be aligned in a diagonal direction, and used to support the lower electrode in the process of forming a capacitor having a high aspect ratio. The nitride film patterns to be aligned are also aligned in an oblique direction. As such, as the density of semiconductor memory devices increases, the spacing between components decreases unless they interfere with the operation of each component. As a result, each component is arranged not only on the X and Y axes but on the upper and lower sides. It may be arranged at an angle of 45 degrees to the left and right.

Since the process margin is reduced by increasing the density, reducing the alignment error of the diagonal patterns is more important in the highly integrated semiconductor memory device. However, if the overlay vernier of the rectangular shape is used to measure the overlay, only overlay values between the top and bottom and left and right sides can be measured, and overlay values in the diagonal direction are difficult to accurately measure, and overlay values between the top and bottom and left and right sides are used. Should be calculated as an approximation. Therefore, even when the overlay measurement, there is a problem that the reliability and accuracy is lowered.

The present invention provides an overlay vernier for eliminating alignment errors in the process of forming a capacitor having a high aspect ratio by using a nitride film pattern included in a highly integrated semiconductor memory device as a support film, thereby preventing defects in manufacturing and operating reliability of the semiconductor memory device. Is to improve.

The overlay vernier according to the present invention includes a polygonal shape vernier and a polygonal shape vernier provided inside the parent vernier.

Preferably, the polygon is characterized in that the octagon.

Preferably, the line width of the cross section of the parent vernier is characterized in that 7 ~ 8㎛.

Preferably, the line width of the cross section of the vernier is characterized in that 5 ~ 5.5㎛.

Preferably, the parent vernier is characterized in that it is formed in a frame (frame) form.

Preferably, the parent vernier is formed in the shape of a bar, the plurality of bar-shaped pattern is formed, characterized in that arranged in a polygonal shape.

Preferably, the distance between both edge portions of the parent vernier is characterized in that 40 ~ 50㎛.

Preferably, the parent vernier and the vernier vernier is characterized in that formed in the polygonal donut or ring shape.

Preferably, the parent vernier is characterized in that composed of a plurality of fine patterns.

Preferably, the plurality of fine patterns are characterized in that arranged at intervals of 1 ~ 5μm.

Preferably, the fine patterns located at the outermost or innermost edge of the shape in the parent vernier is connected to each other.

Preferably, the degree of overlap is measured by overlapping the outermost edges of the movernier and the zavernier.

In addition, the present invention comprises the steps of forming a lower electrode of the capacitor corresponding to the parent vernier of the polygonal form; Overlapping the child vernier of the polygonal shape of the parent vernier to measure the degree of overlap and then removing the alignment error; And forming a support film corresponding to the magnetic vernier between the lower electrodes of the capacitor.

Furthermore, the present invention comprises the steps of forming a polygonal shape of the vernier pattern on the substrate; Forming a polygonal shaped vernier pattern; And measuring an overlay value between the parent vernier pattern and the child vernier pattern.

Preferably, the overlay value is measured in up, down, left, and right directions.

Preferably, the overlay value is measured by matching the center of the mother vernier pattern with the mother vernier pattern.

Preferably, the overlay value is measured by matching the outermost etch of the parent vernier pattern and the child vernier pattern.

The overlay vernier according to an embodiment of the present invention may measure overlay values of patterns formed in an oblique direction as well as overlay values in up and down directions and left and right directions. In particular, the reliability and accuracy of overlay measurement at the time of formation of the capacitor included in the highly integrated semiconductor memory device can be improved, thereby reducing the defects in manufacturing the capacitor. As a result, it is possible to increase the production yield of the highly integrated semiconductor memory device and to lower the production cost.

The present invention manufactures a highly integrated semiconductor device by using an overlay vernier to reduce alignment errors, and will be described with reference to an embodiment in which the overlay vernier is applied to a process of forming a capacitor in which manufacturing defects are frequently caused by alignment errors. In addition to the process of forming a capacitor, the overlay vernier according to an embodiment of the present invention includes patterns in which two different components are aligned in a diagonal direction as well as an overlap between patterns aligned in X, Y axes of up, down, left, and right. It can be applied to the process of forming a semiconductor device. Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A and 2B are plan views illustrating overlay verniers according to an embodiment of the present invention.

Referring to FIG. 2A, there is illustrated an overlay vernier having a mother vernier 200 having a polygonal frame shape and a child vernier 210 having a polygonal shape formed inside the mother vernier 200.

Here, the polygon is preferably octagonal. The line width D1 of one cross section of the parent vernier 200 is preferably 7 to 8 μm, and the line width D2 of one cross section of the child vernier 210 is preferably 5 μm to 5.5 μm. Moreover, it is preferable that the distance D3 between the cross sections formed in parallel with each other among the parent verniers 200 is 40-50 micrometers.

Referring to FIG. 2B, a parent vernier 220 having a plurality of bar-shaped patterns arranged in a polygonal shape is provided, and an overlay vernier having a polygonal ruler vernier 230 is provided inside the parent vernier 220. It is shown.

Here, the polygon is preferably octagonal. The line width D1 of one cross section of the parent vernier 220 is preferably formed to 7 to 8 μm, and the line width D2 of one cross section of the child vernier 230 is preferably 5 to 5.5 μm. Do. In addition, it is preferable that the distance D3 between the cross sections formed in parallel among the parent verniers 220 is 40-50 micrometers.

Although not shown, the overlay vernier forming process of FIGS. 2A and 2B will be described.

First, an etched layer (not shown) and a hard mask layer (not shown) are formed on a semiconductor substrate (not shown).

Next, a first photoresist pattern (not shown) is formed on the hard mask layer (not shown). Here, the first photoresist pattern (not shown) defines a parent vernier having a polygonal frame shape (FIG. 2A '200'). Also, a bar vernier (FIG. 2B '230') may be defined in which a bar pattern is arranged in a polygonal shape.

Next, the hard mask layer (not shown) is etched using the first photoresist pattern (not shown) as a mask to form a hard mask pattern (not shown). Then, the first photosensitive film pattern (not shown) is removed.

Next, an etched layer (not shown) is etched using a hard mask pattern (not shown) as a mask to form a parent vernier having a step difference.

Next, a planarized intermediate layer (not shown) is formed over the entire etched layer (not shown) including the parent vernier. Then, a second photoresist film (not shown) is formed on the intermediate layer (not shown).

Next, the second photoresist film (not shown) is patterned to form a ruler vernier ('210' in FIG. 2A and '220' in FIG. 2B). At this time, the ruler vernier is formed in a polygonal shape, it is preferable to be formed inside the parent vernier.

And, it is preferable to form each cross section of the child vernier (210, 230) to correspond to the respective cross-section of the parent vernier (200, 220). That is, cross sections of the parent vernier 200 and 220 and the child vernier 210 and 230 are formed to be parallel to each other.

3 illustrates an overlay measurement method using the overlay vernier of FIG. 2A.

An overlay measurement method will be described with reference to FIG. 3.

First, a mother vernier 200 and a child vernier 210 having a polygonal shape are formed on a substrate (not shown).

Then, an overlay scan is performed in the measurement equipment. The overlay value between the parent vernier 200 formed in the previous layer and the child vernier 210 formed in the current layer is measured through the overlay measurement signal (Signal) obtained by the overlay scan. Here, the overlay value can be measured in the overlay of the X-axis and Y-axis direction as in the conventional overlay vernier. In addition, as indicated by the arrow, overlay measurement in the A direction or the B direction is possible. Therefore, it is possible to measure not only the overlay value of the pattern having the long axis in the vertical, left and right directions, but also the overlay value of the pattern having the long axis in the diagonal direction. That is, as shown in FIG. 3, overlay values in the 'A' direction (45 degrees with respect to the X axis) and the 'B' direction (135 degrees with respect to the X axis) may also be measured.

Conventionally, when the overlay is measured for the diagonal pattern, the overlay is measured by guessing an approximate value for the diagonal direction after measuring the overlay of the X and Y axes. However, when the overlay vernier according to an embodiment of the present invention is applied to a manufacturing process, the overlay value in the diagonal direction may be measured in addition to the X-axis or Y-axis direction. Therefore, the measurement reliability is improved with respect to the diagonal pattern, and even when the direction of the pattern is not 45 degrees, an overlay value that is close to that of the existing overlay vernier can be obtained.

4A to 4C are plan views illustrating overlay verniers according to another exemplary embodiment of the present invention. Specifically, FIG. 4A shows the parent vernier 400 corresponding to the lower layer, and FIG. 4B shows the child vernier 410 corresponding to the upper layer. 4C illustrates the shape when the parent vernier 400 and the child vernier 410 are superimposed.

Referring to FIG. 4A, the parent vernier 400 is formed in a donut or ring shape having a polygonal shape similar to the parent vernier 200 illustrated in FIG. 2A, but has a wide width of the pattern. For example, the pattern width of the parent vernier 400 may have a size of several tens of μm.

In addition, the parent vernier 400 includes a plurality of fine patterns rather than the entire pattern of the octagon in one pattern. In this case, the plurality of fine patterns have the same shape as the lower electrode of the pillar-shaped capacitor formed in the cell region. That is, when the lower electrode is formed in the cell region, the parent vernier 400 may be formed by forming a pattern having the same pattern in the scribe lane region where the overlay vernier is formed.

Furthermore, when the parent vernier 400 is composed of a plurality of fine patterns, a disadvantage may occur such that the fine patterns are inclined, so that the outermost regions and the innermost regions of the polygonal vernier 400 are overcome in order to overcome such a point. The fine patterns located in the region may be connected to each other to form a line-shaped pattern 402 so as not to fall or tilt.

Referring to FIG. 4B, the child vernier 410 corresponding to the upper layer is formed in a polygonal shape similar to the parent vernier 400, and is formed in one pattern instead of a plurality of fine patterns, and the width of the pattern is the mother vernier 410. It is characterized by being formed narrower than the width of the vernier 400. In the exemplary embodiment of the present invention described with reference to FIG. 3, the pattern overlaps with a method of measuring the distance between the child vernier 210 and the mother vernier 200 after matching the centers of the child vernier 210 and the mother vernier 200. Although the degree of alignment and the degree of alignment have been confirmed, in another embodiment of the present invention, there is a difference in confirming the puffiness and the degree of alignment of the pattern by matching the outermost edges of the vernier 410 and the parent vernier 400 instead of the center.

Referring to FIG. 4C, the child vernier 410 is superimposed on the parent vernier 400. When the outermost edge of the child vernier 410 is matched with the outermost edge of the parent vernier 400, the pattern width of the child vernier 410 is smaller than the pattern width of the parent vernier 400, so that it is included in the parent vernier 400. Some of the multiple micro patterns that have been exposed are exposed.

At this time, the size and spacing of the plurality of fine patterns included in the exposed parent vernier 400 is preset according to the design rule and the size of the capacitor formed in the cell area, the parent vernier 400 and the child vernier 410 Knowing the number of fine patterns exposed without the need to measure the distance between them makes it easy to see the measurement. In addition, in another embodiment of the present invention, if a plurality of fine patterns included in the parent vernier 400 are designed and formed at intervals of about 1 to 5 μm apart from the capacitor of the cell region, each fine pattern may serve as a ruler. have.

If the parent vernier 400 of the overlay vernier according to another embodiment of the present invention described above corresponds to the lower electrode of the capacitor formed in the cell region, the child vernier 410 is a nitride film pattern formed to support the lower electrode of the capacitor (I.e., a support film for a nitride floating capacitor (NFC)).

FIG. 5 is a plan view illustrating an overlay measuring method using the overlay vernier illustrated in FIGS. 4A to 4C.

As illustrated, after overlapping the parent vernier 400 and the child vernier 410, different regions are identified according to which direction the patterns formed inside the semiconductor device should be aligned in correspondence with the lower layer and the upper layer. This makes it easy to measure the alignment error. In other words, when two different patterns are aligned on the X axis, the alignment error can be easily identified by checking the 'A' area. When two different patterns are aligned on the Y axis, the 'B' area is different. If the two patterns are aligned in the diagonal of 45 degrees, the overlap and alignment can be easily calculated through the 'C' region.

FIG. 6 is a plan view illustrating a capacitor formed in a cell region using the overlay vernier illustrated in FIGS. 4A to 4C.

As illustrated, a plurality of cylindrical capacitor lower electrodes 600 are formed in the cell region, and the lower electrode 600 is a support layer for preventing the lower electrode 600 of the capacitor from falling down or tilting in a subsequent process. The nitride film pattern 610 is formed therebetween. At this time, since the lower electrode 600 and the nitride film pattern 610 are not aligned with each other in the X-axis or Y-axis direction, it is difficult to accurately measure the overlap and the alignment degree with a conventional overlay vernier, but in the present invention, the 45-degree diagonal More precise measurement can be achieved through the 'C' region (see FIG. 5), which can measure the degree of overlap and alignment when aligned in the direction.

As described above, a method of manufacturing a semiconductor device using an overlay vernier according to an embodiment of the present invention forms a lower electrode of a capacitor corresponding to a parent vernier having a polygonal shape, and forms a polygonal vernier of the parent vernier. You can measure the degree of overlap to eliminate the alignment error. Thereafter, a supporting film corresponding to the child vernier may be formed to prevent the lower electrode of the capacitor from falling or tilting in a subsequent process.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1 is a plan view of an overlay vernier according to the prior art.

2A and 2B are plan views illustrating overlay verniers in accordance with one embodiment of the present invention.

3 is a plan view illustrating an overlay measurement method using the overlay vernier shown in FIGS. 2A and 2B.

4A to 4C are plan views illustrating overlay verniers according to another embodiment of the present invention.

FIG. 5 is a plan view illustrating an overlay measuring method using the overlay vernier shown in FIGS. 4A to 4C.

FIG. 6 is a plan view illustrating a capacitor formed in a cell region using the overlay vernier shown in FIGS. 4A to 4C.

Claims (18)

A mother vernier having a polygonal shape including a plurality of fine patterns having the same shape as the capacitor lower electrode; And A polygonal shape vernier provided inside the mother vernier and including a pattern identical to a nitride film pattern for supporting the capacitor lower electrode. Overlay vernier comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Overlay vernier, characterized in that the polygon is octagon. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, Overlay vernier, characterized in that the line width of the cross section of the parent vernier is 7 ~ 8㎛. Claim 4 was abandoned when the registration fee was paid. The method of claim 1, Overlay vernier, characterized in that the line width of the cross section of the vernier is 5 ~ 5.5㎛. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, The parent vernier is overlay vernier, characterized in that formed in the form of a frame (frame). Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The parent vernier is an overlay vernier, characterized in that formed in the shape of a bar. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, The plurality of bar-shaped patterns are formed, overlay vernier, characterized in that arranged in a polygonal form. Claim 8 was abandoned when the registration fee was paid. The method of claim 1, Overlay vernier, characterized in that the distance between the edge portion of the parent vernier is 40 ~ 50㎛. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, The parent vernier and the vernier vernier is an overlay vernier, characterized in that formed in the polygonal donut or ring shape. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, The width of the vernier vernier overlay vernier, characterized in that narrower than the width of the parent vernier. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 1, The plurality of fine patterns are overlay vernier, characterized in that arranged at intervals of 1 ~ 5μm. Claim 12 was abandoned upon payment of a registration fee. The method of claim 1, And the fine patterns positioned at the outermost or innermost edges of the shape in the parent vernier are connected to each other. Claim 13 was abandoned upon payment of a registration fee. The method of claim 1, Overlay vernier, characterized in that for overlapping the outermost edge of the vernier and the vernier. Forming a mother vernier having a polygonal shape including a lower electrode of the capacitor and the same fine pattern as the lower electrode of the capacitor; Removing an alignment error after measuring a degree of overlap by overlapping a child vernier having a polygonal shape on the outermost edge of the parent vernier; And Forming a support film corresponding to the magnetic vernier between the lower electrodes of the capacitor. Claim 15 was abandoned upon payment of a registration fee. The method of claim 14, The magnetic vernier is a semiconductor device manufacturing method, characterized in that formed corresponding to the nitride film pattern for supporting the parent vernier. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 14, In measuring the overlay values of the parent vernier and the child vernier, the overlay value is measured in up, down, left, and right directions. Claim 17 has been abandoned due to the setting registration fee. The method of claim 14, The method of manufacturing a semiconductor device, characterized in that the overlay value is measured by matching the center of the parent vernier pattern and the child vernier pattern. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 14, Measuring the degree of overlap, And measuring the degree of overlap based on the number of fine patterns of the parent vernier exposed after the child vernier is overlapped.

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