KR20110001192A - Overlay vernier and method for measuring overlay using the same - Google Patents

Overlay vernier and method for measuring overlay using the same Download PDF

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Publication number
KR20110001192A
KR20110001192A KR1020090058601A KR20090058601A KR20110001192A KR 20110001192 A KR20110001192 A KR 20110001192A KR 1020090058601 A KR1020090058601 A KR 1020090058601A KR 20090058601 A KR20090058601 A KR 20090058601A KR 20110001192 A KR20110001192 A KR 20110001192A
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KR
South Korea
Prior art keywords
vernier
overlay
parent
pattern
ruler
Prior art date
Application number
KR1020090058601A
Other languages
Korean (ko)
Inventor
배재준
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090058601A priority Critical patent/KR20110001192A/en
Publication of KR20110001192A publication Critical patent/KR20110001192A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: An overlay vernier and a method for measuring an overlay using the same are provided to improve the yield of a semiconductor device by measuring an overlay value due to the amount of light reflected at each divided region. CONSTITUTION: An overlay vernier includes a polygonal main vernier(310) and a sub vernier(320). The sub vernier divides the main vernier into a plurality of regions. A polygonal main vernier is formed on the upper side of the substrate. The sub vernier pattern is formed on the main vernier pattern. Light is inputted to the divided main vernier pattern and an overlay value is measured by detecting the amount of light reflected according to each region.

Description

Overlay vernier and overlay measurement method using the same {OVERLAY VERNIER AND METHOD FOR MEASURING OVERLAY USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a highly integrated semiconductor device, and more particularly, to an overlay vernier for measuring alignment in a semiconductor lithography process and an overlay measuring method using the same.

The semiconductor memory device includes various components including a plurality of unit cells for storing data and an input / output circuit for inputting and outputting data to and from the unit cells. In general, in the manufacturing process of a cell array including a plurality of unit cells in a semiconductor memory device, a gate is formed on a semiconductor substrate, a bit line is formed on an upper layer, a capacitor is formed on an upper layer of a bit line, and a capacitor is formed. The upper layer is formed in the order of forming the metal wiring.

In order to increase the degree of integration, the components included in the semiconductor memory device are not only arranged in a plane but also in a vertical stack structure. As described above, the components of the gate, the bit line, the capacitor, and the like are formed in different layers stacked vertically, and as a result, more components in the semiconductor memory device are stacked vertically to increase the degree of integration. In order to vertically arrange a plurality of components without errors, it is very important to eliminate alignment errors from the bottom semiconductor substrate to the topmost layer, which forms an overlay vernier. The overlay vernier is generally formed in an extra space in which no component of the semiconductor device is formed on the wafer, and is mainly formed in the scribe lane area of the semiconductor substrate.

1 is a plan view showing an overlay vernier according to the prior art, Figure 2 is a view showing a case where the overlay vernier according to the prior art is damaged.

Referring to FIG. 1, as a general overlay vernier, there are a parent vernier 110 formed in a rectangular frame shape and a child vernier 120 arranged in a bar shape inside a mother vernier 110.

An overlay scan is performed in the measurement equipment with respect to the substrate provided with the overlay vernier having the above structure. Overlay values, such as the degree of overlap, spacing, etc. between the parent vernier 110 formed in the previous layer and the child vernier 120 formed in the current layer are measured through the overlay measurement signal (signal) obtained by the overlay scan. Comparing the measurement results, it is possible to measure the degree to which the parent vernier 110 and the child vernier 120 deviate from the center, and reflects this as an overlay misalignment value to control the degree of alignment of the upper layer with respect to the lower layer.

However, as shown in FIG. 2, when the parent vernier 110 is attacked due to a chemical mechanical polishing (CMP) process or the like, an attack occurs on the cross section of the parent vernier 110 during the etching process, and thus the parent vernier 110 is damaged. This can lead to errors in measuring the center, which can cause problems with the reliability of the overlay measurement for that layer. That is, the method of measuring the degree of alignment using the overlay vernier shown in FIG. 1 has no problem when the overlay vernier is normally formed. However, when the overlay vernier is damaged by an attack that may occur in the process as shown in FIG. The misalignment of the centers increases the error in the alignment measurement.

The present invention has been proposed to solve the above problems of the prior art, and provides an overlay vernier and an overlay measuring method using the same that can stably measure the degree of alignment even when an attack occurs in the process.

In particular, the overlay vernier of the present invention provides a polygonal vernier and a vernier that can divide the parent vernier into a plurality of areas, by using this to irradiate light to the divided areas of the parent vernier and to The present invention provides an overlay measurement method of controlling the degree of alignment by detecting an amount of reflected light and measuring an overlay value.

In order to achieve the above object, according to an aspect of the present invention, the overlay vernier, and includes a parent vernier of the polygonal shape, and a child vernier is provided on the parent vernier and divides the parent vernier into a plurality of areas.

Preferably, the parent vernier has a rectangular structure.

Preferably, the ruler vernier is characterized in that it comprises an X-shaped cross in the diagonal direction.

Preferably, the length of one side of the parent vernier is characterized in that in the range of about 15 um to about 20 um.

Preferably, the maximum distance between neighboring sides in the X-shape that crosses diagonally in the ruler vernier is characterized in that more than 30um.

Preferably, the magnetic vernier is characterized in that it has a lattice shape.

Preferably, the parent vernier comprises an opaque layer, characterized in that the opaque layer is made of a metallic material.

Preferably, the parent vernier is characterized in that it has a circular structure.

Preferably, the magnetic vernier is characterized by having a plurality of bars spreading around the center point of the parent vernier.

Preferably, the ruler vernier divides the parent vernier into a plurality of regions having the same area.

Preferably, the ruler vernier divides the parent vernier into four regions.

According to another aspect of the present invention, the overlay measurement method using the overlay vernier, forming a polygonal parent vernier pattern on the substrate, the ruler to divide the parent vernier pattern into a plurality of areas on the parent vernier pattern Forming a vernier pattern, and detecting an amount of light reflected by each region by injecting light into the divided parent vernier pattern and measuring an overlay value.

The present invention can normally measure the overlay value even when an attack occurs on the overlay vernier in a manufacturing process such as chemical mechanical polishing (CMP) or an etching process, and as a result, there is an advantage of improving the characteristics and yield of the semiconductor device.

The present invention is to manufacture a highly integrated semiconductor device using an overlay vernier in order to reduce the alignment error, in the following detailed description so that those skilled in the art can easily implement the technical idea of the present invention. In order to describe, the most preferred embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a plan view illustrating an overlay vernier according to an embodiment of the present invention.

Referring to FIG. 3, the overlay vernier according to an embodiment of the present invention includes a parent vernier 310 formed in a quadrangle and a child vernier 320 having an X shape for dividing the parent vernier 310 into four regions. have.

Here, the parent vernier 310 is formed in a rectangular structure in which the length D1 of one side is in a range of about 15 um to about 20 um, and is made of an opaque layer. Here, a metal material may be used to form the opaque layer. The length D1 of one side of the parent vernier 310 corresponds to the size of the region where the overlay vernier is to be formed, but is not limited to the size.

 The ruler vernier 320 is formed in an orthogonal X-shape, and the maximum distance D2 between two neighboring sides of the X-shape is 30 um or more to sufficiently divide the parent vernier 310.

In the present embodiment, the parent vernier 310 of the rectangular structure is provided, but the present invention is not limited thereto, and may be formed of a polygon other than a circle or a rectangle.

For example, as shown in FIG. 4A, if the parent vernier 410a is formed in a circle, the child vernier 420a may have one or more bars spreading around the center point of the circle so as to divide the circle into a plurality of regions having the same size. It may be formed in the form. 4A illustrates an X-shaped ruler vernier 420a dividing the parent vernier 410a into four regions.

Meanwhile, even when the parent vernier 310 is formed in a quadrangle, as shown in FIG. 3, the ruler vernier 320 is not formed in an X shape, but the ruler vernier 420b has a lattice pattern as shown in FIG. 4B. ), It is also possible to divide the parent vernier 410b into a plurality of regions of the same size. That is, the child vernier can be formed in any structure that can divide the parent vernier into several areas of the same size.

FIG. 5 is a diagram for describing a method of measuring an overlay using an overlay vernier according to an embodiment of the present invention shown in FIG. 3.

Referring to FIG. 5, the parent vernier 310 is divided into four regions 310a, 310b, 310c, and 310d by the ruler vernier 320 formed in the X shape. After injecting light into the divided four regions 310a, 310b, 310c, and 310d, the amount of reflected light is detected to measure the overlay value. The measured value is compared up, down, left and right to adjust the alignment. For example, if the amount of light reflected in each area is 25%, the degree of alignment between the layers is 0, that is, the two corresponding layers can be regarded as correctly aligned.

As described above, the method for manufacturing a semiconductor device using the overlay vernier according to an embodiment of the present invention forms a pattern corresponding to the parent vernier, and the parent vernier on the mother vernier of the polygonal structure formed of an opaque layer is the same. After forming the vernier vernier splitting into a plurality of regions of the size, the incident light is incident on the divided region to detect the amount of reflected light and compare the detected results in up, down, left, and right to eliminate alignment errors. Therefore, as in the conventional overlay vernier, even if the overlay vernier is damaged due to a process problem such as a CMP process or an etching process, it is possible to increase the reliability of inter-layer alignment. In the present invention, by using a metal material as a material constituting the parent vernier, it is possible to minimize the loss in the process. As a result, when the semiconductor device is manufactured using the overlay vernier with improved alignment reliability, the characteristics and yield of the semiconductor device may be improved.

Preferred embodiments of the present invention described above are intended for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications may be made by the following patents. It should be regarded as belonging to the claims.

1 is a plan view of an overlay vernier according to the prior art.

2 is a view showing a case in which the overlay vernier according to the prior art is damaged.

3 is a plan view illustrating an overlay vernier according to an embodiment of the present invention.

4A and 4B illustrate an overlay vernier according to another embodiment of the present invention.

FIG. 5 is a diagram for describing a method of measuring an overlay using an overlay vernier according to an embodiment of the present invention shown in FIG. 3.

Claims (16)

Mor vernier in the form of a polygon; And Child vernier which is provided on the mother vernier and divides the mother vernier into a plurality of areas Overlay vernier including. The method of claim 1, The ruler vernier is an overlay vernier dividing the parent vernier into four regions. The method of claim 1, Overlay vernier that the parent vernier has a rectangular structure. The method of claim 3, wherein The ruler vernier is an overlay vernier comprising an X-shape perpendicular to the diagonal direction. The method of claim 4, wherein An overlay vernier of one side of said parent vernier in the range of about 15 um to about 20 um. The method of claim 5, An overlay vernier having a maximum distance of at least 30 μm between two neighboring sides in an X shape constituting the ruler. The method of claim 3, wherein An overlay vernier in which the ruler vernier has a lattice shape. The method of claim 1, The parent vernier is an overlay vernier comprising an opaque layer. The method of claim 8, The parent vernier is an overlay vernier comprising a metal material. The method of claim 1, Overlay vernier said parent vernier has a circular structure. The method of claim 10, The ruler vernier has an overlay vernier having a plurality of bars that extend from the center point of the parent vernier. The method of claim 1, Overlay vernier that the child vernier divides the parent vernier into a plurality of areas of the same size. Forming a vernier pattern of polygonal shape; Forming a child vernier pattern on the parent vernier pattern to divide the parent vernier pattern into a plurality of regions; And Injecting light into the divided vernier pattern to detect the amount of light reflected by each area to measure the overlay value Overlay measurement method comprising a. The method of claim 13, An overlay measuring method in which the parent vernier pattern has a polygon. The method of claim 14, The ruler vernier pattern includes a plurality of bars that divide the parent vernier pattern into a plurality of regions having the same size. The method of claim 15, The ruler vernier pattern divides the parent vernier pattern into four regions.
KR1020090058601A 2009-06-29 2009-06-29 Overlay vernier and method for measuring overlay using the same KR20110001192A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110223917A (en) * 2019-05-09 2019-09-10 上海华力集成电路制造有限公司 The method for reducing influence of the chemomechanical copper grinding to rear end alignment precision

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110223917A (en) * 2019-05-09 2019-09-10 上海华力集成电路制造有限公司 The method for reducing influence of the chemomechanical copper grinding to rear end alignment precision

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