KR20100078599A - Capacitor of semiconductor device and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: A capacitor of a semiconductor device and a manufacturing method thereof are provided to simplify the manufacturing process by forming an insulating layer of a metal-insulator-metal with a HfO2 film with Zr doped through co-sputtering. CONSTITUTION: A capacitor lower electrode(215) is formed on an interlayer dielectric layer(110) of a semiconductor substrate(100). The capacitor lower electrode is formed of a Ti/TiN film. A dielectric pattern(225) is formed of a Zr-doped-HfO2 film on the capacitor lower electrode. A capacitor upper electrode(235) is formed of a TiN film on the dielectric pattern.

Description

Capacitor of Semiconductor Device and Manufacturing Method Thereof {Capacitor of Semiconductor Device and Method for Manufacturing Thereof}

The embodiment relates to a capacitor of a semiconductor device and a method of manufacturing the same.

As a result of the high integration technology of semiconductor devices, semiconductor devices in which analog capacitors are integrated with logic circuits are used as research and development products. Analog capacitors are mainly used in the form of PIP (Polysilicon Insulator Polysilicon) or MIM (Metal-Insulator-Metal).

When the high capacity capacitor has a PIP (Polysilicon-Insulator-Polysilicon) structure, since the upper electrode and the lower electrode are used as polysilicon, an oxidation reaction occurs at the upper electrode, the lower electrode, and the insulator thin film interface, so that a natural oxide film is formed. The disadvantage is that the size is reduced. In addition, since the capacitance is lowered due to the depletion layer formed on the polysilicon, it is not suitable for high speed operation and high frequency operation.

To solve this problem, the structure of the capacitor was changed to MIM (Metal-Insulator-Metal). The MIM capacitors are mainly used in high performance semiconductor devices that require high Q values because of their low resistivity and no parasitic capacitance due to depletion therein. However, the MIM capacitor has a problem that the value of the capacitor is small compared to the effective area.

In order to increase the capacitor value, there are a method of increasing the capacitor area and a method of using a film having a high dielectric constant as the insulating film. The method of increasing the capacitor area has a problem of increasing chip area, and the method of using a film having a high dielectric constant has a problem of re-investing equipment or resetting a new process.

On the other hand, high-k dielectric metal insulator metal capacitors have received great attention in RF / analog circuit applications because of their high capacitance density (1fF / μm ² or more).

However, high dielectric constant (High-K) MIM capacitors are crystallized by high temperature during BEOL (Back End Of Layer) process, resulting in high leakage current. There is this.

In addition, HfO ₂ or HfO ₂ / A1 ₂ O ₂ in a stacking structure, which is currently used to replace an oxide film (SiO ₂ ) or a nitride film (SiN), has a Coefficient of Voltage (VCC2) compared to the oxide film (SiO ₂ ). This is a problem because TCC (Coefficietnt of Temperature) is high.

In particular, the sandwich structure or laminated structure of the HfO ₂ / A1 ₂ O ₂ is made of a structure to form an oxide film through the HF, Al metal target in the O ₂ atmosphere, due to the contamination (contamination) level of Al during Hf deposition Since the dielectric constant is determined, a purge time (purge time, cleaning step) is required when Hf is deposited after Al deposition, which causes a complicated process.

In addition, a sandwich structure in which SiNx / HfO ₂ / SiO ₂ is laminated may be used. However, such a sandwich structure is complicated in the process, and the etching ratio of the laminated films depends on the etch recipe (ehch recipe) to proceed to the step, because the process is complicated, there is an irrationality. In addition, after the BEOL process, the oxide film (SiO ₂ ) or the nitride film (SiN) is thermally stable, but HfO ₂ is thermally stressed, thereby deteriorating electrical characteristics.

Embodiments provide a capacitor of a semiconductor device and a method of manufacturing the same, by using a Zr doped HfO ₂ film as a capacitor insulating film to improve electrical characteristics of the device.

The capacitor of the semiconductor device according to the embodiment includes a capacitor lower electrode formed on the interlayer insulating layer of the semiconductor substrate; On the capacitor lower electrode Zr doped _{HfO 2 (Zr-doped HfO 2} ) the dielectric pattern formed in a membrane; And a capacitor upper electrode formed on the dielectric pattern to selectively expose the dielectric pattern.

In another embodiment, a capacitor manufacturing method of a semiconductor device includes: forming a lower electrode layer on a first interlayer insulating layer of a semiconductor substrate; Forming a capacitor insulating layer and Zr doped _{HfO 2 (Zr-doped HfO 2} ) film is deposited on the lower electrode layer; Forming an upper electrode layer on the capacitor insulating layer; Selectively etching the upper electrode layer to form a capacitor upper electrode; Selectively etching the capacitor insulating layer and the lower electrode layer to form a dielectric pattern and a capacitor lower electrode under the upper electrode.

According to the embodiment, it is possible to improve the electrical characteristics of the device by reducing the leakage current by using the base film of the MIM capacitor insulating film Zr doped _{HfO 2 (Zr-doped HfO 2} ).

A capacitor and a method of manufacturing the semiconductor device according to the embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

5 is a cross-sectional view illustrating a capacitor of a semiconductor device in accordance with an embodiment. For reference, reference numerals of the reference numerals of FIG. 5 will be described in the following manufacturing method.

The capacitor of the semiconductor device according to the embodiment may include a capacitor lower electrode 215 formed on the first interlayer insulating layer 110 of the semiconductor substrate 100, and Zr doped HfO ₂ on the capacitor lower electrode 215. A dielectric pattern 225 formed of a Zr-doped HfO ₂ film and a capacitor upper electrode 235 formed on the dielectric pattern 225 to selectively expose the dielectric pattern 225.

For example, the Zr doped HfO ₂ (Zr-doped HfO ₂ ) layer, which is the dielectric pattern 225, may have 4 to 12% zirconium (Zr) compared to hafnium (Hf).

The capacitor lower electrode 215 may be formed of a Ti / TiN film, and the capacitor upper electrode 235 may be formed of a TiN film.

A method of manufacturing a capacitor of a semiconductor device according to an embodiment will be described in detail with reference to FIGS. 1 to 5.

Referring to FIG. 1, a first interlayer insulating layer 110 including a lower wiring 115 is formed on a semiconductor substrate 100.

Although not shown in FIG. 1, an isolation layer for defining an active region may be formed in the semiconductor substrate 100, and devices such as a gate electrode and a source / drain of a transistor may be formed on the active region.

The first interlayer insulating layer 110 including the lower wiring 115 is formed on the semiconductor substrate 100. For example, the first interlayer insulating layer 110 may be formed of an oxide film or a nitride film. The lower interconnection 115 may be formed of various conductive materials including copper, aluminum, tungsten, an alloy, or silicide.

Meanwhile, before forming the first interlayer insulating layer 110, the PMD layer 105, which is an insulating layer before metal wiring, may be formed on the semiconductor substrate 100. For example, the PMD layer 105 may be formed of an FSG film.

A second interlayer insulating layer 120 is formed on the first interlayer insulating layer 110 on which the lower wiring 115 is formed. The second interlayer insulating layer 120 may be formed to cover the entire upper portion of the second interlayer insulating layer 120 so that the lower interconnection 115 is not exposed. For example, the second interlayer insulating layer 120 may be formed of a nitride film (SiN). The second interlayer insulating layer 120 may serve as an etch stop layer.

The lower electrode layer 210 is formed on the second interlayer insulating layer 120 to form a capacitor. The lower electrode layer 210 may have a structure in which a Ti layer and a TiN layer are stacked.

Referring to FIG. 2, a capacitor insulating layer 220 is formed on the lower electrode layer 210. The capacitor insulating layer 220 may use Zr-doped HfO ₂ (Zr-doped HfO ₂ ) as an insulating layer.

For example, the capacitor insulating layer 220 may be formed by a sputtering process. Specifically, the capacitor insulating layer 220 targets the zirconium (Zr) and the hafnium (Hafnium: Hf) in an O ₂ atmosphere to the lower electrode layer 210 through a DC magnetron sputtering process. It can be formed on).

In addition, the capacitor insulating layer 220 is co-sputtering (co-sputtering) can be deposited by adjusting the Zr and Hf which is almost similar series within 4 ~ 12% of Hf compared to Hf.

Therefore, the capacitor insulating layer 220 may be formed so that the ratio of Zr and Hf is 1: 9. In particular, when the concentration of Zr is 4% and the concentration of Hf is 96%, excellent results can be obtained in terms of liquidity, and your capacitance density can be 3 × 10 ^-6 to 3 × 10 ^-7 A / cm 2. .

As described above, the capacitor insulation layer 220 may be formed of a Zr-doped HfO ₂ (Zr-doped HfO ₂ ) film to obtain a high capacitance density thin film while reducing a low leakag current. Will be. In addition, since Zr-doped HfO ₂ (Zr-doped HfO ₂ ) is formed by a co-sputtering process, the process may be simplified and may have a low VCC value (Coefficient of Voltage value).

Referring to FIG. 3, an upper electrode layer 230 is formed on the capacitor insulating layer 220. The upper electrode layer 230 may be formed of a TiN layer.

Referring to FIG. 4, a MIM capacitor 200 is formed on the second interlayer insulating layer 120. The MIM capacitor 200 may be formed of a lower electrode 215, a dielectric pattern 225, and an upper electrode 235.

The MIM capacitor 200 may be formed by selectively etching the upper electrode layer 230, the capacitor insulating layer 220, and the lower electrode layer 210. For example, the MIM capacitor 200 selectively etches the upper electrode layer 230 using a first mask pattern (not shown) so that the capacitor insulating layer 220 is selectively exposed to the upper electrode 235. ) Can be formed. In addition, the capacitor insulating layer 220 and the lower electrode layer 210 are selectively etched by using a second mask pattern (not shown) to selectively expose the second interlayer insulating layer 120 to form the dielectric pattern 225. And a lower electrode 215.

Accordingly, the MIM capacitor 200 may be formed by the lower electrode 215, the dielectric pattern 225, and the upper electrode 235.

Referring to FIG. 5, the third interlayer dielectric layer 130, the fourth interlayer dielectric layer 140, and the fifth interlayer dielectric layer 150 are formed on the second interlayer dielectric layer 120 on which the capacitor 200 is formed. Is formed. For example, the third interlayer insulating layer 130 is formed of a TEOS film, the fourth interlayer insulating layer 140 is formed of a nitride film (SiN), and the fifth interlayer insulating layer 150 is a TEOS film. It can be formed as.

First to third metal wires 181, 182, and 183 are formed on the fifth interlayer insulating layer 150. The first metal wire 181 may be connected to the lower wire 115 through the first via contact 171. The second metal wire 182 may be connected to the lower electrode 215 and the second via contact 172. The third metal wire 183 may be connected to the upper electrode 235 through the third via contact 173.

The first to third via contacts 171, 172, and 173 form a via hole corresponding to the lower wiring 115, the lower electrode 215, and the upper electrode 235 in the fourth interlayer insulating layer 140. It can be formed by gap filling. The first to third metal wires 181, 182, and 183 may be formed by forming a trench in the fourth and fifth interlayer insulating layers 140 and 150 to expose the first to third via contacts 171, 172, and 173, and then gap-filling a metal material. have.

MIM capacitors for RF bias (RF baypass) or MIM capacitors for RF should have a low capacitance density deviation according to VCC1, VCC2, TCC and frequency.

Embodiment, the nose of the capacitor insulating film of the MIM capacitor - is formed by a sputtering (co-sputtering) Zr-doped _{HfO 2 (Zr-doped HfO 2} ) by a film can simplify the process.

In addition, by adjusting the concentration of the zirconium and hafnium so as to have a zirconium 4 ~ 12% compared to the hafnium, 1 × 10 ^-8 A / ㎠ (ITRS: International Technical Roadmap for Semiconductor required by the high-k MIM capacitor By maintaining the following characteristics, liquid current can be reduced.

In addition, a capacitor insulating film formed of a Zr-doped HfO ₂ (Zr-doped HfO ₂ ) film is manufactured by co-sputtering to obtain a high-k MIM capacitor because the etching ratio is the same.

The embodiments described above are not limited to the above-described embodiments and drawings, and it is to be understood that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be obvious to those who have it.

1 to 5 are views illustrating a capacitor manufacturing process of a semiconductor device according to an embodiment.

Claims (9)

A capacitor lower electrode formed on the interlayer insulating layer of the semiconductor substrate; On the capacitor lower electrode Zr doped _{HfO 2 (Zr-doped HfO 2} ) the dielectric pattern formed in a membrane; And a capacitor upper electrode formed on the dielectric pattern to selectively expose the dielectric pattern. The method of claim 1, The Zr doped HfO ₂ (Zr-doped HfO ₂ ) film is a capacitor of the semiconductor device, characterized in that the zirconium (Zr) compared to the hafnium (Hf) 4-12%. The method of claim 1, And the capacitor lower electrode is formed of a Ti / TiN film, and the capacitor upper electrode is formed of a TiN film. Forming a lower electrode layer on the first interlayer insulating layer of the semiconductor substrate; Forming a capacitor insulating layer and Zr doped _{HfO 2 (Zr-doped HfO 2} ) film is deposited on the lower electrode layer; Forming an upper electrode layer on the capacitor insulating layer; Selectively etching the upper electrode layer to form a capacitor upper electrode; Selectively etching the capacitor insulating layer and the lower electrode layer to form a dielectric pattern and a capacitor lower electrode under the upper electrode. The method of claim 4, wherein The capacitor insulating layer is a capacitor manufacturing method of a semiconductor device, characterized in that formed by a sputtering process to target zirconium (Zr) and hafnium (Hf) in an O ₂ atmosphere. The method of claim 5, The capacitor insulating layer is a capacitor manufacturing method of a semiconductor device, characterized in that formed by a co-sputtering process to target the zirconium (Zr) and hafnium (Hf). The method of claim 5, The Zr doped HfO ₂ (Zr-doped HfO ₂ ) film has a method of manufacturing a capacitor of a semiconductor device, characterized in that the zirconium (Zr) compared to the hafnium (Hf) 4-12%. The method of claim 4, wherein And the capacitor lower electrode is formed of a Ti / TiN film, and the capacitor upper electrode is formed of a TiN film. The method of claim 4, wherein Forming a second interlayer insulating layer on the capacitor lower electrode, the dielectric pattern, and the capacitor upper electrode; And And forming a via contact connected to the capacitor upper electrode and the capacitor lower electrode through the second interlayer insulating layer.

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