KR100696765B1 - Dielectric films of Semiconductor devices and Method for forming the same - Google Patents
Dielectric films of Semiconductor devices and Method for forming the same Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 29
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims abstract description 28
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- MXRIRQGCELJRSN-UHFFFAOYSA-N O.O.O.[Al] Chemical compound O.O.O.[Al] MXRIRQGCELJRSN-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000231 atomic layer deposition Methods 0.000 claims description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 7
- 239000010408 film Substances 0.000 description 85
- 239000010410 layer Substances 0.000 description 16
- 239000003990 capacitor Substances 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 230000000877 morphologic effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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Abstract
Description
도 1a 내지 도 1d 는 본 발명의 실시예에 따라 형성된 반도체소자의 유전체막 형성방법을 나타낸 단면도.1A to 1D are cross-sectional views illustrating a method of forming a dielectric film of a semiconductor device formed in accordance with an embodiment of the present invention.
본 발명은 반도체소자의 유전체막 및 그 형성방법에 관한 것으로, 특히 반도체소자의 고집적화에 충분한 정전용량을 확보할 수 있도록 고유전율을 갖는 박막을 이용하여 유전체막을 형성하는 기술에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric film of a semiconductor device and a method of forming the same, and more particularly, to a technique of forming a dielectric film using a thin film having a high dielectric constant so as to secure a sufficient capacitance for high integration of a semiconductor device.
반도체소자가 고집적화되어 셀 크기가 감소됨에따라 저장전극의 표면적에 비례하는 정전용량을 충분히 확보하기가 어려워지고 있다.As semiconductor devices are highly integrated and cell size is reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.
특히, 단위 셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게 하면서, 면적을 줄이는 것이 디램 소자의 고집적화에 중요한 요인이 된다.In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor, which occupies a large area on a chip, which is an important factor for high integration of the DRAM device.
그래서, ( εo × εr × A ) / T ( 단, 상기 εo 는 진공유전율, 상기 εr 은 유전막의 유전율, 상기 A 는 저장전극의 면적 그리고 상기 T 는 유전막의 두께 ) 로 표시되는 캐패시터의 정전용량 C 를 증가시키기 위하여, 유전상수가 높은 물질을 유전체막으로 사용하거나, 유전체막을 얇게 형성하거나 또는 저장전극의 표면적을 증가시키는 등의 방법을 사용하였다.Thus, the capacitance C of the capacitor represented by (εo × εr × A) / T (where, εo is the dielectric constant of the dielectric, εr is the dielectric constant of the dielectric film, A is the area of the storage electrode and T is the thickness of the dielectric film). In order to increase the dielectric constant, a material having a high dielectric constant was used as the dielectric film, a thin dielectric film was formed, or the surface area of the storage electrode was increased.
최근에는, 상기 저장전극의 표면적을 증가시키는 방법으로 콘케이브 캐패시터의 측벽에 반구형 다결정실리콘을 형성하여 반도체소자의 고집적화를 가능하게 하였으나, 반도체소자가 더욱 고집적화 됨에 따라 한계에 다달았으며, 이를 극복하기 위하여 고유전율을 갖는 유전체막을 사용하는 방법을 사용하고 있다. Recently, hemispherical polycrystalline silicon is formed on the sidewalls of the concave capacitor in order to increase the surface area of the storage electrode, thereby enabling high integration of semiconductor devices. A method of using a dielectric film having a high dielectric constant is used.
도시되지 않았으나 종래기술에 따른 반도체소자의 유전체막 형성방법을 다음과 같다. Although not shown, a method of forming a dielectric film of a semiconductor device according to the prior art is as follows.
먼저, 상기 반도체기판(도시안됨)의 소자분리막(도시안됨), 불순물 접합영역(도시안됨), 워드라인(도시안됨), 비트라인(도시안됨) 및 저장전극용 콘택플러그(도시안됨)가 구비되는 층간절연막(도시안됨)을 형성한다. First, an isolation layer (not shown), an impurity junction region (not shown), a word line (not shown), a bit line (not shown) and a contact plug (not shown) for a storage electrode of the semiconductor substrate (not shown) are provided. An interlayer insulating film (not shown) is formed.
상기 저장전극용 콘택플러그에 접속되는 하부전극(도시안됨)을 형성하고 그 표면에 유전체막(도시안됨) 및 상부전극(도시안됨)을 형성한다. A lower electrode (not shown) connected to the contact plug for storage electrodes is formed, and a dielectric film (not shown) and an upper electrode (not shown) are formed on the surface thereof.
이때, 상기 유전체막은 고유전 물질인 HfO2 또는 ZrO2 막의 비정질 상태와 알루미나 ( Al2O3 )를 이용하여 두께나 위치 그리고 조성비를 조합하여 사용한다. 여기서, 상기 HfO2 또는 ZrO2 막의 비정질 상태를 유지하기 위하여 별도의 질화처리 공정을 실시하고 그에 따른 후처리 공정을 실시하여야 한다. In this case, the dielectric film is used in combination with the amorphous state of the HfO2 or ZrO2 film, which is a high dielectric material, and using alumina (Al2O3) in combination of thickness, position, and composition ratio. In this case, in order to maintain an amorphous state of the HfO 2 or ZrO 2 film, a separate nitriding process should be performed and a post-treatment process accordingly should be performed.
그러나, 반도체소자가 필요로 하는 높은 캐패시턴스 값을 얻을 수 없게 됨에 따라 상기 비정질 상태의 HfO2 또는 ZrO2을 결정화시켜 유전체막의 유전율을 상승 시킴으로써 높은 캐패시턴스 값을 갖는 캐패시터를 형성할 수 있도록 하였다. However, as the high capacitance value required by the semiconductor device cannot be obtained, the amorphous HfO 2 or ZrO 2 is crystallized to increase the dielectric constant of the dielectric film, thereby forming a capacitor having a high capacitance value.
여기서, 상기 HfO2 또는 ZrO2 막은 결정화 공정으로 인하여 유전율을 상승시키지만 표면이 거칠어져 전기적 특성 및 형태기학적 특성이 나빠지게 됨으로써 누설전류 및 웨이퍼의 균질도 ( uniformity ) 저하 현상이 발생한다. Here, the HfO2 or ZrO2 film increases the dielectric constant due to the crystallization process, but the surface is roughened, thereby deteriorating the electrical and morphological properties, thereby causing leakage current and uniformity of the wafer.
상기한 바와 같이 종래기술에 따른 반도체소자의 유전체막 및 그 형성방법은, 고유전율의 HfO2 또는 ZrO2 박막을 결정화시켜 유전율을 증가시켰으나 전기적 특성 및 형태기학적 특성이 열화되어 반도체소자의 특성 및 신뢰성을 저하시키는 문제점이 있다. As described above, the dielectric film and the method of forming the semiconductor device according to the prior art have increased the dielectric constant by crystallizing the HfO2 or ZrO2 thin film having a high dielectric constant, but the electrical and morphological characteristics of the semiconductor device deteriorate to improve the characteristics and reliability of the semiconductor device. There is a problem of deterioration.
본 발명은 상기한 바와 같은 종래기술의 문제점을 해결하기 위하여, 고유전율을 갖는 HfO2 및 ZrO2 의 적층된 결정구조와 비정질의 알루미나를 조합하여 유전체막을 형성함으로써 유전율을 증가시키는 동시에 누설전류를 감소시키고 박막의 표면 거칠기를 개선하여 박막의 균질도를 개선하여 반도체소자의 고집적화의 충분한 캐패시턴스를 확보할 수 있는 반도체소자의 유전체막 및 그 형성방법을 제공하는데 그 목적이 있다. The present invention is to solve the problems of the prior art as described above, by forming a dielectric film by combining a laminated crystal structure of HfO2 and ZrO2 having a high dielectric constant and amorphous alumina to increase the dielectric constant while reducing leakage current and thin film SUMMARY OF THE INVENTION An object of the present invention is to provide a dielectric film of a semiconductor device and a method for forming the same, which can improve the surface roughness of the film and improve the homogeneity of the thin film to ensure sufficient capacitance for high integration of the semiconductor device.
상기 목적 달성을 위해 본 발명에 따른 반도체소자의 유전체막은,
반도체기판 상에 제1유전체막과 제2유전체막 적층구조를 포함하되, 상기 제1유전체막과 제2유전체막이 서로 다르도록 결정화된 HfO2 막과 ZrO2 막의 적층구조를 형성하거나 ZrO2 막과 HfO2 막의 적층구조를 형성하고,The dielectric film of the semiconductor device according to the present invention for achieving the above object,
A stacked structure of a HfO2 film and a ZrO2 film including a first dielectric film and a second dielectric film stacked structure on a semiconductor substrate, wherein the first dielectric film and the second dielectric film are crystallized so as to be different from each other, or the ZrO2 film and the HfO2 film are stacked. Form a structure,
상기 제1유전체막과 제2유전체막 적층구조 상측 또는 하측에 형성된 제3유전체막인 비정질의 알루미나층을 포함하는 것과,An amorphous alumina layer that is a third dielectric film formed above or below the first dielectric film and the second dielectric film stacked structure;
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상기 제1유전체막은 30 ～ 100 Å 두께로 형성된 것과,The first dielectric film is formed to a thickness of 30 ~ 100 Å,
상기 제2유전체막은 5 ～ 100 Å 두께로 형성된 것과,The second dielectric film is formed to a thickness of 5 ~ 100 Å,
상기 제3유전체막은 5 ～ 50 Å 두께로 형성된 것을 특징으로 한다. The third dielectric film is characterized in that formed 5 ~ 50 thickness.
또한, 상기 목적 달성을 위해 본 발명에 따른 반도체소자의 유전체막 형성방법은, In addition, the dielectric film forming method of a semiconductor device according to the present invention for achieving the above object,
반도체기판 상에 제1유전체막과 제2유전체막을 형성하되, 상기 제1유전체막과 제2유전체막은 서로 동일하지 않도록 결정화된 HfO2 막과 ZrO2 막을 적층하여 형성하는 공정과,Forming a first dielectric film and a second dielectric film on a semiconductor substrate, wherein the first dielectric film and the second dielectric film are formed by stacking a crystallized HfO2 film and a ZrO2 film such that they are not identical to each other;
상기 제2유전체막 상에 제3유전체막인 비정질의 알루미나층을 형성하는 공정을 포함하는 것과,Forming an amorphous alumina layer that is a third dielectric film on the second dielectric film;
상기 제1유전체막과 제2유전체막은 원자층증착 ( ALD : Atomic Layer Deposition ) 방법으로 형성하되, 상기 제1유전체막은 30 ～ 100 Å 두께로 형성하고, 상기 제2유전체막은 5 ～ 100 Å 두께로 형성된 것과,The first dielectric film and the second dielectric film are formed by atomic layer deposition (ALD), wherein the first dielectric film is formed to have a thickness of 30 to 100 Å, and the second dielectric film has a thickness of 5 to 100 Å. Formed,
상기 알루미나층은 원자층증착 방법으로 5 ～ 50 Å 두께만큼 형성하는 것을 제1특징으로 하고, The alumina layer is a first feature that is formed by the thickness of 5 ~ 50 Å by atomic layer deposition method,
반도체기판 상에 제1유전체막인 비정질의 알루미나층을 형성하는 공정과,Forming an amorphous alumina layer, which is a first dielectric film, on the semiconductor substrate;
상기 제1유전체막 상에 제2유전체막과 제3유전체막을 형성하되, 상기 제2유전체막과 제3유전체막은 서로 동일하지 않도록 결정화된 HfO2 막과 ZrO2 막을 적층하여 형성하는 공정을 포함하는 것을 제2특징으로 한다.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다. Forming a second dielectric film and a third dielectric film on the first dielectric film, wherein the second dielectric film and the third dielectric film are formed by stacking a crystallized HfO2 film and a ZrO2 film so as not to be identical to each other. We assume two features.
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
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도 1a 내지 도 1d 는 본 발명의 실시예에 따른 반도체소자의 유전체막 형성방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a dielectric film of a semiconductor device in accordance with an embodiment of the present invention.
도 1a 를 참조하면, 상기 반도체기판(도시안됨)의 소자분리막(도시안됨), 불순물 접합영역(도시안됨), 워드라인(도시안됨) 및 비트라인(도시안됨)이 형성된 층간절연막(도시안됨)을 형성한다. Referring to FIG. 1A, an interlayer insulating film (not shown) in which an isolation layer (not shown), an impurity junction region (not shown), a word line (not shown), and a bit line (not shown) are formed on the semiconductor substrate (not shown). To form.
상기 층간절연막 상부에 식각장벽층(도시안됨)인 질화막을 형성한다. A nitride film as an etch barrier layer (not shown) is formed on the interlayer insulating film.
저장전극 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 층간절연막을 식각하여 저장전극 콘택홀을 형성하고 이를 매립하는 도전층으로 저장전극 콘택플러그(도시안됨)를 형성한다. The interlayer insulating layer is etched by a photolithography process using a storage electrode contact mask (not shown) to form a storage electrode contact hole, and a storage electrode contact plug (not shown) is formed as a conductive layer filling the interlayer insulating layer.
그 다음, 상기 저장전극 콘택플러그에 접속되는 하부전극(11)을 형성한다. Next, a
상기 하부전극(11) 상부에 제1유전체막(13)을 형성한다. 이때, 상기 제1유전체막(13)은 ZrO2 막으로 형성하거나 HfO2 막으로 형성한다. The first
도 1b를 참조하면, 상기 제1유전체막(13) 상부에 제2유전체막(15)을 형성한다. 이때, 상기 제2유전체막(15)은 HfO2 막으로 형성하거나 ZrO2 막으로 형성한다. Referring to FIG. 1B, a second
여기서, 상기 제1유전체막(13)은 30 ～ 100 Å 의 두께로 형성한 것으로, 박막의 특성상 30 Å 이상의 두께부터 증착되면서 결정화된다. 상기 제2유전체막(15)은 5 ～ 100 Å 의 두께로 형성한 것으로, 상기 제1유전체막(13) 상부에 형성되며 결정화되어 증착된다. Here, the first
상기 제1유전체막(13)과 제2유전체막(15)은 동일하지 않도록 각각 ZrO2 막이나 HfO2 막으로 형성한 것으로, 원자층증착 ( ALD : Atomic Layer Deposition ) 방법을 이용하여 형성한 것이다. The first
도 1c를 참조하면, 상기 제2유전체막(15) 상부에 제3유전체막(17)인 비정질의 알루미나층을 원자층증착 방법으로 5 ～ 50 Å 두께만큼 형성한다. Referring to FIG. 1C, an amorphous alumina layer, which is the third
도 1d를 참조하면, 상기 제3유전체막(17) 상에 상부전극(19)을 형성하여 캐패시터를 형성한다. Referring to FIG. 1D, a capacitor is formed by forming an
본 발명의 다른 실시예는 상기 제1,2,3유전체막(13,15,17)을 적층구조 대신 제3유전체막(17), 제1유전체막(13), 제2유전체막(15)의 적층구조를 제공하는 것이다. According to another embodiment of the present invention, the first, second, and third
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 유전체막 및 그 형성방법은, 동일하지 않은 ZrO2 막이나 HfO2 막으로 각각 제1유전체막과 제2유전체막의 적층구조를 형성하고 상기 적층구조의 상측 및 하측에 비정질의 알루미나층을 형성하여 고유전율을 가지며, 전기적 특성 및 형태기학적 특성이 향상된 유전체막을 제공함으로써 반도체소자의 고집적화에 충분한 캐패시턴스를 확보할 수 있도록 하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다. As described above, the dielectric film of the semiconductor device and the method of forming the same according to the present invention form a stacked structure of the first dielectric film and the second dielectric film, each of which is made of a non-identical ZrO2 film or an HfO2 film, and the upper side and By forming an amorphous alumina layer on the lower side to provide a dielectric film having high dielectric constant and improved electrical and morphological characteristics, it is possible to secure sufficient capacitance for high integration of semiconductor devices and thereby to improve the characteristics and reliability of semiconductor devices. The present invention provides the effect of enabling high integration of semiconductor devices.
아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.
Claims (8)
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| JP2018129354A (en) * | 2017-02-07 | 2018-08-16 | 株式会社アルバック | Forming method of gate insulation film, and gate insulation film |
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| JP2004260168A (en) * | 2003-02-27 | 2004-09-16 | Sharp Corp | Atomic layer deposition of nanolaminate film |
| KR20050074850A (en) * | 2004-01-14 | 2005-07-19 | 삼성전자주식회사 | Capacitor including a dielectric layer having crystalline areas distributed inhomogeneously and method of fabricating the same |
| KR20060019011A (en) * | 2004-08-26 | 2006-03-03 | 삼성전자주식회사 | Metal-insulator-metal capacitor having dielectric film with layer for preventing crystallization and method for manufacturing the same |
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| KR20040060443A (en) * | 2002-12-30 | 2004-07-06 | 삼성전자주식회사 | Capacitor of a semiconductor device and manufacturing method whereof |
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