KR20100078357A - Method for fabricating a cu metal layer - Google Patents

Method for fabricating a cu metal layer Download PDF

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Publication number
KR20100078357A
KR20100078357A KR1020080136598A KR20080136598A KR20100078357A KR 20100078357 A KR20100078357 A KR 20100078357A KR 1020080136598 A KR1020080136598 A KR 1020080136598A KR 20080136598 A KR20080136598 A KR 20080136598A KR 20100078357 A KR20100078357 A KR 20100078357A
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KR
South Korea
Prior art keywords
film
copper
forming
wiring
semiconductor substrate
Prior art date
Application number
KR1020080136598A
Other languages
Korean (ko)
Inventor
김성진
Original Assignee
주식회사 동부하이텍
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Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080136598A priority Critical patent/KR20100078357A/en
Publication of KR20100078357A publication Critical patent/KR20100078357A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for fabricating a copper metal wiring is provided to reduce the electro-migration and stress migration phenomena of copper by preventing electronic copper plating particles from being migrated to a contact region and a lower metal wiring with unstable high-energy. CONSTITUTION: A lower copper wiring is formed on a semiconductor substrate(200). An interlayer insulating film is formed on the semiconductor substrate, and a dual damascene pattern is formed by patterning the interlayer insulating film. A tantalum/tantalum nitride film(208) is formed in the dual damascene pattern. Copper fills the dual damascene pattern to form an upper copper wiring. The upper copper wiring is connected with the lower copper wiring. A tantalum film is formed on the entire surface of the semiconductor substrate including the upper copper wiring. A tantalum nitride film(214) is formed on the tantalum film.

Description

Copper metal wiring formation method {METHOD FOR FABRICATING A Cu METAL LAYER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and more particularly, to electromigration (SM) and stress migration (SM) of copper by preventing ECP particles from moving toward unstable high energy contacts or lower metal wiring. The present invention relates to a copper metal wiring forming method capable of improving the characteristics.

The semiconductor device manufacturing process is divided into a front end of the line (FEOL) and a wiring end (Back End Of the Line) BEOL. Wiring technology connects individual transistors to each other to implement a power supply and signal path on a silicon that constitutes an integrated circuit.

In such wiring technology, wiring using copper (Cu), a material having high EM (electro-migration) resistance, has been actively developed. However, since copper is not easily etched and oxidized during the process, copper metal wirings are formed through a dual damascene process technology unlike a general metal process. In particular, in the dual damascene process, via holes and trenches are formed in the interlayer insulating film, and copper is then embedded in the via holes or trenches using an electrochemical plating method and planarized by a chemical mechanical polishing process. By doing so, a copper wiring is formed.

In the dual damascene process, a damascene pattern including vias and trenches is formed in the interlayer insulating layer. As such, the dual damascene process can reduce the step of the metal wiring, making subsequent processing easier. Conventionally, as a method of forming a damascene pattern, a method of forming a via first and a trench later or a method of forming a trench first and a via later is used. Either method requires several steps of photolithography and etching, which increases the number of processes compared to the general metallization process.

The most widely used method of the dual damascene process is a method of forming a via first. Referring to FIGS. 1A to 1D, a method of forming a metal wire using a conventional dual damascene pattern will be described.

1A to 1D are cross-sectional views illustrating a method of forming metal wirings in a conventional semiconductor device.

As shown in FIG. 1A, a first copper thin film is formed on a semiconductor substrate 11, and the first copper thin film is selectively removed through a photo and etching process to form a first copper wiring 12.

Subsequently, a nitride film 13 is formed on the entire surface of the semiconductor substrate 11 including the first copper wiring 12, and an interlayer insulating film 14 is formed on the nitride film 13. The nitride layer 13 is used as an etch stop layer and the interlayer insulating layer 14 is made of FSG material.

Next, after applying the first photoresist 15 on the interlayer insulating layer 14, the first photoresist 15 is patterned by an exposure and development process to define a contact region.

In addition, the via layer 16 is formed by selectively removing the interlayer insulating layer 14 using the patterned first photoresist 15 as a mask and using the nitride layer 13 as an etching end point.

As shown in FIG. 1B, the first photoresist 15 is removed and the second photoresist 17 is coated on the entire surface of the semiconductor substrate 11 including the via holes 16. The second photoresist 17 is patterned.

Subsequently, the interlayer insulating layer 14 is selectively removed from the surface by a predetermined thickness using the patterned second photoresist 17 as a mask to form a trench 18.

As shown in FIG. 1C, the second photoresist 17 is removed and the nitride film 13 remaining under the via hole 16 is etched off.

Subsequently, a barrier metal film 19 is formed on the entire surface of the semiconductor substrate 11 including the trench 18 and the via hole 16 by a metal organic chemical vapor deposition (MOCVD) method.

 Subsequently, after forming a copper seed layer on the barrier metal film 19, an electronic copper plating (ECP) is performed to form a second copper thin film 20a. .

As shown in FIG. 1D, a CMP process is performed on the entire surface of the second copper thin film 20a to target the upper surface of the interlayer insulating film 14 to form the second copper thin film 20a and the barrier metal film 19. ) Is selectively polished to form a second copper wiring 20 in the trench 18 and the via hole 16.

Conventional metal wiring formation methods react with various additives in the copper ECP process to form ECP particles, which particles have unstable high energy contact portions, ie where the first copper wiring and the second copper wiring meet or the first copper Since the wires move through the grains to form voids, the reliability of the semiconductor device is reduced.

When the polymer is deposited on the chamber wall or the upper side and the semiconductor substrate is unloaded after the reactive ion etching process, scratches or cracks are generated on the semiconductor substrate, thereby lowering the yield of the semiconductor device.

The present invention forms a Ta film and a TaN film thereon after forming a copper wiring, thereby preventing the ECP particles generated during the copper ECP process from moving toward a contact portion or a lower metal wiring having unstable high energy.

The method for forming a copper metal wiring according to the present invention includes forming a dual damascene pattern by forming an interlayer insulating film on a semiconductor substrate on which a lower copper wiring is formed, and patterning the interlayer insulating film, and Ta / TaN on an inner wall of the dual damascene pattern. Forming a top copper wiring connected to the bottom copper wiring by embedding copper in the dual damascene pattern having the Ta / TaN film formed thereon, and forming a Ta film on the entire surface of the semiconductor substrate on which the top copper wiring is formed. And forming a TaN film on the Ta film.

The present invention forms a Ta film and a TaN film thereon after forming a copper wiring, thereby preventing the ECP particles generated during the copper ECP process from moving toward a contact portion or a lower metal wiring, which has unstable high energy, and thus, EM (ElectroMigration) of copper. ) And SM (Stress Migration) characteristics can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, if it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

In an embodiment of the present invention, after forming a copper wiring, by forming a Ta film and a TaN film thereon, the ECP particles generated during the copper ECP process can be prevented from moving toward a contact portion or a lower metal wiring that has unstable high energy. The copper wiring formation method is demonstrated.

2A through 2C are cross-sectional views illustrating a process of forming a metal wiring according to an embodiment of the present invention.

As shown in FIG. 2A, the nitride film 204 and the interlayer insulating film 206 are formed on the semiconductor substrate 200 on which the first copper wiring 202 is formed through the process as shown in FIGS. 1A to 1D. After forming, the interlayer insulating film 206 and the nitride film 204 are patterned to form a dual damascene pattern consisting of via holes and trenches. Then, a Ta / TaN film 208, which is a barrier metal film, is formed on the entire surface of the semiconductor substrate 200 including trenches and via holes by MOCVD (Metal Organic Chemical Vapor Deposition).

 Subsequently, after forming a copper seed layer on the Ta / TaN film 208, and then proceeding with ECP to form a second copper thin film, the upper surface of the interlayer insulating film 206 on the front of the second copper thin film The second copper thin film and the Ta / TaN film 208 are selectively polished by a CMP process to form a second copper wiring 210 in the trench and the via hole.

Then, as illustrated in FIG. 2B, an Ta implantation process using Ta is formed to form a Ta film 212 on the second copper wiring 210 and on the interlayer insulating film 206.

Then, as shown in FIG. 2C, an annealing process in an N 2 atmosphere is performed so that the N component reacts with Ta in the Ta film 212 to form a TaN film 214 on top of the Ta film 212.

According to the present invention, since the second copper wiring 210 has a structure surrounded by the Ta film 212 and the TaN film 214, that is, an encapsulated structure, the ECP particles generated during the copper ECP process have unstable high energy. Movement toward the contact portion or the lower portion of the first copper wiring 202 can be prevented.

It has been described so far limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

1A to 1D are cross-sectional views illustrating a process of forming a copper metal wire using a damascene pattern according to the prior art;

2A to 2C are cross-sectional views illustrating a process of forming a copper metal wire according to the present invention.

Description of the Related Art

200 semiconductor substrate 202 first copper wiring

204: nitride film 206: interlayer insulating film

208 Ta / TaN film 210 Second copper wiring

212: Ta film 214: TaN film

Claims (3)

Forming an interlayer insulating film on the semiconductor substrate on which the lower copper wiring is formed, and then patterning the interlayer insulating film to form a dual damascene pattern; Forming an upper copper wiring connected to the lower copper wiring by forming a Ta / TaN film on an inner wall of the dual damascene pattern and then embedding copper inside the dual damascene pattern on which the Ta / TaN film is formed; Forming a Ta film on an entire surface of the semiconductor substrate on which the upper copper wiring is formed; Forming a TaN film on the Ta film Copper metal wiring forming method comprising a. The method of claim 1, The forming of the Ta film may include forming the Ta film through a Ta implant process on the entire surface of the semiconductor substrate on which the upper copper wiring is formed. The method of claim 1, In the forming of the TaN film, the TaN film is formed by performing an annealing process using N2 gas on the entire surface of the semiconductor substrate on which the Ta film is formed.
KR1020080136598A 2008-12-30 2008-12-30 Method for fabricating a cu metal layer KR20100078357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080136598A KR20100078357A (en) 2008-12-30 2008-12-30 Method for fabricating a cu metal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080136598A KR20100078357A (en) 2008-12-30 2008-12-30 Method for fabricating a cu metal layer

Publications (1)

Publication Number Publication Date
KR20100078357A true KR20100078357A (en) 2010-07-08

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Family Applications (1)

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KR1020080136598A KR20100078357A (en) 2008-12-30 2008-12-30 Method for fabricating a cu metal layer

Country Status (1)

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KR (1) KR20100078357A (en)

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