KR20100076812A - Memory device capable of data compression test - Google Patents

Memory device capable of data compression test Download PDF

Info

Publication number
KR20100076812A
KR20100076812A KR1020080134983A KR20080134983A KR20100076812A KR 20100076812 A KR20100076812 A KR 20100076812A KR 1020080134983 A KR1020080134983 A KR 1020080134983A KR 20080134983 A KR20080134983 A KR 20080134983A KR 20100076812 A KR20100076812 A KR 20100076812A
Authority
KR
South Korea
Prior art keywords
data
read
global bit
output
bit lines
Prior art date
Application number
KR1020080134983A
Other languages
Korean (ko)
Inventor
박기천
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080134983A priority Critical patent/KR20100076812A/en
Publication of KR20100076812A publication Critical patent/KR20100076812A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques

Abstract

The present invention discloses a memory device capable of data compression testing capable of preventing a drop in yield. A data compression testable memory device according to the present invention comprises: a plurality of write global bit lines and a plurality of read global bit lines arranged alternately with each other; Multiple test global bit lines; In response to the compression test control signal, all mode sense amplifiers for selectively amplifying-output any one of the plurality of read data from the memory cell array to any one of the plurality of write global bit lines and the plurality of test global bit lines; Dual mode sense amplifiers selectively amplifying-output the remainder of the plurality of read data from the memory cell array to corresponding read global bit lines and corresponding test global bit lines in response to the compression test control signal; And a data compressor selectively responsive to the compression test control signal to compress read data on the test global bit lines and output compressed data through a read global bit line to which the mono mode sense amplifier is connected. The dual mode sense amplifiers drive the read global bit line to a specific level voltage corresponding to the enable period of the compression test control signal.

Description

Memory device capable of data compression test

The present invention relates to a memory device having a write-global bus and a read-global bus, and more particularly, to a memory device capable of a data compression test.

Recently, a semiconductor memory device includes a read global bus and a write global bus instead of one global bus to improve a slope of a global input / output signal. The write global bus transfers data from the data pads into the cell array upon data writing. The read global bus delivers data from the cell array towards the data pads upon data read.

In addition, with the development of process technology, as semiconductor memory devices are highly integrated, tests are performed for a long time with expensive test equipment after manufacturing to ensure chip reliability. In order to test such a memory device, in order to reduce the time and cost of the test, a self test circuit is built in the chip in advance in the design stage.

The DQ compress test, which is a kind of self-test, stores the same data in a plurality of memory cells and outputs the data again at the same time, and then compresses the outputted data at the same time, thereby testing whether there is an error in the memory. That's how. Since the compressed data is output, the data compression test can minimize the usage quantity of the data output channel (ie, data pad). Thus, the data compression test enables testing of multiple dies at the same time.

1 is a block diagram illustrating a data storage path of a memory device for implementing a data compression test. As shown in FIG. 1, the memory device includes first to fourth aligners 20 to 26 connected to the first data input buffers 10 to 16, respectively. The first to fourth data input buffers 10 to 16 input serial data from corresponding first to fourth data pads (not shown). The first to fourth aligners 20 to 26 convert serial data from the corresponding data input buffers 10 to 16 into parallel data of 8 bits. These first to fourth aligners 20 to 26 are connected to first input ports of the corresponding first to fourth multiplexers 30 to 36, respectively. The first aligner 20 is also connected to all of the second input ports of the first to fourth multiplexers 30 to 36. Output ports of the first to fourth multiplexers 30 to 36 are connected to corresponding first to fourth data input sense amplifiers 40 to 46, respectively. The first to fourth multiplexers 30 to 36 transmit parallel data on the first or second input port toward corresponding data input sense amplifiers 40 to 46 in response to the compression test control signal TM_COMP. In fact, when the compression test control signal TM_COMP is disabled (i.e., during normal operation), the first to fourth multiplexers 30 to 36 are connected from the corresponding first to fourth aligners 20 to 26. The parallel data is supplied to the corresponding data input sense amplifiers 40 to 46. In contrast, when the compression test control signal TM_COMP is enabled (that is, during the data compression test operation), all of the first to fourth multiplexers 30 to 36 are parallel data from the first aligner 20. Is supplied to the corresponding data input sense amplifiers 40 to 46. The first to fourth data input sense amplifiers 40 to 46 amplify the parallel data from the corresponding multiplexers 30 to 36 so that the parallel data has a CMOS voltage level instead of the TTL voltage level. This 32-bit amplified parallel data is transferred through 32-bit write global I / O buses (WGIO0 <0: 7>, WGIO1 <0: 7>, WGIO2 <0: 7>, WGIO3 <0: 7>). Supply to a memory bank (not shown). As a result, during the data compression test, the memory device uses all of the write global I / O buses (WGIO0 <0: 7>, WGIO1 <0: 7>, WGIO2 <0: 7>, WGIO3 <0: 7>). Cause the same data to be stored.

2 is a block diagram illustrating a portion of a data read path of a memory device for implementing a data compression test. Referring to FIG. 2, the memory device includes first to fourth input / output sense amplifiers 50 to 56 and a data compressor 60 that commonly respond to the compression test control signal TM_COMP. These first to fourth input / output sense amplifiers 50 to 56 and the data compressor 60 are included in each memory bank.

The first input / output sense amplifier 50 senses and amplifies 1-bit read data on the lowest positive and negative local input / output lines LIO <0> and LIOB <0> among the 4-bit local input / output buses. In addition, the first input / output sense amplifier 50, in response to the compression test control signal TM_COMP, receives the amplified 1-bit read data as the lowest of the 8-bit first read global input / output buses RGIO0 <0: 7>. Bit line RGIO0 <0> (hereinafter referred to as "lowest first lead global I / O bit line") or the lowest bit line TGIO0 <0> of the first test global I / O bus TGIO0 <0: 7> (Hereinafter, referred to as "lowest first test global input / output bit line"). In fact, when the compression test control signal TM_COMP is disabled (that is, during normal read operation), the first input / output sense amplifier 50 may output the amplified read data to the lowest first read global input / output bit line RGIO0 <. 0>). In this case, the lowest first test global input / output bit line TGIO0 <0> is not driven. On the contrary, when the compression test control signal TM_COMP is enabled (that is, during a data compression test operation), the first input / output sense amplifier 50 may output the amplified read data to the lowest first test global input / output bit line RGIO0. <0>). At this time, the lowest first read global input / output bit line RGIO0 <0> is not driven.

Like the first input / output sense amplifier 50, the second to fourth input / output sense amplifiers 50 also have positive and negative local input and output bit lines LIO <1> and LIOB <1>, next higher and negative local. The positive and negative bit data on the input / output bit lines LIO <2> and LIOB <2> and the most significant positive and negative local input and output bit lines LIO <3> and LIOB <3> are respectively sense-amplified. In addition, the second to fourth input / output sense amplifiers 52 to 56 may output the amplified read data to the lowest second to fourth read global input / output bit lines RGIO1 <0 in response to the compression test control signal TM_COMP. >, RGIO2 <0>, RGIO3 <0>) or the lowest second to fourth test global input / output bit lines TGIO1 <0>, TGIO2 <0>, and TGIO3 <0>, respectively. Similarly, when read data is output to the lowest second to fourth read global input / output bit lines RGIO1 <0>, RGIO2 <0>, and RGIO3 <0> (that is, during a normal read operation), the lowest second The fourth to fourth test global input / output bit lines TGIO1 <0>, TGIO2 <0>, and TGIO3 <0> are not driven. On the contrary, when read data is output to the lowest second to fourth test global I / O bit lines TGIO1 <0>, TGIO2 <0>, and TGIO3 <0> (that is, during a data compression test operation), The second to fourth read global input / output bit lines RGIO1 <0>, RGIO2 <0>, and RGIO3 <0> are not driven.

The data compressor 60 performs the lowest first through fourth test global input / output bit lines TGIO0 <0> and TGIO1 <0 only when the compression test control signal TM_COMP is enabled (that is, during data compression test). >, TGIO2 <0>, TGIO3 <0>) compresses 4-bit read data to generate 1-bit compressed data. The 1-bit compressed data generated by the data compressor 60 is output toward the data pad (not shown) through the lowest first read global input / output bit line RGIO0 <0>.

During the data compression test operation, only one of the lowest first to fourth read global I / O bit lines RGIO0 <0, RGIO1 <0>, RGIO2 <0>, RGIO3 <0> is used as the representative data channel. Only the first read global I / O bus (that is, eight bit lines) of the first to fourth read global I / O buses (total 32 bit lines) is used as the representative channel. The 8-bit compressed data may be output in serial form through one of four data pads (ie, a data pad connected to the first data input buffer 10). Accordingly, the write operation and the physical state of the memory device can be detected through the confirmation of the compressed data from the specific data pad. Eight lead global I / O bitlines and one data pad were used for the data compression test, but four or 16 lead global I / O bitlines and two data pads may be used, depending on design specifications.

In this way, since the write global I / O bus WGIO is used for all data compression tests, the state can be detected even if a short circuit or a disconnection occurs. On the other hand, only part of the read global I / O bus is used for data compression testing. For this reason, although a short circuit or disconnection in some of the lead global I / O buses used may be detected, whether or not a fault of the remaining lead global I / O buses that are not used cannot be detected.

In addition, the number of bit lines included in the write global I / O bus and the read global I / O bus is inevitably increased because the number of pre-patches or data pads increases as the operation speed of the memory device increases. This also increases the probability of disconnection and short circuit in the lead global I / O bus. In addition, the number of coupled memory devices being packaged increases. Therefore, not only the yield of the memory device is lowered, but also the waste of cost and time due to unnecessary packaging becomes large.

Accordingly, an object of the embodiments of the present invention is to solve the above problems and to provide a data compression testable memory device capable of preventing a decrease in yield.

According to an embodiment of the present invention, a data compression testable memory device includes: a plurality of write global bit lines and a plurality of read global bit lines arranged alternately with each other; Multiple test global bit lines; In response to the compression test control signal, all mode sense amplifiers for selectively amplifying-output any one of the plurality of read data from the memory cell array to any one of the plurality of write global bit lines and the plurality of test global bit lines; Dual mode sense amplifiers selectively amplifying-output the remainder of the plurality of read data from the memory cell array to corresponding read global bit lines and corresponding test global bit lines in response to the compression test control signal; And a data compressor selectively responsive to the compression test control signal to compress read data on the test global bit lines and output compressed data through a read global bit line to which the mono mode sense amplifier is connected.

Preferably, the dual mode sense amplifiers drive the read global bit line to a specific level voltage corresponding to the enable period of the compression test control signal.

Preferably, the lead global bit line connected to the mono mode sense amplifier is disposed at the outermost portion.

According to the above configuration, the memory device in accordance with the embodiment of the present invention detects a short circuit condition in a global input / output bus through a data compression test. As a result, the packaging of the defective memory device is greatly reduced. As a result, a decrease in yield of the memory device can be prevented and unnecessary waste of time and money can be saved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

FIG. 3 is a block diagram schematically illustrating a read path structure of a data compression testable memory device according to example embodiments. FIG. Referring to FIG. 3, the memory device may include a mono mode input / output sense amplifier 100, first to third dual mode input / output sense amplifiers 110, 112, and 114, and a data compressor 120 in response to a compression test control signal TM_COMP. It is provided. These all mode input / output sense amplifiers 100, the first to third dual mode input / output sense amplifiers 110 to 114, and the data compressor 120 are included in each memory bank.

The mono mode input / output sense amplifier 110 senses and amplifies 1-bit read data on the lowest positive and negative local input / output lines LIO <0> and LIOB <0> among the 4-bit local input / output buses. In addition, the mono mode input / output sense amplifier 100, in response to the compression test control signal TM_COMP, transmits the amplified 1-bit read data to the lowest of the 8-bit first read global input / output buses RGIO0 <0: 7>. Bit line RGIO0 <0> (hereinafter referred to as "lowest first lead global I / O bit line") or the lowest bit line TGIO0 <0> of the first test global I / O bus TGIO0 <0: 7> (Hereinafter, referred to as "lowest first test global input / output bit line"). In detail, when the compression test control signal TM_COMP is disabled (that is, during normal read operation), the mono mode input / output sense amplifier 100 displays the amplified read data as the lowest first read global input / output bit line ( RGIO0 <0>). In this case, the lowest first test global input / output bit line TGIO0 <0> is not driven. On the contrary, when the compression test control signal TM_COMP is enabled (that is, during the data compression test operation), the mono mode input / output sense amplifier 100 displays the amplified read data at the lowest first test global input / output bit line RGIO0. <0>). At this time, the lowest first read global input / output bit line RGIO0 <0> is not driven.

The first dual mode input / output sense amplifier 110 senses and amplifies 1-bit read data on positive and negative local input / output lines LIO <1> and LIOB <1> of the lower and lower portions of the 4-bit local input / output bus. In addition, the first dual mode input / output sense amplifier 100 may transmit the amplified 1-bit read data to the lowest second read global input / output bit line RGIO1 <0> or the lower order in response to the compression test control signal TM_COMP. To the second test global input / output bit line (TGIO1 <0>). In fact, when the compression test control signal TM_COMP is disabled (that is, during a normal read operation), the first dual mode input / output sense amplifier 110 may display the amplified read data as the lowest second read global input / output bit line. RGIO1 <0>). In this case, the second lowest test global input / output bit line TGIO1 <0> is not driven by the first dual mode input / output sense amplifier 110. On the contrary, when the compression test control signal TM_COMP is enabled (that is, during the data compression test operation), the first dual mode input / output sense amplifier 110 displays the amplified read data at the second lowest test global input / output bit line. Output to (RGIO1 <0>). In addition, the first dual mode input / output sense amplifier 110 charges the lowest second read global input / output bit line RGIO1 <0> to a high level voltage or a low level voltage. In other words, the first dual mode input / output sense amplifier 110 drives the lowest second test global I / O bit line TGIO1 <0> at the time of the data compression test, and the lowest second lead global I / O bit line. Drive (RGIO1 <0>) to a specific logic voltage (low or high logic voltage).

Like the first dual mode input and output sense amplifier 110, the second and third dual mode input and output sense amplifiers 112 and 114 also have the next higher and negative local input and output bit lines (LIO <2>, LIOB <2>) and the highest positive. And positive and negative bit data on the negative local input / output bit lines LIO <3> and LIOB <3>, respectively. In addition, the second and third input / output sense amplifiers 112 and 114 may output the amplified read data to the lowest third and fourth read global input / output bit lines RGIO2 <0> and RGIO3 in response to the compression test control signal TM_COMP. <0>) or the lowest and second test global I / O bit lines TGIO2 <0> and TGIO3 <0>, respectively. When read data is output to the lowest third and fourth read global I / O bit lines RGIO2 <0> and RGIO3 <0> (that is, during a normal read operation), the third and fourth test global I / O bits of the lowest Lines TGIO2 <0> and TGIO3 <0> are not driven. On the contrary, when the read data is output to the lowest third and fourth test global I / O bit lines TGIO2 <0> and TGIO3 <0> (that is, during the data compression test operation), the second and third dual modes The input / output sense amplifiers 112 and 114 charge the high level voltage or the low level voltage to the lowermost third and fourth lead global input / output bit lines RGIO2 <0> and RGIO3 <0>.

The data compressor 120 performs the lowest first through fourth test global I / O bit lines TGIO0 <0> and TGIO1 <0 only when the compression test control signal TM_COMP is enabled (that is, during data compression test). >, TGIO2 <0>, TGIO3 <0>) compresses 4-bit read data to generate 1-bit compressed data. The compressed data will have a logical value of "0" or "1" depending on whether the logical values of the 4-bit read data are identical. Specifically, if all of the 4-bit read data has the same logical value, the compressed data has a logical value of "1", whereas if any of the 4-bit read data has a different logical value, the compressed data is "0". Will have a logical value. The 1-bit compressed data generated by the data compressor 120 is output toward the data pad (not shown) through the lowest first read global input / output bit line RGIO0 <0>. In other words, the lowest first read global input / output bit line RGIO0 <0> is driven by the data compressor 120 instead of the mono mode input / output sense amplifier 100 during the data compression test.

The lowest first to fourth read global I / O bit lines RGIO0 <0>, RGIO1 <0>, RGIO2 <0>, and RGIO3 <0> are the lowest to first to fourth write global I / O bit lines WGIO0 <0. >, WGIO1 <0>, WGIO2 <0>, WGIO3 <0>). In this form, the read bit lines constituting the read global input / output bus RGIO (for example, 32) are alternated with the write bit lines constituting the write global input / output bus (WGIO) (for example, 32). Are arranged. In addition, the lowest first lead global I / O bit line RGIO0 <0> used as an output channel of the compressed data is disposed at the outermost side so that a signal line other than the write global I / O bit line (WGIO) when shorted to an adjacent line is provided. And short circuit. Accordingly, a short circuit between the read global I / O bit lines RGIO0 <0>, RGIO1 <0>, RGIO2 <0>, RGIO3 <0> cannot occur, and instead, the read global I / O bit lines RGIO0 <0> , RGIO1 <0>, RGIO2 <0>, RGIO3 <0>) and the write global I / O bit lines (WGIO0 <0>, WGIO1 <0>, WGIO2 <0>, WGIO3 <0>) may occur. have. The lowest first lead global I / O bit line RGIO0 <0> used as the output channel of the compressed data is connected to the drivers of five input / output sense amplifiers as shown in FIG. 4 during the data compression test operation. Will be. On the other hand, the remaining second to fourth read global I / O bit lines RGIO1 <0>, RGIO2 <0>, and RGIO3 <0>, which are not used as output channels of the compressed data, are illustrated in FIG. 5. In the data compression test operation, four drivers of the input / output sense amplifiers are connected. 4 and 5 are equivalent circuits created by taking a case where a memory device includes four memory banks as an example. 4 and 5, the lowest first read global input / output bit line RGIO0 <0> and the lowest second, third or fourth read global input / output bit line RGIO1 <0>, RGIO2 <0>, The latches 130 and 132 connected to the RGIO3 <0> have a function of preventing floating of the corresponding read global input / output bit line. However, as these latches 130 and 132, a small size latch may be used to improve the slop of a signal in the corresponding read global I / O bit line.

One of the read global I / O bit lines RGIO0 <0>, RGIO1 <0>, RGIO2 <0>, RGIO3 <0>, which is not used as an output channel of the compressed data, is adjacent to the write global I / O bit line WGIO0 <0. >, WGIO1 <0>, WGIO2 <0>, WGIO3 <0>), the impact is added to the shorted write global I / O bitline by the driver of four input / output sense amplifiers as shown in FIG. To be added. This is because four dual mode input / output sense amplifiers 110, 112, or 114 are driving the shorted lead global input / output bit lines to a specific level voltage. Accordingly, the signal on the shorted write global input / output bit line may be changed so that error data having a logical value different from the original input data may be stored in the memory cell (not shown). In addition, when the channel width of the driver included in the dual mode input / output sense amplifiers 110, 112, and 113 is equal to the channel width of the driver of the data input sense amplifiers 30 to 36, the drivers of the data input sense amplifiers 30 to 36 are used. The effect of the channel width becoming larger than 4 times will occur. As a result, the short state between the read and write global I / O bit lines is detected by the compressed data output through the data compression test data channel (for example, the lowest first read global I / O bit line RGIO0 <0>). Can be.

As such, since a short state of the read and write global I / O buses is detected by the data compression test, the packaging of the defective memory device can be greatly reduced. As a result, a decrease in yield of the memory device can be prevented and unnecessary waste of time and money can be saved.

FIG. 6 is a detailed circuit diagram of the input / output sense amplifier shown in FIG. 3. The mono mode input / output sense amplifier 100 of FIG. 6 is connected between the read global input / output bit line RGIO and the first level voltage source Vdd to form the first transistor MP1, the read global input / output bit line RGIO, and the first input / output bit line RGIO. It is connected between the two-level voltage source Vss and is connected between the second transistor MN1 and the test global input / output bit line TGIO and the first level voltage source Vdd to connect the third transistor MP2 and the test global input / output bit. A fourth transistor MN2 is connected between the line TGIO and the second level voltage source Vss. The first level voltage source Vdd supplies a high potential voltage to the first and third transistors MP1 and MP3, and the first and third transistors MP1 and MP2 have a pull-up function. The second level voltage source Vss supplies the low potential voltage to the second and fourth transistors MN1 and MN3, and the second and fourth transistors MN1 and MN2 have a pull-down function.

The mono mode input / output sense amplifier 100 further includes first and second logic controllers 200 and 210 that complementarily respond to the compression test control signal TM_COMP. The first logic controller 200 generates the positive and negative read data D0 and D0B when the compression test control signal TM_COMP is disabled (that is, during normal operation). Transfer to the gate electrode of MN1). At this time, the second logic controller 210 blocks the positive and negative read data D0 and D0B supplied to the gates of the third and fourth transistors MP2 and MN2. On the contrary, when the compression test control signal TM_COMP is enabled (that is, during the data compression test), the second logic controller 210 may read the positive and negative read data D0 and D0B from the third and fourth transistors MP2 and. Transfer to the gate electrode of MN2). In this case, the first logic controller 200 blocks the positive and negative read data D0 and D0B supplied to the gates of the first and second transistors MP1 and MN1. As a result, the first and second transistors MP1 and MN1 perform the amplification operation of the read data only when the compression test control signal TM_COMP is disabled, while driving when the compression test control signal TM_COMP is enabled. It doesn't work. The third and fourth transistors MP2 and MN2 perform amplification of read data only when the compression test control signal TM_COMP is enabled, but are not driven when the compression test control signal TM_COMP is disabled.

FIG. 7 is a detailed circuit diagram of the dual mode input and output sense amplifier shown in FIG. 3. Referring to FIG. 7, the dual mode input / output sense amplifier 110 is connected between the read global input / output bit line RGIO and the first level voltage source Vdd so that the fifth transistor MP3 and the read global input / output bit line ( Connected between the RGIO and the second level voltage source Vss and connected between the sixth transistor MN31, the test global input / output bit line TGIO and the first level voltage source Vdd, and the seventh transistor MP4. The eighth transistor MN4 is connected between the test global input / output bit line TGIO and the second level voltage source Vss. The first level voltage source Vdd supplies high potential voltages to the fifth and seventh transistors MP3 and MP4, and the fifth and seventh transistors MP3 and MP4 have a pull-up function. The second level voltage source Vss supplies the low potential voltage to the sixth and eighth transistors MN3 and MN4, and the sixth and eighth transistors MN3 and MN4 have a pull-down function.

The dual mode input / output sense amplifier 110 further includes third and fourth logic controllers 300 and 310 that complementarily respond to the compression test control signal TM_COMP. The third logic controller 300 may output the positive and negative read data D0 and D0B when the compression test control signal TM_COMP is disabled (that is, during normal operation). Transfer to the gate electrode of MN3). In this case, the fourth logic controller 310 blocks the positive and negative read data D0 and D0B supplied to the gates of the seventh and eighth transistors MP4 and MN4. On the contrary, when the compression test control signal TM_COMP is enabled (i.e., during the data compression test), the fourth logic controller 310 generates the positive and negative read data D0 and D0B in the seventh and eighth transistors MP4. To the gate electrode of MN4). At this time, the third logic controller 300 blocks the positive and negative read data D0 and D0B supplied to the gate electrodes of the fifth and sixth transistors MP3 and MN3, and instead of blocking the gate electrodes of the sixth transistor MN3. The high potential signal is applied only to cause the sixth transistor MN3 to drive the read global input / output bit line RGIO to a low potential level. As a result, the fifth and sixth transistors MP3 and MN3 perform an amplification operation of read data when the compression test control signal TM_COMP is disabled, and read global input / output when the compression test control signal TM_COMP is enabled. Causes the bit line RGIO to be driven to a low potential level. In contrast, the seventh and eighth transistors MP4 and MN4 perform amplification of read data only when the compression test control signal TM_COMP is enabled, while driving when the compression test control signal TM_COMP is disabled. It doesn't work.

1 is a block diagram schematically illustrating a data storage path of a data compression testable memory device of the related art.

FIG. 2 is a block diagram schematically illustrating a data read path of a data compression testable memory device of the related art. FIG.

3 is a block diagram schematically illustrating a data read path of a data compression testable memory device according to an exemplary embodiment of the inventive concept.

Fig. 4 is an equivalent circuit diagram showing a shared state of an input / output sense amplifier of a representative lead global input / output bit line.

5 is an equivalent circuit diagram illustrating a sharing state of an input / output sense amplifier of a non-representative global input / output bit line.

FIG. 6 is a detailed circuit diagram of the input / output sense amplifier shown in FIG. 3.

FIG. 7 is a detailed circuit diagram of the dual mode input and output sense amplifier shown in FIG. 3.

Explanation of symbols on the main parts of the drawings

100: mono mode input and output sense amplifier

110, 112, 114: first to third dual mode input and output sense amplifier

120: data compressor

130, 132: latch

Claims (3)

A plurality of write global bit lines and a plurality of read global bit lines arranged alternately with each other; Multiple test global bit lines; In response to the compression test control signal, all mode sense amplifiers for selectively amplifying-output any one of the plurality of read data from the memory cell array to any one of the plurality of write global bit lines and the plurality of test global bit lines; Dual mode sense amplifiers selectively amplifying-output the remainder of the plurality of read data from the memory cell array to corresponding read global bit lines and corresponding test global bit lines in response to the compression test control signal; And And in response to the compression test control signal, compressing read data on the test global bit lines to output compressed data through the read global bit line to which the mono mode sense amplifier is connected. Memory device capable of data compression testing. 2. The data compression testable memory device of claim 1, wherein the dual mode sense amplifiers drive a read global bit line at a specific level voltage corresponding to an enable period of a compression test control signal. 2. The data compression testable memory device as recited in claim 1, wherein said lead global bit line coupled to said mono mode sense amplifier is disposed outermost.
KR1020080134983A 2008-12-26 2008-12-26 Memory device capable of data compression test KR20100076812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080134983A KR20100076812A (en) 2008-12-26 2008-12-26 Memory device capable of data compression test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080134983A KR20100076812A (en) 2008-12-26 2008-12-26 Memory device capable of data compression test

Publications (1)

Publication Number Publication Date
KR20100076812A true KR20100076812A (en) 2010-07-06

Family

ID=42638462

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080134983A KR20100076812A (en) 2008-12-26 2008-12-26 Memory device capable of data compression test

Country Status (1)

Country Link
KR (1) KR20100076812A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9824776B1 (en) 2016-05-17 2017-11-21 SK Hynix Inc. Semiconductor memory device and weak cell detection method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9824776B1 (en) 2016-05-17 2017-11-21 SK Hynix Inc. Semiconductor memory device and weak cell detection method thereof
KR20170129386A (en) * 2016-05-17 2017-11-27 에스케이하이닉스 주식회사 Semiconductor memory device and weak cell detection method thereof

Similar Documents

Publication Publication Date Title
KR100689011B1 (en) Semiconductor integrated circuit
US6650582B2 (en) Semiconductor memory device
US7586804B2 (en) Memory core, memory device including a memory core, and method thereof testing a memory core
KR100930384B1 (en) Input / output line detection amplifier and semiconductor memory device using same
US6400623B2 (en) Semiconductor memory having parallel test mode
US7085171B2 (en) Semiconductor memory device
US6504784B1 (en) Semiconductor memory device with reduced standby current
US6859409B2 (en) Semiconductor memory having sense amplifier architecture
KR100866136B1 (en) Semiconductor memory device
JP3830692B2 (en) Semiconductor memory device
US8248835B2 (en) Semiconductor memory and test method for the semiconductor memory
US20070070740A1 (en) Semiconductor memory device having data-compress test mode
KR20100076812A (en) Memory device capable of data compression test
KR20120087831A (en) Semiconductor memory device comprising compress parallel test circuit
JP5527957B2 (en) Semiconductor memory device and control method thereof
KR100699827B1 (en) Memory module
US8289794B2 (en) Integrated circuit
JP5442562B2 (en) Semiconductor memory device
US10964404B2 (en) Semiconductor device
US6975548B2 (en) Memory device having redundant memory cell
US20020036932A1 (en) Semiconductor memory device and method of repairing same
JPH07201199A (en) Semiconductor integrated circuit
US9013937B2 (en) Semiconductor device, method for inspecting the same, and method for driving the same
KR20060031393A (en) Semiconductor memory device
KR20120042578A (en) Test circuit of semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination