KR20100076323A - Gate pattern for nonvolatile memory device and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A gate pattern of a non-volatile memory device and a formation method are provided to prevent voids from moving toward a dielectric film by maximizing the size of a grain of a first polysilicon layer contacting with the dielectric film. CONSTITUTION: Conductive films(105,119) are formed on the top of a semiconductor substrate(101) between tunnel insulating layers(103). A dielectric film(117) is formed on the top of the conductive film. A first polysilicon layer(119a) is formed on the top of the dielectric film. A second polysilicon layer(119b) is formed on the top of the first polysilicon layer. The second polysilicon layer comprises grains smaller than the first polysilicon layer.

Description

Gate pattern for nonvolatile memory device and its formation method {Gate pattern for nonvolatile memory device and manufacturing method of the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate pattern of a nonvolatile memory device and a method of forming the same. In particular, a gate pattern of a nonvolatile memory device capable of improving a program threshold voltage distribution characteristic by improving a phenomenon in which voids move toward a dielectric film and forming the same. It is about a method.

The cell array of the nonvolatile memory device is formed of a string structure including a drain select transistor, a source select transistor, and a plurality of memory cells connected in series between the drain select transistor and the source select transistor. Each string structure is electrically isolated with an isolation layer therebetween. Each of the memory cells includes a stacked gate pattern in which a floating gate, a dielectric layer, and a control gate are stacked.

The above-described floating gate is formed to be separated from each other with the device isolation layer interposed therebetween, and the control gate is connected in a direction crossing the device isolation layer so as to be formed on the device isolation layers as well as on top of the plurality of floating gates. On the other hand, the device isolation layer is formed lower than the height of the floating gate, the control gate is formed to fill the space between the floating gates. Recently, as semiconductor devices have been highly integrated, as the aspect ratio of the space defined between the floating gates increases, it is difficult to gap-fill the space defined between the floating gates using the conductive film for the control gate. That is, as semiconductor devices become highly integrated, a phenomenon occurs in which a seam is generated in the control film conductive film during deposition of the control film conductive film. The shim generated in the control film conductive film is converted into a void in a subsequent thermal process and moves along the grain boundary of the control film conductive film. Voids moving along the grain boundary of the control gate conductive film become a problem because they penetrate the dielectric film and degrade the threshold voltage distribution characteristic of the nonvolatile memory device.

The present invention provides a gate pattern of a nonvolatile memory device and a method of forming the same, which can improve a program threshold voltage distribution characteristic by improving a phenomenon in which voids move toward a dielectric film.

The gate pattern of the nonvolatile memory device according to the present invention includes conductive films formed on the semiconductor substrate with a tunnel insulating film interposed therebetween, a dielectric film formed on the conductive film, a first polysilicon film formed on the dielectric film, and a first pattern. A second polysilicon film is formed on the polysilicon film and is thicker than the first polysilicon film and includes grains smaller than the first polysilicon film.

The upper width of the conductive film may be narrower than the lower width of the conductive film.

A method of forming a gate pattern of a nonvolatile memory device according to the present invention includes providing a semiconductor substrate in which a device isolation layer is formed in an isolation region, and a tunnel insulating layer and a conductive layer are stacked on an active region defined between the isolation layers. Forming a dielectric film on the surfaces of the separator and the conductive film, forming a first polysilicon film on top of the dielectric film, and grains thicker than the first polysilicon film and smaller than the first polysilicon film on top of the first polysilicon film A second polysilicon film is formed.

Forming the first polysilicon film includes forming an amorphous silicon film on top of the dielectric film, and annealing the amorphous silicon film at a temperature of 600 ° C to 700 ° C for 4 to 6 hours.

Forming the amorphous silicon film is carried out at a temperature of 450 ℃ to 500 ℃ using SiH ₂ H ₆ gas.

The first polysilicon film includes grains having a size of 1 μm to 2 μm.

The first polysilicon film is formed to a thickness of 150 kPa to 200 kPa.

Prior to forming the dielectric film, etching the device isolation film to expose the sidewalls of the conductive film, oxidizing the surface of the conductive film to form an oxide film, removing the oxide film, and controlling the EFH of the device isolation film are further performed. .

According to the present invention, by maximizing the grain size of the first polysilicon film in contact with the dielectric film, voids generated after forming the first polysilicon film may be moved toward the dielectric film through the grain boundary of the first polysilicon film. Therefore, the present invention can improve the program threshold voltage distribution characteristic of the nonvolatile memory device.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention can be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

1A to 1G are cross-sectional views illustrating a method of forming a gate pattern of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a trench 109 is formed by a conventional manufacturing method of a nonvolatile memory device, and the tunnel insulating film 103 and the first conductive film 105 are formed on an active region defined by the trench 109. This stacked semiconductor substrate 101 is provided.

In more detail, the semiconductor substrate 101 is divided into a cell region A in which a plurality of memory cells are to be formed and a select transistor region B in which select transistors are to be formed with the cell region A therebetween. The tunnel insulating layer 103, the first conductive layer 105, and the device isolation hard mask pattern 107 are sequentially formed on the semiconductor substrate 101. Subsequently, the first conductive layer 105, the tunnel insulating layer 103, and the semiconductor substrate 101 are etched by an etching process using the device isolation hard mask pattern 107 as an etching barrier to form a trench 109 in the semiconductor substrate 101. ) Is formed. The formation of the trench 109 defines the active region of the semiconductor substrate 101, and the tunnel insulating layer 103 and the first conductive layer 105 remain on the active region. The first conductive film 105 and the tunnel insulating film 103 are patterned in a direction parallel to the trench 109.

The tunnel insulating film 103 may be formed by forming an oxide film using a radical oxidation process. In addition, in order to improve the film quality of the tunnel insulating film 103, after forming an oxide film using a radical oxidation process, an annealing process using N ₂ O or NO gas may be performed. The first conductive layer 105 is used as a floating gate of the nonvolatile memory device and may be formed using a polysilicon layer. In addition, an impurity such as phosphorus (P) is doped into the polysilicon film used as the first conductive film 105. At this time, the first conductive film 105 may be undoped with the polysilicon film 105a and the impurity concentration at the interface between the first conductive film 105 and the tunnel insulating film 103 to improve the characteristics of the nonvolatile memory device. The doped polysilicon film 105b may be formed in a stacked structure.

Referring to FIG. 1B, after the insulating film is formed to a sufficient thickness to fill the trench (109 of FIG. 1A), the surface of the insulating film is planarized to form the device isolation film 113 having the first height h1. The process of planarizing the surface of the insulating film may be performed until the first conductive film 105 is exposed by using a chemical mechanical polishing (CMP) method. The device isolation hard mask pattern on the first conductive layer 105 is removed through a planarization process that is stopped when the first conductive layer 105 is exposed.

Meanwhile, before depositing an insulating film for forming the device isolation layer 113, a sidewall oxidation process and a liner insulating film forming process may be further performed. Through the sidewall oxidation process and the liner insulating film forming process, the sidewall oxide film and the liner insulating film 113 may be formed on the surface of the trench (109 of FIG. 1A). The sidewall oxidation process is performed to remove damage generated during the etching process of forming the trench (109 of FIG. 1A), and may be performed using a radical oxidation method. The liner insulating film forming process serves to prevent impurities generated in subsequent processes from penetrating into the structure under the liner insulating film. The liner insulating film is formed to have a thickness of 150 kPa to 250 kPa to sufficiently protect the tunnel insulating film 103 and the first conductive film 105 at 500 ° C to 700 ° C using TEOS (Tetra Ethyl Ortho Silicate) gas.

The width of the first conductive film 105 formed through the above process is defined as a first width W1.

The device isolation layer 113 may be formed using a PSZ (Poly Silazane) film having excellent gap-fill characteristics. That is, the device isolation layer 113 may be formed by coating the PSZ film by spin coating and then planarizing the surface of the PSZ film. When the PSZ film is coated, the thickness is preferably 3000 kPa to 6000 kPa. On the other hand, a curing process for removing impurities in the PSZ film is performed before the planarization process. The curing process may be divided into a first curing process and a second curing process to increase the etching rate of the PSZ film. The primary curing process of the PSZ film may be performed at 300 ° C. to 400 ° C. using a c-WVG (Catalythic Water Vapor Generator) method. The secondary curing process of the PSZ film is O ₂ at 400 ℃ to 500 ℃ It can be performed by an annealing process using only gas. In addition, after the curing process of the PSZ film, in order to more quickly remove impurities in the PSZ film, the semiconductor substrate 101 including the PSZ film is loaded at 100 ° C to 200 ° C and annealed at 500 ° C to 700 ° C for 1 to 2 hours. The process can be carried out further. After the curing process and annealing process of such a PSZ film, the PSZ film is planarized.

Referring to FIG. 1C, the device isolation layer 111 is etched. In this case, the peripheral region (not shown) formed outside the cell region A and the select transistor region B may be blocked and protected by the photoresist pattern.

In the above-described etching process of the device isolation layer 111, the height of the device isolation layer 111 becomes a second height h2 lower than the first height, and the sidewall of the first conductive layer 105 is exposed. Thereafter, the exposed surface of the first conductive film 105 is oxidized to form an oxide film 115 on the surface of the first conductive film 105. The process of oxidizing the surface of the first conductive film 105 may be performed using a plasma method.

The process of oxidizing the surface of the first conductive film 105 prevents a smiling phenomenon in which the oxidation proceeds from the sidewalls of the tunnel insulating film 103 and the sidewalls of the tunnel insulating film 103 are thickened. The surface of the first conductive film 105 must proceed to be sufficiently oxidized. For this purpose, the thickness of the oxide film 115 formed by oxidizing the surface of the first conductive film 105 is preferably 150 kPa to 100 kPa. In addition, the process of oxidizing the surface of the first conductive film 105 uses a plasma formed at a temperature of 350 ° C to 600 ° C, a pressure of 1torr to 5torr, and a power of 3000W to 5000W to minimize thermal budget. It is preferable to carry out.

Referring to FIG. 1D, the oxide film (115 of FIG. 1C) formed on the surface of the first conductive film 105 is removed to expose the first conductive film 105. Removal of the oxide film (FIG. 1C 115) can be performed using a dry cleaning process. At this time, the upper width of the first conductive film 105 is the second width W2 narrower than the first width. Therefore, the upper width of the first conductive film 105 is narrower than the lower width of the first conductive film 105, so that the upper interval between the first conductive films 105 is widened.

Thereafter, the height of the device isolation layer 113 is lowered to adjust the effective field oxide height (EFH). Through the adjustment of the EFH, the height of the device isolation layer 113 becomes a third height h3 lower than the second height. Meanwhile, in order to prevent deterioration of cycling characteristics of the nonvolatile memory device, it is preferable that the height of the device isolation layer 113 is not lower than that of the tunnel insulating layer 103 during the EFH adjustment.

After EFH adjustment, remove the photoresist pattern blocking the peripheral area.

Referring to FIG. 1E, a dielectric film 117 is formed on the surfaces of the first conductive films 105 and the surface of the device isolation layer 113. At this time, the dielectric film 117 is deposited after the upper gap between the first conductive films 105 is widened. Accordingly, the dielectric layers 117 formed on the sidewalls of the first conductive layers 105 may be formed to be spaced apart from each other without filling the space between the first conductive layers 105. The dielectric film 117 may have a stacked structure of an oxide film 117a, a nitride film 117b, and an oxide film 117c.

Referring to FIG. 1F, a second conductive layer 119 is formed on the dielectric layer 117. The second conductive film 119 includes a first polysilicon film 119a and a second polysilicon film 119b thicker than the first polysilicon film 119a.

The first polysilicon film 119a is a film in contact with the dielectric film 117a. The first polysilicon film 119a lowers the aspect ratio of the space defined between the first conductive films 105 and also voids the first polysilicon film 119a itself. It is preferable to form a thin thickness so that no void or seam is formed. In more detail, the first polysilicon film 119a is preferably formed to a thickness of 150 kPa to 200 kPa.

In addition, the grain size of the first polysilicon film 119a may be such that voids that may occur in a subsequent process may move to the dielectric film 117a along the grain boundary of the first polysilicon film 119a to minimize the phenomenon. It is preferable to form larger than the grain size of the silicon film 117b. The first polysilicon film 119a may be formed by depositing amorphous silicon at a temperature of 450 ° C. to 500 ° C. using SiH ₂ H ₆ gas, and then performing an annealing process. At this time, the annealing process is preferably performed for 4 hours to 6 hours at a temperature of 600 ℃ to 700 ℃ to maximize the grain size of the first poly silicon film 119a. Through the above-described process, the grain size of the first polysilicon 119a may be secured to 1 μm to 2 μm. In addition, since the temperature of the annealing process is low at 600 ° C to 700 ° C when forming the first polysilicon film 119a, the roughness of the surface of the first polysilicon film 119a may be uniformized. Accordingly, the deposition of the second polysilicon film 119b formed on the first polysilicon film 119a may be uniformly performed.

As such, when the grain size of the first polysilicon layer 119a is maximized, a path through which voids may move in the first polysilicon layer 119a is reduced, so that the voids are formed along the grain boundary of the first polysilicon layer 119a. Penetration into the film 117a can be minimized.

The second polysilicon film 119b is formed on the first polysilicon film 119a, is thicker than the first polysilicon film 119a, and includes smaller grains than the first polysilicon film 119a. . In addition, the second polysilicon film 119b is formed by filling gaps between the first conductive films 105. In this case, the second polysilicon layer 119b may be formed in the space between the first conductive layers 105 so that the dielectric layers 117 formed on the sidewalls of the adjacent first conductive layers 105 may be spaced apart from each other. This is because the gap between the upper portions of the first conductive layers 105 is enlarged.

Meanwhile, since the aspect ratio of the space defined between the first conductive films 105 is improved by controlling the thickness of the first polysilicon 119a, a phenomenon in which seams are generated when the second polysilicon film 119b is formed may be reduced. . In addition, a seam may be generated in the second polysilicon film 119b, and the seam may be converted into a void by heat generated in a subsequent process to move along the grain boundaries of the first and second polysilicon films 119a and 119b. At this time, since the grain size of the first polysilicon film 119a is maximized by c, the movement path of the voids in the first polysilicon film 119a is reduced, so that the dielectric material is formed through the grain boundary of the first polysilicon film 119a. The voids that penetrate the membrane 117 can be reduced.

The second conductive film 119 described above may be used as a capping film to protect the dielectric film 117 formed in the cell region A from being damaged during the formation of contact holes in the dielectric film 117 in a subsequent process. Can be. In addition, the second conductive film 119 used as the capping film is used as a lower conductive film of the conductive film for the control gate.

As described above, the second conductive film 119 used as the conductive film for the control gate and formed in the space between the first conductive films 105 may secure the coupling ratio between the floating gate and the control gate.

Referring to FIG. 1G, an etching barrier pattern (not shown) such as a photoresist pattern is formed on the second conductive layer 119 to etch the second conductive layer 119 and the dielectric layer 117. As a result, a contact hole for exposing the first conductive film 105 formed in the select transistor region B is formed in the dielectric film 117. Thereafter, the etch barrier pattern is removed to form the third conductive layer 121. In the select transistor region B, the third conductive layer 121 is connected to the first conductive layer 105 through a contact hole formed in the dielectric layer 117.

The third conductive film 121 may be formed using a metal silicide film or a metal film as the control film for the control gate.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A to 1G are cross-sectional views illustrating a gate pattern forming method of a nonvolatile memory device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101 semiconductor substrate 103 tunnel insulating film

105: first conductive film 107: device isolation hard mask pattern

109: trench 113: device isolation film

115: oxide film 117: dielectric film

119a: first polysilicon film 119b: second polysilicon film

119: second conductive film 121: third conductive film

Claims (10)

Conductive films formed over the semiconductor substrate with the tunnel insulating film interposed therebetween; A dielectric film formed over the conductive film; A first polysilicon film formed on the dielectric film; And The gate pattern of the nonvolatile memory device including a second polysilicon layer formed on the first polysilicon layer and thicker than the first polysilicon layer and including grains smaller than the first polysilicon layer. The method of claim 1, The first polysilicon layer includes grains having a size of about 1 μm to about 2 μm. The method of claim 1, The first polysilicon layer is a gate pattern of a nonvolatile memory device formed to a thickness of 150 ~ 200Å. The method of claim 1, The upper width of the conductive layer is narrower than the lower width of the conductive layer gate pattern of the memory device. Forming a device isolation film in the device isolation region, and providing a semiconductor substrate having a tunnel insulating film and a conductive film stacked on an active region defined between the device isolation films; Forming a dielectric film on surfaces of the device isolation film and the conductive film; Forming a first polysilicon film on the dielectric film; And And forming a second polysilicon layer on the first polysilicon layer, the second polysilicon layer including grains thicker than the first polysilicon layer and smaller than the first polysilicon layer. The method of claim 5, Forming the first polysilicon film Forming an amorphous silicon film on the dielectric film; And And annealing the amorphous silicon film at a temperature of 600 ° C. to 700 ° C. for 4 hours to 6 hours. The method of claim 6, The forming of the amorphous silicon film is a method of forming a gate pattern of a nonvolatile memory device using a SiH ₂ H ₆ gas at a temperature of 450 ℃ to 500 ℃. The method of claim 5, The first polysilicon layer includes grains having a size of about 1 μm to about 2 μm. The method of claim 5, The first polysilicon film is a gate pattern forming method of a nonvolatile memory device formed to a thickness of 150 ~ 200Å. The method of claim 5, Before forming the dielectric film, Etching the device isolation layer to expose sidewalls of the conductive layer; Oxidizing a surface of the conductive film to form an oxide film; Removing the oxide film; And controlling the EFH of the device isolation layer.

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