KR101050454B1 - Device Separation Film of Semiconductor Device and Formation Method Thereof - Google Patents

Device Separation Film of Semiconductor Device and Formation Method Thereof Download PDF

Info

Publication number
KR101050454B1
KR101050454B1 KR20070066132A KR20070066132A KR101050454B1 KR 101050454 B1 KR101050454 B1 KR 101050454B1 KR 20070066132 A KR20070066132 A KR 20070066132A KR 20070066132 A KR20070066132 A KR 20070066132A KR 101050454 B1 KR101050454 B1 KR 101050454B1
Authority
KR
South Korea
Prior art keywords
film
formed
insulating film
trench
insulating
Prior art date
Application number
KR20070066132A
Other languages
Korean (ko)
Other versions
KR20090002624A (en
Inventor
양해창
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR20070066132A priority Critical patent/KR101050454B1/en
Publication of KR20090002624A publication Critical patent/KR20090002624A/en
Application granted granted Critical
Publication of KR101050454B1 publication Critical patent/KR101050454B1/en

Links

Images

Abstract

The present invention is to provide a non-volatile memory device and a method of manufacturing the same that can ensure the uniformity of the threshold voltage by minimizing the non-uniformity of the effective field oxide height (EFH) in the entire wafer area, for this purpose A substrate having a silver trench, a first insulating film formed along an inner side wall of the trench to partially fill the trench, a second insulating film formed on the first insulating film to partially fill the trench by spin coating, and an upper portion of the second insulating film And a third insulating film formed on the protective film so as to fill the trench, and a protective film formed in a liner shape along the side surface of the first insulating film.
Nonvolatile Memory Devices, NAND Flash Memory Devices, Device Separators

Description

Device isolation film of semiconductor device and its formation method {AN ISOLATION LAYER IN SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and manufacturing techniques, and more particularly, to a nonvolatile memory device and a manufacturing method thereof.

NAND type flash memory devices, which are nonvolatile memory devices, form a unit string by connecting a plurality of cells in series for high integration, and are mainly a memory stick and a USB driver (Universal Serial Bus). As a device that can replace a driver and a hard disk, the application field is expanding.

Currently, in the method of manufacturing a NAND flash memory device, the floating gate forming method adopts an ASA-STI (Advanced Self Aligned Shallow Trench Isolation) process according to a decrease in an overlay margin between an active region and a floating gate. Doing.

1A to 1G are cross-sectional views illustrating the ASA-STI process according to the prior art.

First, as shown in FIG. 1A, a tunneling insulating film 101 and a floating gate conductive film (not shown) are formed on a substrate 100 and then etched to form trenches 103.

Subsequently, as shown in FIG. 1B, the liner isolation film HDP (High Density Plasma) film 104 is formed along the inner wall to partially fill the trench 103 (see FIG. 1A), and then the trench ( A SOD (Spin On Dielectric) film 105 is formed to fill the 103.

Subsequently, as shown in FIG. 1C, the SOD film 105A is recessed to a predetermined depth.

Next, as shown in FIG. 1D, in FIG. 1C, the HDP film 106 is formed on the substrate 100 so that all the grooves in the trench formed as the SOD film 105A is retracted are filled.

Subsequently, as shown in Fig. 1E, the HDP films 104A and 106A are planarized.

Subsequently, as shown in FIG. 1F, the HDP films 104B and 106B are retracted to a predetermined depth in order to adjust the effective field oxide height (EFH) of the device isolation film. Here, EFH means the distance from the surface of the active region defined by the device isolation film to the dielectric film.

Subsequently, as illustrated in FIG. 1G, the dielectric film 107 is formed along the stepped surface above the substrate 100.

Subsequently, the control gate 108 is formed on the dielectric film 107.

However, the ASA-STI process according to the prior art has the following problems.

As described above, the ASA-STI process has a higher aspect ratio than the Self Aligned-STI (SA-STI) process. For this reason, the device isolation film is not formed as a single HDP film as in the SA-STI process, but is formed as a laminated structure in which the HDP film-SOD film-HDP film is laminated. In other words, it is possible to easily control the process during the polishing process and the etching process for the subsequent EFH control by final landfilling using HDP film having higher hardness than SOD film while using the SOD film having excellent embedding characteristics. To achieve the effect that can be.

However, in the etching process for controlling the EFH described in FIG. 1F, the EFH is not uniformly controlled but uniformly controlled in the entire region of the wafer. The reason is because of the polishing nonuniformity depending on the pattern density. Accordingly, depending on the region, the HDP film 106B is controlled to be low, so that the SOD film 105A formed at the bottom thereof is exposed to the etching process. The SOD film 105A is etched at the time of exposure because the etch rate is significantly higher than that of the HDP film 106B. This causes a problem that voids are generated between the HDP films 104B and 106B.

FIG. 2A is a plan view illustrating a device isolation region after an etching process for controlling EFH, and FIG. 2B is a cross-sectional view. 3 is an enlarged cross-sectional view of the cross-sectional view shown in FIG.

Referring to FIGS. 2 and 3, it can be seen that the SOD film is unevenly controlled according to the region after the etching process for controlling EFH, and in particular, the etching process for controlling the EFH of the SOD film, such as the 'A' region shown in FIG. 3. It can be seen that the voids are generated at the site when exposed to the.

As described above, a problem caused by the loss of the SOD film is that it causes a punch through phenomenon of the dielectric film interposed between neighboring floating gates. That is, due to the loss of the SOD film, the dielectric film is destroyed in the region where the EFH is controlled to be low, and an electrical short circuit occurs in which the control gate and the substrate are directly connected. When the control gate and the substrate are electrically shorted, a leakage current is generated in this region, and this leakage current prevents a stable writing or erasing operation of the device, which eventually causes the device to fail and discard, thereby resulting in a yield of the device. This deterioration problem occurs.

Therefore, the present invention has been proposed to solve the problems of the prior art, and has the following objects.

First, an object of the present invention is to provide a device isolation film of a semiconductor device and a method for forming the same, which can secure uniformity of threshold voltage by minimizing non-uniformity of EFH in the entire wafer area.

Second, another object of the present invention is to provide a device isolation film of a semiconductor device and a method of forming the same, which can prevent the punch-through phenomenon of the dielectric film due to the reduction of the EFH in the cell region.

According to an aspect of the present invention, there is provided a substrate in which a trench is formed, a first insulating film formed along an inner side wall of the trench to partially fill the trench, and the first trench to partially fill the trench by spin coating. A semiconductor including a second insulating film formed on the insulating film, a protective film formed on the second insulating film, a liner-shaped protective film formed along the side surface of the first insulating film, and a third insulating film formed on the protective film so that the trench is buried. The device isolation film of the device is provided.

In addition, according to another aspect of the present invention, there is provided a method of forming a tunneling insulating film and a floating gate conductive film on a substrate, and partially etching the conductive film for the floating gate, the tunneling insulating film, and the substrate. Forming a trench; forming a first insulating film for device isolation film along an inner wall to partially fill the trench; and forming a second insulating film for device isolation film on the first insulating film so that the trench is partially filled. Forming a protective film in the form of a liner along the sidewalls of the first insulating film, and forming a third insulating film for the isolation layer on the protective film so that the trench is buried. It provides a device isolation film forming method of a semiconductor device comprising.

As described above, according to the present invention, the following effects can be obtained.

First, according to the present invention, by forming a protective film on the spin coating film constituting the device isolation film to protect the SOD film from the etching process for subsequent EFH control by suppressing the generation of voids in the device isolation film caused by the loss of the SOD film Fail can be prevented, thereby improving the yield of the device. In addition, the uniformity of the threshold voltage can be secured by minimizing the non-uniformity of the EFH in the entire wafer due to the SOD film loss, and the punch-through phenomenon of the dielectric film due to the reduction of the EFH in the cell region can be prevented.

Second, according to the present invention, by forming a passivation layer as a conductive layer in the device isolation layer, the parasitic capacitance between neighboring memory cells (floating gate) can be minimized, thereby minimizing the interference effect between the memory cells, and thereby the threshold voltage distribution. Can be improved.

In addition, in the nonvolatile memory device according to the related art, only an isolation layer exists between neighboring floating gates, but in the nonvolatile memory device according to an exemplary embodiment of the present invention, a conductive film is interposed between the floating gate and the device isolation layer. As a result, the parasitic capacitance between the floating gates can be reduced as compared with the prior art.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process.

Example

4 is a cross-sectional view illustrating a device isolation layer of a semiconductor device in accordance with an embodiment of the present invention. Here, a nonvolatile memory device is illustrated for convenience of description.

Referring to FIG. 4, in the nonvolatile memory device according to the embodiment of the present invention, the device isolation layer may include first to third insulating layers 205B, 206A, and 208B, and second and third insulating layers 206A and 208B. A protective film 207B is formed further to protect the second insulating film 206A therebetween.

The passivation layer 207B is made of a heterogeneous material having a high etching selectivity with the third insulating layer 208B. For example, when the third insulating film 208B is formed of an oxide film, it is formed of a nitride film. More specifically, when the third insulating film 208B is formed of an HDP film, it is formed of a silicon nitride film (Si 3 N 4 ). However, the present invention is not limited thereto, and the passivation layer 207B may use both the third insulating layer 208B and a material having a high etching selectivity. For example, it may be formed of a polycrystalline silicon film, a transition metal, a rare earth metal or an alloy film thereof. In this case, an effect that also prevents the interference effect between the floating gates 202 may be obtained.

Hereinafter, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention shown in FIG. 4 will be described.

5A through 5G are cross-sectional views illustrating manufacturing processes in order to explain a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention. As an example, a method of manufacturing a NAND flash memory device using the ASA-STI process will be described.

First, as shown in FIG. 5A, triple n-type wells (not shown) and p-type wells (not shown) in a semiconductor substrate 200, such as a p-type substrate, are shown. To form.

Subsequently, an ion implantation process for adjusting the threshold voltage is performed in the channel region in the p-well.

Subsequently, a tunneling insulating layer 201 in which FN tunneling (Fouler-Nordheim Tunneling) occurs is formed on the substrate 200. At this time, the tunneling insulation film 201 is an oxide film, a silicon oxide film (SiO 2) after forming, or forming a silicon oxide film (SiO 2) of nitrogen, for example by carrying out the heat treatment process using a N 2 gas of silicon oxide (SiO 2) A nitride layer may be formed at the interface between the substrate 200 and the substrate 200. In addition, it may be formed of a high dielectric film having a dielectric constant of 3.9 or more, such as a metal oxide such as an aluminum oxide film (Al 2 O 3 ), a hafnium oxide film (HfO 2 ), or a zirconium oxide film (ZrO 2 ). The tunneling insulating film 201 may be formed to a thickness of about 50 ~ 100Å.

For example, when the tunneling insulating film 201 is formed of a silicon oxide film, the manufacturing method may be a dry oxidation, a wet oxidation process or an oxidation process using radical ions. It is preferable to carry out dry oxidation or wet oxidation instead of the oxidation process using radical ions. On the other hand, the heat treatment process using nitrogen gas can be carried out using a furnace (furnace) equipment.

Subsequently, a conductive film 202 (hereinafter referred to as a first conductive film) is formed on the tunneling insulating film 201 as a floating gate. In this case, the first conductive layer 202 may be made of any material having conductivity, and may be formed of any one material selected from polycrystalline silicon, a transition metal, and a rare earth metal. For example, the polysilicon film may be an un-doped polysilicon film that is not doped with impurity ions or a doped polysilicon film that is doped with impurity ions, and is used for an undoped polysilicon film. Impurity ions are implanted separately through a subsequent ion implantation process. The polysilicon film is formed by Low Pressure Chemical Vapor Deposition (LPCVD), wherein a silane (SiH 4 ) gas is used as a source gas, and phosphine (PH 3 ), 3 is used as a doping gas. Fluorine chloride (BCl 3 ) or giborane (B 2 H 6 ) gas is used. As the transition metal, iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo) or titanium (Ti) and the like are used. Erbium (Er), Ytterium (Yb), Samarium (Sm), Yttrium (Y), Lanthanum (La), Cerium (Ce), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), and Tolium ( Tm), lutetium (Lu) and the like.

Subsequently, a buffer film (not shown) may be formed on the first conductive film 202, wherein the buffer film (not shown) is formed during the deposition and removal of the hard mask 203 to be formed through a subsequent process. 1 is formed to prevent damage to the conductive film 202, and is preferably formed of a material having a high etching selectivity with the hard mask 203. For example, when the hard mask 203 is formed of a nitride film, for example, a silicon nitride film (Si 3 N 4 ), the hard mask 203 is formed of a silicon oxide film (SiO 2 ).

Subsequently, a hard mask 203 may be formed on the buffer film. In this case, the hard mask 203 is to compensate for the lack of thickness of the photoresist pattern (not shown) to be formed through a subsequent process, and when the buffer layer is not formed, a material having a high etching selectivity with the first conductive layer 202. To form. For example, when the first conductive film 202 is formed of a polycrystalline silicon film, the first conductive film 202 is formed of a silicon nitride film (Si 3 N 4 ). The hard mask 203 is formed by LPCVD to minimize stress during the deposition process, and the nitrogen (N 2 ) flow rate is 40 to 60 cc at a temperature of 700 to 800 ° C. and a pressure of 0.3 to 0.4 Torr. DCS (Diclorosilane, SiCl 2 H 2 ) flow rate is set to 800 ~ 1000cc, ammonia (NH 3 ) flow rate is formed to 800 ~ 1000cc.

Subsequently, the hard mask 203, the first conductive layer 202, the tunneling insulating layer 201, and the substrate 200 are partially etched to form trenches 204 having a predetermined depth inside the substrate 200. In this case, the trench 204 may be formed in a line type in the case of a NAND flash memory device.

Subsequently, as shown in FIG. 5B, the first insulating layer 205 for the device isolation layer is deposited through the deposition process along the inner wall such that the trench 204 (see FIG. 5A) is partially filled. In this case, the first insulating layer 205 is deposited in a liner type in which the bottom portion is thicker than the inner wall. The first insulating film 205 can be formed of an HDP film having excellent embedding characteristics even at a high aspect ratio.

Subsequently, a second insulating film 206 for spacers is deposited on the first insulating film 205 so that the trench 204 (see FIG. 5A) is completely filled. In this case, the second insulating film 206 is formed of an SOD film which is a spin coating film having excellent embedding characteristics. For example, a PSZ (polisilazane ) film is used as the SOD film.

On the other hand, when the second insulating film 206 is formed of an SOD film, a bake process for curing the SOD film may be performed. At this time, the baking process can be carried out at 600 ~ 900 ℃.

Subsequently, as shown in FIG. 5C, the second insulating film 206A is retracted to a predetermined depth. In this case, the second insulating film 206A may be retracted to the lower portion of the tunneling insulating film 201. In addition, the step of retracting the second insulating film 206A may be performed by a dry etching method or a wet etching method.

Subsequently, as shown in FIG. 5D, the passivation layer 207 is formed along the space formed as the second insulation layer 206A is retracted in FIG. 5C, that is, the upper stepped surface of the first insulation layer 205. At this time, the protective film 207 is also formed on the second insulating film 206A. The protective film 207 is formed of a nitride film that can function as an etch stopper to protect the second insulating film 206A from the etching solution (or etching gas) for the oxide film used in the etching process for subsequent EFH control. desirable. In addition, the conductive film may be formed of any one selected from a conductive film such as a polysilicon film, a transition metal, a rare earth metal, or an alloy film containing these.

Subsequently, as shown in FIG. 5E, a third insulating film 208 for device isolation film is formed on the protective film 207 so that the trench 204 (see FIG. 5A) is completely filled. In this case, the third insulating layer 208 is formed of a material having an etching selectivity with the protective layer 207. For example, the same HDP film as the first insulating film 205 is formed.

Subsequently, as shown in FIG. 5F, the first and third insulating films 205A and 208A and the protective film 207A are subjected to planarization, for example, chemical mechanical polishing (hereinafter referred to as CMP). do. At this time, the CMP process is performed using an oxide film polishing slurry as the polishing mask for the hard mask 203. Further, the hard mask 203 may be polished to a predetermined thickness by performing an excessive polishing process so that the first and third insulating films 205A and 208A do not remain on the hard mask 203.

Then, as shown in FIG. 5G, the hard mask 203 (see FIG. 5F) is removed. In this case, the hard mask 203 may be removed using phosphoric acid (H 3 PO 4 ).

Subsequently, the first and third insulating films 205B and 208B and the protective film 207B are retracted to a predetermined depth. At this time, the depth to be retracted may be appropriately selected in consideration of the coupling ratio (EFH) and the coupling ratio (coupling ratio) of the device, for example, to retreat to about 1/2 of the height of the first conductive film 202. In addition, the etching process for retreating may be both dry etching and wet etching. In the dry etching method, the selectivity of the first conductive layer 202 is high, and the etching selectivity between the first and third insulating layers 205B and 208B and the passivation layer 207B is performed under a low etching condition. For example, a mixed gas in which CF 4 and H 2 are mixed is used. In the wet etching method, when the first and third insulating layers 205B and 208B and the protective layer 207B are simultaneously etched, it is difficult to control the etch selectivity. The first and third insulating layers 205B and 208B are first etched. The protective film 207B may be etched or the protective film 207B may be etched first, followed by the first and third insulating films 205B and 208B.

Meanwhile, although the retreat process is performed after removing the hard mask 203, the hard mask 203 may be removed after the retreat process using the hard mask 203 as an etching barrier layer. In this case, the first conductive film 202 may be exposed to the etching process and damaged during the retreat process through the hard mask 203.

Subsequently, as shown in FIG. 5H, the dielectric film 209 is formed along the stepped surface above the substrate 200. In this case, the dielectric film 209 is formed in a stacked structure of an oxide film-nitride film-oxide film, or a metal oxide layer having a dielectric constant of 3.9 or higher than a silicon oxide film (SiO 2 ), for example, an aluminum oxide film (Al 2 O 3 ) or a zirconium oxide film (ZrO). 2 ) or a hafnium oxide film (HfO 2 ), or a mixed film or a laminated film thereof.

Subsequently, a control gate conductive film 210 (hereinafter referred to as a second conductive film) is formed on the dielectric film 209. In this case, the second conductive film 210 may be formed of the same material as the first conductive film 202.

Subsequently, a metal nitride, a metal silicide layer, or a laminated film in which these layers are laminated may be further formed on the second conductive film 210 to lower the specific resistance. For example, a titanium nitride layer (TiN), a tantalum nitride layer (TaN), or a tungsten nitride layer (WN) is used as the metal nitride, and a titanium silicide layer (TiSi 2 ), a tungsten silicide layer (Wsi), or the like is used as the metal silicide layer. do.

Subsequently, although not shown, a floating gate separated in an island form by sequentially etching the second conductive film 210, the dielectric film 209, the first conductive film 202, and the tunneling insulating film 201, The control gate is formed in a direction perpendicular to the active region.

Since the process is the same as the general process, description thereof will be omitted.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, although the embodiment of the present invention has been described using a method of manufacturing a NAND flash memory device as an example, the present invention can be applied to all nonvolatile Mary devices including NOR type flash memory devices. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1G are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to the prior art.

2 and 3 are SEM (Scanning Electron Microscope) photographs shown to explain the problems occurring in the prior art.

4 is a cross-sectional view illustrating a nonvolatile memory device according to an embodiment of the present invention.

5A through 5H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200: semiconductor substrate

101, 201: tunneling insulating film

102 and 202: first conductive film (floating gate)

103, 204: trench

104, 104A, 104B, 205, 205A, 205B: First insulating film (HDP film)

105, 105A, 206, 206A: second insulating film (SOD film)

106, 106A, 106B, 208, 208A, 208B: third insulating film (HDP film)

107 and 209 dielectric films

108, 210: second conductive film (control gate)

207, 207A: Shield

Claims (11)

  1. A trench formed substrate;
    A first insulating film formed in a liner shape along the trench surface;
    A second insulating film formed on the first insulating film to partially fill the trench;
    A protective film formed in a liner shape along a surface of the structure including the first and second insulating films, the protective film comprising a conductive film; And
    A third insulating layer formed on the passivation layer to fill the remaining trenches
    Device isolation film of a semiconductor device comprising a.
  2. Claim 2 has been abandoned due to the setting registration fee.
    The method of claim 1,
    The passivation layer is a device isolation layer of a semiconductor device formed of a material having an etch selectivity with the third insulating film.
  3. Claim 3 was abandoned when the setup registration fee was paid.
    The method of claim 1,
    The passivation layer is a device isolation layer of a semiconductor device formed of a material having an etch selectivity with the second insulating film.
  4. Claim 4 was abandoned when the registration fee was paid.
    The method of claim 1,
    And the second insulating film is formed of a PSZ (polisilazane ) film, and the first and third insulating films are formed of a high density plasma (HDP) film.
  5. Claim 5 was abandoned upon payment of a set-up fee.
    The method of claim 1,
    And a thickness of the first insulating film formed on the bottom of the trench is thicker than the thickness of the first insulating film formed on the inner wall of the trench.
  6. Claim 6 was abandoned when the registration fee was paid.
    The method of claim 1,
    The protective film is a device isolation film of a semiconductor device formed of a conductive film of any one selected from a polycrystalline silicon film, a transition metal, a rare earth metal or an alloy film mixed with them.
  7. Forming a tunneling insulating film and a conductive film for a floating gate on the substrate;
    Etching a portion of the conductive film for the floating gate, the tunneling insulating film, and the substrate to form a trench;
    Forming a first insulating film in the form of a liner along the trench surface;
    Forming a second insulating film on the first insulating film to partially fill the trench;
    Forming a protective film having a liner shape along the surface of the structure including the first and second insulating films and formed of a conductive film; And
    Forming a third insulating layer on the protective layer to fill the remaining trenches
    Device isolation film forming method of a semiconductor device comprising a.
  8. Claim 8 was abandoned when the registration fee was paid.
    The method of claim 7, wherein
    The passivation layer may be formed of a material having an etch selectivity with the second and third insulating layers.
  9. Claim 9 was abandoned upon payment of a set-up fee.
    The method of claim 7, wherein
    And the second insulating film is formed of a PSZ (polisilazane ) film, and the first and third insulating films are formed of a high density plasma (HDP) film.
  10. Claim 10 was abandoned upon payment of a setup registration fee.
    The method of claim 7, wherein
    Forming the first insulating film,
    And forming a thickness of the first insulating film formed on the bottom of the trench thicker than the thickness of the first insulating film formed on the inner wall of the trench.
  11. Claim 11 was abandoned upon payment of a setup registration fee.
    The method of claim 7, wherein
    The protective film is a device isolation film forming method of a semiconductor device to form a conductive film of any one selected from a polysilicon film, a transition metal, a rare earth metal or an alloy film mixed with them.
KR20070066132A 2007-07-02 2007-07-02 Device Separation Film of Semiconductor Device and Formation Method Thereof KR101050454B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR20070066132A KR101050454B1 (en) 2007-07-02 2007-07-02 Device Separation Film of Semiconductor Device and Formation Method Thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR20070066132A KR101050454B1 (en) 2007-07-02 2007-07-02 Device Separation Film of Semiconductor Device and Formation Method Thereof

Publications (2)

Publication Number Publication Date
KR20090002624A KR20090002624A (en) 2009-01-09
KR101050454B1 true KR101050454B1 (en) 2011-07-19

Family

ID=40485602

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20070066132A KR101050454B1 (en) 2007-07-02 2007-07-02 Device Separation Film of Semiconductor Device and Formation Method Thereof

Country Status (1)

Country Link
KR (1) KR101050454B1 (en)

Cited By (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013049173A2 (en) * 2011-09-26 2013-04-04 Applied Materials, Inc. Improved intrench profile
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US8741778B2 (en) 2010-12-14 2014-06-03 Applied Materials, Inc. Uniform dry etch in two stages
US8771536B2 (en) 2011-08-01 2014-07-08 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299582B2 (en) 2013-11-12 2016-03-29 Applied Materials, Inc. Selective etch for metal-containing materials
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101890818B1 (en) * 2012-03-26 2018-08-22 에스케이하이닉스 주식회사 Semiconductor device with isolation layer, electromagnetic device having the same and method for fabriacting the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040049739A (en) * 2002-12-07 2004-06-12 주식회사 하이닉스반도체 Method of forming isolation layer for semiconductor device
KR20050002439A (en) * 2003-06-30 2005-01-07 주식회사 하이닉스반도체 Manufacturing method for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040049739A (en) * 2002-12-07 2004-06-12 주식회사 하이닉스반도체 Method of forming isolation layer for semiconductor device
KR20050002439A (en) * 2003-06-30 2005-01-07 주식회사 하이닉스반도체 Manufacturing method for semiconductor device

Cited By (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US8741778B2 (en) 2010-12-14 2014-06-03 Applied Materials, Inc. Uniform dry etch in two stages
US8771539B2 (en) 2011-02-22 2014-07-08 Applied Materials, Inc. Remotely-excited fluorine and water vapor etch
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8771536B2 (en) 2011-08-01 2014-07-08 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US9236266B2 (en) 2011-08-01 2016-01-12 Applied Materials, Inc. Dry-etch for silicon-and-carbon-containing films
US8679982B2 (en) 2011-08-26 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and oxygen
US8679983B2 (en) 2011-09-01 2014-03-25 Applied Materials, Inc. Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
US9012302B2 (en) 2011-09-26 2015-04-21 Applied Materials, Inc. Intrench profile
WO2013049173A2 (en) * 2011-09-26 2013-04-04 Applied Materials, Inc. Improved intrench profile
WO2013049173A3 (en) * 2011-09-26 2013-06-13 Applied Materials, Inc. Improved intrench profile
US8927390B2 (en) 2011-09-26 2015-01-06 Applied Materials, Inc. Intrench profile
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US8975152B2 (en) 2011-11-08 2015-03-10 Applied Materials, Inc. Methods of reducing substrate dislocation during gapfill processing
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9887096B2 (en) 2012-09-17 2018-02-06 Applied Materials, Inc. Differential silicon oxide etch
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9064816B2 (en) 2012-11-30 2015-06-23 Applied Materials, Inc. Dry-etch for selective oxidation removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US9093390B2 (en) 2013-03-07 2015-07-28 Applied Materials, Inc. Conformal oxide dry etch
US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
US9023732B2 (en) 2013-03-15 2015-05-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9991134B2 (en) 2013-03-15 2018-06-05 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9153442B2 (en) 2013-03-15 2015-10-06 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9184055B2 (en) 2013-03-15 2015-11-10 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9093371B2 (en) 2013-03-15 2015-07-28 Applied Materials, Inc. Processing systems and methods for halide scavenging
US8895449B1 (en) 2013-05-16 2014-11-25 Applied Materials, Inc. Delicate dry clean
US9114438B2 (en) 2013-05-21 2015-08-25 Applied Materials, Inc. Copper residue chamber clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US8956980B1 (en) 2013-09-16 2015-02-17 Applied Materials, Inc. Selective etch of silicon nitride
US9209012B2 (en) 2013-09-16 2015-12-08 Applied Materials, Inc. Selective etch of silicon nitride
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9236265B2 (en) 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9299582B2 (en) 2013-11-12 2016-03-29 Applied Materials, Inc. Selective etch for metal-containing materials
US9711366B2 (en) 2013-11-12 2017-07-18 Applied Materials, Inc. Selective etch for metal-containing materials
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9117855B2 (en) 2013-12-04 2015-08-25 Applied Materials, Inc. Polarity control for remote plasma
US9263278B2 (en) 2013-12-17 2016-02-16 Applied Materials, Inc. Dopant etch selectivity control
US9190293B2 (en) 2013-12-18 2015-11-17 Applied Materials, Inc. Even tungsten etch for high aspect ratio trenches
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9136273B1 (en) 2014-03-21 2015-09-15 Applied Materials, Inc. Flash gate air gap
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9847289B2 (en) 2014-05-30 2017-12-19 Applied Materials, Inc. Protective via cap for improved interconnect performance
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9159606B1 (en) 2014-07-31 2015-10-13 Applied Materials, Inc. Metal air gap
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9165786B1 (en) 2014-08-05 2015-10-20 Applied Materials, Inc. Integrated oxide and nitride recess for better channel contact in 3D architectures
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch

Also Published As

Publication number Publication date
KR20090002624A (en) 2009-01-09

Similar Documents

Publication Publication Date Title
US7224019B2 (en) Semiconductor device and method of manufacture thereof
US7045413B2 (en) Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby
JP4734019B2 (en) Semiconductor memory device and manufacturing method thereof
US7015099B2 (en) Method of manufacturing a flash memory cell capable of increasing a coupling ratio
JP2004165553A (en) Semiconductor memory device
TWI278970B (en) Method for manufacturing flash memory device
JP4746835B2 (en) Nonvolatile semiconductor memory device
US8497547B2 (en) Semiconductor device and a method of manufacturing the same
KR100554830B1 (en) Method of manufacturing a flash memory device
US6878588B2 (en) Method for fabricating a flash memory cell
JP2008192991A (en) Semiconductor device
US8008702B2 (en) Multi-transistor non-volatile memory element
US7053444B2 (en) Method and apparatus for a flash memory device comprising a source local interconnect
TW587331B (en) Double densed core gates in SONOS flash memory
JP4171695B2 (en) Semiconductor device
JP4065414B2 (en) Self-aligned method for forming a semiconductor memory array of floating gate memory cells with buried source lines and floating gates and memory array made thereby
US20040178470A1 (en) Semiconductor memory device and method of manufacturing the same
KR100696382B1 (en) Semiconductor device and method of fabricating the same
KR100625142B1 (en) Method of manufacturing a semiconductor device
US20060113590A1 (en) Method of forming a recess structure, recessed channel type transistor and method of manufacturing the recessed channel type transistor
US6642109B2 (en) Method of manufacturing a flash memory cell
JP3699956B2 (en) Manufacturing method of semiconductor device
KR100471575B1 (en) Method of manufacturing flash memory device
US6853028B2 (en) Non-volatile memory device having dummy pattern
US7301196B2 (en) Nonvolatile memories and methods of fabrication

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee