KR20100074508A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR20100074508A
KR20100074508A KR1020080132968A KR20080132968A KR20100074508A KR 20100074508 A KR20100074508 A KR 20100074508A KR 1020080132968 A KR1020080132968 A KR 1020080132968A KR 20080132968 A KR20080132968 A KR 20080132968A KR 20100074508 A KR20100074508 A KR 20100074508A
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South Korea
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oxide film
interface
substrate
semiconductor device
trench
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KR1020080132968A
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Korean (ko)
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신문우
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주식회사 동부하이텍
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Publication of KR20100074508A publication Critical patent/KR20100074508A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent the generation of a leakage current by compensating the interfacial property between each interface. CONSTITUTION: A trench for isolating elements is formed by etching a substrate(100). An oxide film(103) is formed on the entire surface of the substrate including the trench. Ions are implanted into the oxide film and are dispersed in the interface between the substrate and the oxide film. The substrate and the oxide film are thermally treated in order to remove the defects in the interface.

Description

반도체 소자의 제조 방법{Method of manufacturing semiconductor device}Method of manufacturing semiconductor device

본 발명은 반도체 소자에 관한 것으로, 특히 각 계면 사이의 계면특성을 보상하여 누설 전류 발생을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of compensating for interfacial properties between respective interfaces to prevent leakage currents.

일반적으로 반도체 소자 제작시 금속 배선, 층간 절연막 등 다층 구조에서 각 계면 사이에서 원자간 불완전 결합에 의해 누설 전류(Leakage Current)가 발생하게 된다. 이와 같은 누설 전류는 제품 불량의 원인이 되며 특히 시모스 이미지 센서(CMOS Image Sensor)의 경우 다크 디펙트(Dark Defect)를 유발하여 품질에 치명적인 문제점이 발생한다. In general, in the manufacture of semiconductor devices, leakage current is generated by incomplete coupling between atoms in each interface in a multi-layer structure such as a metal wiring and an interlayer insulating film. Such leakage current causes product defects, and in particular, the CMOS image sensor causes a dark defect, causing a fatal problem in quality.

이를 방지하기 위해 제품 제작 마지막 단계에서 각 계면에 격자 구조를 안정시키기 위해 수소 어닐링(Anneal)을 실시하나 트랜지스터 영역까지 수소가 충분히 전달되지 못하게 되어 각 계면 사이의 누설 전류 등 문제점을 해결할 수 없다. In order to prevent this, hydrogen annealing is performed to stabilize the lattice structure at each interface at the final stage of product manufacturing, but hydrogen cannot be sufficiently delivered to the transistor region, and thus problems such as leakage current between each interface cannot be solved.

본 발명이 이루고자 하는 기술적 과제는 각 계면 사이의 계면특성을 보상하여 누설 전류 발생을 방지할 수 있는 반도체 소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device capable of compensating for interfacial properties between respective interfaces to prevent leakage currents.

상기와 같은 과제를 달성하기 위한 본 발명의 실시 예에 따른 반도체 소자의 제조방법은 기판을 식각하여 소자 분리를 위한 트렌치를 형성하는 단계와, 상기 트렌치를 포함하는 상기 기판 전면에 산화막을 형성하는 단계와, 상기 산화막 상에 이온 주입을 실시하여 상기 트렌치를 포함하는 상기 기판과 상기 산화막의 계면 사이에 상기 이온들이 분포하도록 하는 단계와, 상기 이온이 분포된 상기 기판과 상기 산화막에 열처리하여 상기 기판과 상기 산화막의 계면 사이의 결함을 제거하는 단계를 포함하는 것을 특징으로 한다. In another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: etching a substrate to form a trench for device isolation, and forming an oxide film on an entire surface of the substrate including the trench. And implanting ions on the oxide film to distribute the ions between the substrate including the trench and the interface of the oxide film, and heat-treating the substrate on which the ions are distributed and the oxide film. And removing a defect between the interfaces of the oxide film.

본 발명의 실시 예에 따른 반도체 소자의 제조방법은 다음과 같은 효과가 있다.A method of manufacturing a semiconductor device according to an embodiment of the present invention has the following effects.

제품 제작 마지막 단계가 아닌 각 계면에서 수소(H) 임플란트 공정을 실시하므로써, 각 계면 내의 불완전 결합되어 있는 원자 결합에 수소(H)가 댕글링 본드(dangling bond)와 공유 결합하여 수소(H)가 트랩핑(trapping)되어 계면 내의 결함을 제거할 수 있다. 따라서, 결함이 발생할 가능성이 많은 소자의 계면 부위에 수소(H)를 집중적으로 도핑하여 수소(H)를 통한 큐어링(curing) 효과를 극대화할 수 있다. By performing the hydrogen (H) implant process at each interface rather than at the final stage of product manufacture, hydrogen (H) covalently bonds with dangling bonds to incompletely bonded atomic bonds at each interface, thereby producing hydrogen (H). Trapping can eliminate defects in the interface. Therefore, by intensively doping hydrogen (H) to the interface portion of the device that is likely to cause a defect can be maximized the curing effect through the hydrogen (H).

이에 따라, 계면 영역의 계면 특성을 보상할 수 있으므로 다크 커런트(Dark Current)와 같은 누설 전류 발생을 방지할 수 있다. Accordingly, since interfacial characteristics of the interfacial region can be compensated, leakage current such as dark current can be prevented.

이하, 본 발명의 기술적 과제 및 특징들은 첨부된 도면 및 실시 예들에 대한 설명을 통하여 명백하게 드러나게 될 것이다. 본 발명을 구체적으로 살펴보면 다음과 같다.Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

일반적으로, 반도체 소자는 금속 배선, 층간 절연막 등 다층 구조로 이루어지는데, 이 각 계면에서 원자간 불완전 결합에 의해 발생하는 누설 전류(Leakage Current)를 감소시키기 위한 방안이 필요하다. In general, a semiconductor device has a multi-layered structure such as a metal wiring and an interlayer insulating film, and a method for reducing leakage current caused by incomplete bonding between atoms at each interface is required.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 제조 방법을 나타내는 단면도이다. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도 1a를 참조하면, 실리콘 기판(100) 상에 소자 격리막(Shallow Trench Isolation)을 위한 트렌치(105)를 형성한다. Referring to FIG. 1A, a trench 105 for a shallow trench isolation is formed on the silicon substrate 100.

구체적으로, 실리콘 기판(100) 상에 패드 산화막(도시하지 않음) 및 질화막(도시하지 않음)을 형성하고, 이를 선택적으로 식각하여 소자 분리막이 형성될 영역을 노출시키는 트렌치 마스크를 형성한 다음 패터닝된 질화막(도시하지 않음)을 식각 마스크로 사용하여 실리콘 기판(100)을 건식 식각함으로써 트렌치(105)를 형성한다.Specifically, a pad oxide layer (not shown) and a nitride layer (not shown) are formed on the silicon substrate 100, and then selectively etched to form a trench mask that exposes a region where the device isolation layer is to be formed, and then patterned. The trench 105 is formed by dry etching the silicon substrate 100 using a nitride film (not shown) as an etching mask.

도 1b를 참조하면, 트렌치(105)를 포함하는 실리콘 기판(100) 전면에 실리콘 기판(100)과 후속 공정과 절연을 위한 산화막(103)을 형성한다. Referring to FIG. 1B, the silicon substrate 100 and the oxide film 103 for subsequent processing and insulation are formed on the entire surface of the silicon substrate 100 including the trench 105.

이어서, 도 1c와 같이 산화막(103) 상에 수소(H) 임플란트 공정을 실시하여 실리콘 기판(100)과 산화막(103) 계면에 수소(H)가 집중 분포할 수 있도록 한 후, 고온에서 열처리를 하여 실리콘 기판(100)과 산화막(103)을 큐어링(curing)한다. Subsequently, as shown in FIG. 1C, a hydrogen (H) implant process is performed on the oxide film 103 so that hydrogen (H) is concentrated at the interface between the silicon substrate 100 and the oxide film 103, and then heat-treated at a high temperature. The silicon substrate 100 and the oxide film 103 are cured.

예전에는 반도체 소자의 금속 배선 및 층간 절연막 등 다층 공정이 완료된 후, 마지막으로 수소(H) 열처리(Anneal)를 실시하였으나, 이와 같이 제품 제작 마지막 단계에서 수소(H) 열처리를 실시하게 되면 적층 깊이가 깊어질수록 충분히 수소가 전달되지 못하는 문제점이 있으므로, 본 발명의 실시예에서는 다층 구조에 있어서, 각 계면마다 수소(H) 임플란트 공정을 실시한다. Previously, after the multi-layer process such as the metal wiring and the interlayer insulating film of the semiconductor device was completed, hydrogen (H) annealing was finally performed. Since there is a problem that hydrogen is not sufficiently delivered deeper, in the embodiment of the present invention, in a multilayer structure, a hydrogen (H) implant process is performed at each interface.

여기서, 수소(H) 임플란트 공정을 실시하게 되면, 도 2와 같이 각 계면 내의 불완전 결합되어 있는 원자 결합에 수소(H)가 댕글링 본드(dangling bond)와 공유 결합하여 수소(H)가 트랩핑(trapping)되어 계면 내의 결함을 제거할 수 있다. 따라서, 결함이 발생할 가능성이 많은 소자의 계면 부위에 수소(H)를 집중적으로 도핑하여 수소(H)를 통한 큐어링(curing) 효과를 극대화할 수 있다. Here, when the hydrogen (H) implant process is performed, hydrogen (H) covalently bonds with dangling bonds to atomic bonds that are incompletely bonded in each interface as shown in FIG. Trapping can remove defects in the interface. Therefore, by intensively doping hydrogen (H) to the interface portion of the device that is likely to cause a defect can be maximized the curing effect through the hydrogen (H).

따라서, 계면 영역의 계면 특성을 보상할 수 있으므로 다크 커런트(Dark Current)와 같은 누설 전류 발생을 방지할 수 있다. Therefore, since the interfacial characteristics of the interfacial region can be compensated, leakage current such as dark current can be prevented.

본 발명의 실시예에서는 트렌치(105)를 구비한 실리콘 기판(100)와 산화막(103) 간의 계면에서의 임플란트 공정을 설명하였지만, 이에 한정하는 것이 아니라 다층 구조의 반도체 소자에서 계면 간 결함이 발생하는 모든 영역에서 적용 가능하다. Although the implant process at the interface between the silicon substrate 100 having the trench 105 and the oxide film 103 has been described in the embodiment of the present invention, the present invention is not limited thereto. Applicable in all areas.

이상에서 설명한 본 발명은 상술한 실시 예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 종래의 지식을 가진 자에게 있어 명백할 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설 명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여져야만 할 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 제조 방법을 나타내는 단면도이다. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

도 2는 계면 사이에서의 수소 분포를 나타낸 도면이다.2 is a diagram illustrating hydrogen distribution between interfaces.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

100 : 실리콘 기판 103 : 산화막100 silicon substrate 103 oxide film

105 : 트렌치 110 : 수소 이온105: trench 110: hydrogen ion

Claims (2)

기판을 식각하여 소자 분리를 위한 트렌치를 형성하는 단계와,Etching the substrate to form trenches for device isolation; 상기 트렌치를 포함하는 상기 기판 전면에 산화막을 형성하는 단계와,Forming an oxide film on an entire surface of the substrate including the trench; 상기 산화막 상에 이온 주입을 실시하여 상기 트렌치를 포함하는 상기 기판과 상기 산화막의 계면 사이에 상기 이온들이 분포하도록 하는 단계와,Implanting ions on the oxide film to distribute the ions between the substrate including the trench and the interface of the oxide film; 상기 이온이 분포된 상기 기판과 상기 산화막에 열처리하여 상기 기판과 상기 산화막의 계면 사이의 결함을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.And heat-treating the substrate in which the ions are distributed and the oxide film to remove defects between an interface between the substrate and the oxide film. 제 1 항에 있어서,The method of claim 1, 상기 이온 주입은 수소 임플란트 공정인 것을 특징으로 하는 반도체 소자의 제조방법.The ion implantation method of manufacturing a semiconductor device, characterized in that the hydrogen implant process.
KR1020080132968A 2008-12-24 2008-12-24 Method of manufacturing semiconductor device KR20100074508A (en)

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US8801952B1 (en) 2013-03-07 2014-08-12 Applied Materials, Inc. Conformal oxide dry etch
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