KR20100078341A - Method for fabricating a semiconductor - Google Patents

Method for fabricating a semiconductor Download PDF

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Publication number
KR20100078341A
KR20100078341A KR1020080136575A KR20080136575A KR20100078341A KR 20100078341 A KR20100078341 A KR 20100078341A KR 1020080136575 A KR1020080136575 A KR 1020080136575A KR 20080136575 A KR20080136575 A KR 20080136575A KR 20100078341 A KR20100078341 A KR 20100078341A
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KR
South Korea
Prior art keywords
film
stress generating
forming
buffer oxide
active region
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KR1020080136575A
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Korean (ko)
Inventor
현지원
Original Assignee
주식회사 동부하이텍
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Priority to KR1020080136575A priority Critical patent/KR20100078341A/en
Publication of KR20100078341A publication Critical patent/KR20100078341A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to effectively control the leakage current of a gate by blocking stresses which are applied to a source/drain region. CONSTITUTION: A silicide film(222) is formed on first and second gates and first and second conductive source/drain regions through an annealing process. A buffer oxide film(224) is formed to expose the surface of the silicide film on the first and the second gates. A tensile stress generating film is formed on the buffer oxide film of a first active region in order to perform an annealing process. The tensile stress generating film is eliminated. A compressive stress generating film is formed on the buffer oxide film of a second active region in order to perform an annealing process. The compressive stress generating film is eliminated.

Description

Method for manufacturing a semiconductor device {METHOD FOR FABRICATING A SEMICONDUCTOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to fabricate a semiconductor device for applying different stresses to the PMOS region and the NMOS region, and to prevent stress from being applied to the source / drain regions of the PMOS and NMOS regions. It is about a method.

One technique for improving transistor performance is to strain the semiconductor crystal lattice around the charge-carrier channel region. Transistors formed on strained silicon substrates have higher charge-carrier mobility than they were made using conventional substrates. One such strained silicon substrate technology is to provide a germanium or silicon germanium layer. A thin layer of silicon can be grown over the layer containing germanium. In this case, since the germanium crystal lattice is larger than the silicon lattice, the layer containing germanium generates a stress in which the adjacent silicon layer and the crystal lattice are inconsistent.

Thereafter, a transistor having a strained channel may be formed on the strained silicon layer. As another technique for stress generating layers on transistors, various stress layers can be used to improve carrier mobility and performance of semiconductor devices. For example, the stress can be provided by a contact etch stop layer, monolayer, bilayer, stress memory / transfer layer, STI liner, and the like. Most of these techniques use nitride films to provide tensile and compressive forces, but other materials such as HDP oxide films may be used. Another method of generating strain in a transistor is a technique for modified STI regions. One method is to include linings of the STI recess regions with a stress generating material before filling the recess regions of the STI with insulator. The stress generating material can later transfer the stress onto adjacent semiconductors.

In CMOS transistor technology, N-channel and P-channel transistors require stress liners with opposite stress polarities to effectively increase carrier mobility. To increase carrier mobility, N-channel transistors require tensile stress liners and P-channel transistors require compressive stress liners. In both types of transistors, because different types of stress are required, each transistor must withstand the burden of the process to generate stresses of polarity that it does not need. In some processes, the entire SMT (Stress Memory Technology) layer is deposited after the source / drain ion implantation of the N- and P-channels before annealing. This technique etches and removes the SMT layer of a P-channel transistor before annealing so that only the N-channel transistor is under stress.

Recently, one of the methods using the SMT layer is a method of applying strain to a silicon substrate using a strong tensile-SMT layer, which will be described with reference to FIGS. 1A to 1C.

1A to 1C are cross-sectional views illustrating a process of fabricating a strained semiconductor device using a conventional SMT layer.

As shown in FIG. 1A, a semiconductor substrate 100 is provided. Partially fabricated transistor pairs, N-channel transistors and P-channel transistors 102 and 104 are formed on the semiconductor substrate 100. The N-channel and P-channel transistors 102 and 104 include a gate dielectric layer 110, a gate electrode 112, and a spacer 114. The semiconductor substrate 100 may be a single crystal silicon substrate or a silicon on insulator (SOI) wafer.

In addition, an isolation trench 116 is formed in the semiconductor substrate 100, and a source / drain region is formed in the semiconductor substrate 100 exposed by the gate electrode 112 and the spacer 114 through an impurity ion implantation process. 118 and 120 are formed. Here, the source / drain regions 118 and 112 may be formed of an LDD structure.

Then, a silicide process using cobalt / nickel is performed to form the silicide layer 122 on the gate electrode 112 and the source / drain regions 118 and 120.

Thereafter, as shown in FIG. 1B, after forming the liner oxide layer 124, a strong tensile SMT layer 126 is formed thereon, and a stress transition is performed on the gate electrode 112 and the semiconductor substrate 100. The annealing process is performed. Through the annealing process, the semiconductor substrate 100 and the gate electrode 112 in the N-channel and P-channel transistors 102 and 104 have tensile strain.

Next, as shown in FIG. 1C, a cleaning process is performed to remove the SMT layer 126 and the liner oxide layer 124.

In the conventional strain application method using the strong tensile SMT layer, the gate tunneling current is generated by causing damage due to excessive stress on the edge portion of the gate electrode, thereby increasing the gate leakage current.

Conventional strain application method using the strong tensile SMT layer is a strain applied to the source / drain region other than the gate electrode due to the strong tensile SMT layer GIDL (Gate-Induced Drain) due to the side diffusion of the dopant implanted in the source / drain region Leakage) There is a problem that the current is increased.

This problem causes a hot carrier instability of the device, thereby deteriorating the reliability of the CMOS device.

The present invention can improve the stress damage applied to the gate edge region by applying a local strong tensile stress in the gate region using a buffer oxide film, and blocks the stress applied to the source / drain region to prevent N Improves electron mobility of channel transistors, effectively controlling gate leakage current

In the method of manufacturing a semiconductor device according to the present invention, a first gate is formed in a first active region, a second gate is formed in a second active region, and a first conductivity type ion is implanted into the first active region. Forming a first conductivity type source / drain region, implanting a second conductivity type ion into the second active region to form a second conductivity type source / drain region, and performing an annealing process on the first and second gates and the A silicide layer is formed on the first and second conductivity type source / drain regions, and a buffer oxide layer is formed to expose the surface of the silicide layer formed on the first and second gates, and is formed on the buffer oxide layer on the first active region. After forming the tensile stress generating film and performing an annealing process, the tensile stress generating film is removed and the compressive stress is formed on the buffer oxide film on the second active region. After the forming film is subjected to annealing production processes include the removal of the compressive stress generated makreul.

The present invention can improve the stress damage applied to the gate edge region by applying a local strong tensile stress in the gate region using a buffer oxide film, and blocks the stress applied to the source / drain region to prevent N The electron mobility of the channel transistor can be improved to effectively control the gate leakage current.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

According to an exemplary embodiment of the present invention, the tensile strain and the compressive stress are applied to the region where the N-channel transistor is formed and the region where the P-channel transistor is formed, respectively, so that the compressive strain acts in the vertical direction in the P-channel region to improve the mobility of the holes. A semiconductor device manufacturing method that can be described will be described.

2A through 2D are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a semiconductor substrate 200 is provided. Partially fabricated transistor pairs, N-channel transistors and P-channel transistors 202 and 204, are formed on the semiconductor substrate 200. The N-channel and P-channel transistors 202 and 204 include a gate dielectric layer 210, a gate electrode 212, and a spacer 214. The semiconductor substrate 200 may be a single crystal silicon substrate or a silicon on insulator (SOI) wafer.

In addition, an isolation trench 216 is formed in the semiconductor substrate 200, and a source / drain region is formed in the semiconductor substrate 200 exposed by the gate electrode 212 and the spacer 214 through an impurity ion implantation process. 218 and 220 are formed. Here, the source / drain regions 218 and 222 may be formed of an LDD structure.

Then, a silicide process using cobalt / nickel is performed to form the silicide layer 222 on the gate electrode 212 and the source / drain regions 218 and 220.

Thereafter, the buffer oxide film 224 is formed on the entire surface of the semiconductor substrate 200 on which the silicide film 222 is formed, that is, the buffer oxide film is completely embedded in the silicide film 222 formed on the gate electrode 212 by PE-CVD. After forming 224, a planarization process, for example, a CMP process, is performed by using the silicide layer 222 formed on the gate electrode 212 as the polishing stop point.

Then, as shown in FIG. 2B, the tensile stress generating film 226 is formed on the buffer oxide film 224 on which the N-channel transistor 202 is formed, that is, the semiconductor substrate on which the buffer oxide film 224 is formed ( 200, a tensile stress generating film 226 is formed on the entire surface, and then a photoresist pattern is formed in which a region where the N-channel transistor 202 is formed is opened, and a cleaning process using a photoresist pattern as a mask, for example The cleaning process using H 3 PO 4 is performed to open the region where the P-channel transistor 204 is formed. Then, an annealing process, such as Rapid Thermal Processing (RTP), is performed on the semiconductor substrate 200 on which the tensile stress generating film 226 is formed only on the region of the N-channel transistor 202. The stress is transferred to the region where the transistor 202 is formed.

As described above, after the buffer oxide film 224 is formed, the tensile stress generating film 226 is formed only in the region where the N-channel transistor 202 is formed, thereby performing an annealing process, thereby forming the gate electrode (N) of the N-channel transistor 202. Local tensile stress may be applied to 212 and may block the stress applied to the edge portion of the gate electrode 212 and the source / drain regions 218 and 220.

Thereafter, as shown in FIG. 2C, the tensile stress generating film 226 is removed, and the compressive stress generating film 228 is formed on the buffer oxide film 224 in the region where the P-channel transistor 204 is formed. That is, after forming the compressive stress generating film 228 on the entire surface of the semiconductor substrate 200 on which the buffer oxide film 224 is formed, a photoresist pattern is formed in which the region where the P-channel transistor 204 is formed is opened. A cleaning process using a resist pattern as a mask, for example, a cleaning process using H3PO4 is performed to open a region where the N-channel transistor 202 is formed. Then, the annealing process is performed on the semiconductor substrate 200 on which the compressive stress generation film 228 is formed only on the region of the P-channel transistor 202, thereby transferring the stress to the region where the P-channel transistor 204 is formed. All.

As described above, according to the present invention, after the buffer oxide film 224 is formed, the compressive stress generating film 226 is formed only in the region where the P-channel transistor 204 is formed to perform an annealing process such as a rapid heat treatment process (RTP). As a result, local tensile stress is applied to the gate electrode 212 of the P-channel transistor 204, and the stress applied to the edge portion and the source / drain regions 218 and 220 of the gate electrode 212 is blocked. Can be.

Next, as shown in FIG. 2D, an etching process using H 3 PO 4 is performed to remove the compressive stress generating film 228.

According to the present invention, the compressive strain acts in the vertical direction in the P-channel region by providing tensile and compressive stresses to the region where the N-channel transistor 202 is formed and the region where the P-channel transistor 204 is formed, respectively. The mobility of the hole can be improved. That is, as shown in FIG. 3A, it can be seen that the current values of the P-channel transistors 204 and PMOS and the N-channel transistors 202 and NMOS increase. As shown in FIG. 3B, the gate electrode is increased. It can be seen that the GIDL current is improved according to the voltage applied to 212.

The present invention has been limited to the embodiments of the present invention, but it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

1A to 1C are cross-sectional views illustrating a process of fabricating a strained semiconductor device using a conventional SMT layer.

2A to 2D are cross-sectional views illustrating a process of manufacturing a strained semiconductor device according to the present invention.

3A to 3B are graphs showing the characteristics of the current value and the GIDL current value when the present invention is applied.

Description of the Related Art

200 semiconductor substrate 202 N-channel transistor

204: P-channel transistor 210: gate dielectric film

212: gate electrode 214: spacer

216: trenches for device isolation 218, 220: source and drain regions

222: silicide film 224: buffer oxide film

226: tensile stress generating film 228: compressive stress generating film

Claims (9)

Forming a first gate in the first active region, Forming a second gate in the second active region, Implanting first conductivity type ions into the first active region to form a source / drain region of a first conductivity type, Implanting second conductivity type ions into the second active region to form a second conductivity type source / drain region, A silicide film is formed on the first and second gates and the first and second conductivity type source / drain regions through an annealing process, Forming a buffer oxide film so that the surfaces of the silicide films formed on the first and second gates are exposed; Forming an tensile stress generating film on the buffer oxide layer on the first active region, performing an annealing process, and then removing the tensile stress generating film; And forming a compressive stress generating film on the buffer oxide layer on the second active region, performing an annealing process, and then removing the compressive stress generating film. The method of claim 1, The buffer oxide film is a semiconductor device manufacturing method, characterized in that formed by PE-CVD method. The method of claim 1, And forming a buffer oxide film over the entire surface of the semiconductor substrate on which the silicide film is formed, and then performing a chemical mechanical polishing process using the silicide film as a polishing stop point. The method of claim 1, The first conductive type has a polarity opposite to that of the second conductive type. The method of claim 1, The tensile stress generating film is a silicon nitride film formed by a PE-CVD method. The method of claim 1, The annealing process after forming the said tensile stress generation film is a RTP process. The method of claim 1, The tensile stress generating film is removed through a cleaning process using a H 3 PO 4 solution. The method of claim 1, The annealing step after forming the compressive stress generating film is a semiconductor device manufacturing method. The method of claim 1, The compressive stress generating film is removed through a cleaning process using a H 3 PO 4 solution.
KR1020080136575A 2008-12-30 2008-12-30 Method for fabricating a semiconductor KR20100078341A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9595610B2 (en) 2014-07-07 2017-03-14 Samsung Electronics Co., Ltd. Field effect transistor and method of fabricating the same
CN108461448A (en) * 2017-02-17 2018-08-28 力晶科技股份有限公司 Method for manufacturing semiconductor element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9595610B2 (en) 2014-07-07 2017-03-14 Samsung Electronics Co., Ltd. Field effect transistor and method of fabricating the same
CN108461448A (en) * 2017-02-17 2018-08-28 力晶科技股份有限公司 Method for manufacturing semiconductor element

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