KR20100069001A - Semiconductor package - Google Patents

Abstract

PURPOSE: A semiconductor package is provided to be applicable in a fine pitch by electrically connecting a semiconductor die with a substrate through an anisotropic conductive film. CONSTITUTION: A first wiring pattern(113) is formed on the upper side(110a) of a substrate(110). A second wiring pattern(114) is formed on the lower side(110b) of the substrate. The first semiconductor die(120) is adhered on the upper side of the substrate through an anisotropic conductive film(122). A second semiconductor die(150) is adhered on the upper side of the first semiconductor die. A conductive wire(160) electrically connects the second bond pad and the first wiring pattern. An encapsulant(170) encapsulates the substrate, the first semiconductor die, the second semiconductor die, and the conductive wire.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package. More particularly, the present invention relates to a semiconductor package that is electrically connected to a substrate and a semiconductor die through an anisotropic conductive film. .

According to the development of the electronics industry, the core package of the semiconductor device, which is its core device, is highly integrated according to the high functional and miniaturization of electronic devices, and the demand for high performance and small semiconductor packages is rapidly increasing. According to this trend, a semiconductor package is mainly a multi-chip package in which a plurality of semiconductor dies are stacked up or down in a package or embedded in a planar arrangement, or a semiconductor die is directly attached to a substrate and sealed. Board-on-chip (BOC) packages with reduced size are used.

Here, the BOC package forms a center slot in the center of the substrate, and electrically connects the substrate and the semiconductor die with conductive wires through a region where the center slot is formed. That is, in the BOC package, the region where the conductive wire is bonded corresponds to the region where the center slot is formed on the substrate. Therefore, the BOC package has a limitation in bonding area for electrically connecting the substrate and the semiconductor die. In addition, since a wiring pattern is not formed in the region where the semiconductor die is attached to the substrate, when the semiconductor die is stacked for the high capacity semiconductor package, the wiring pattern of the substrate cannot be secured.

In addition, as the wiring pattern of the substrate becomes fine pitch for high capacity and high integration of the semiconductor package, it is difficult to separate the wiring work for electrically connecting the substrate and the semiconductor die, and each wiring pattern becomes fine pitch. In the course of the conducting operation, a problem of electrical shorting has occurred.

The present invention is to overcome the above-mentioned problems, the object of the present invention is electrically applicable to the fine pitch since the substrate and the semiconductor die is electrically connected through an anisotropic conductive film, and to electrically connect the highly integrated substrate and the semiconductor die It is to provide an easy semiconductor package.

In addition, another object of the present invention is to electrically connect the substrate and the semiconductor die through an anisotropic conductive film, so that a separate conduction process can be eliminated. The present invention provides a semiconductor package that can be electrically connected to and can eliminate space inefficiency.

In order to achieve the above object, the semiconductor package according to the present invention has a substrate having a plurality of first wiring patterns formed on an upper surface thereof, a plurality of second wiring patterns formed on a lower surface thereof, and an adhesive film bonded to an upper surface of the substrate through an anisotropic conductive film. And a plurality of first bond pads formed on a bottom surface of the first semiconductor die and the first semiconductor die electrically connected to the first wiring pattern of the substrate through the anisotropic conductive film and the top surface of the first semiconductor die. A second semiconductor die having a bond pad formed on an upper surface thereof, a conductive wire electrically connecting between the second bond pad of the second semiconductor die and the first wiring pattern, the substrate, the first semiconductor die, and the second semiconductor It may include an encapsulant for encapsulating a die and the conductive wire.

 The anisotropic conductive film is an adhesive including a plurality of conductive balls, and may electrically connect between the first bond pad of the first semiconductor die and the first wiring pattern of the substrate through the conductive balls.

The substrate may further include a center slot, which is a slot penetrating through the upper surface and the lower surface, at a central portion of the substrate, and a plurality of bond fingers may be formed at an outer circumference of the center slot on the lower surface.

And a center conductive wire electrically connecting between the bond finger of the substrate and the first bond pad of the first semiconductor die exposed to the bottom surface of the substrate through the center slot.

The apparatus may further include a center encapsulant for encapsulating the center slot of the substrate, the first bond pad of the first semiconductor die electrically connected to the bond finger, and the center conductive wire.

The semiconductor device may further include a solder ball electrically connected to the second wiring pattern of the substrate.

As described above, the semiconductor package according to the present invention is electrically applicable to the fine pitch since the substrate and the semiconductor die are electrically connected through the anisotropic conductive film, and it is easy to electrically connect the highly integrated substrate and the semiconductor die.

In addition, as described above, the semiconductor package according to the present invention electrically connects the substrate and the semiconductor die through the anisotropic conductive film, thereby eliminating a separate conduction process, and bond pads of the semiconductor die may be removed even in areas where the semiconductor die is bonded. Since it is electrically connected to the wiring pattern of the substrate it is possible to eliminate the inefficiency of the space.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention. Here, parts having similar configurations and operations throughout the specification are denoted by the same reference numerals.

Referring to FIG. 1, a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention is illustrated.

As shown in FIG. 1, the semiconductor package 100 includes a substrate 110, a first semiconductor die 120, a center conductive wire 130, a center encapsulant 140, a second semiconductor die 150, and a conductive portion. The wire 160, the encapsulant 170, and the solder ball 180 are included.

The substrate 110 is formed of an upper surface 110a and a lower surface 110b opposite to the upper surface 110a. In addition, a center slot 110c is formed at the center of the substrate 110 to expose the lower surface 120b of the first semiconductor die 120 adhered to the upper surface 110a. The substrate 110 has a plurality of bond fingers 111 formed on the outer circumference of the center slot 110c on the lower surface 110b, a plurality of first wiring patterns 113 formed on the upper surface 110a, and the lower surface ( A plurality of second wiring patterns 114 formed on 110b). In addition, the first wiring pattern 122 of the substrate 110 is formed to protrude toward the upper surface 110a of the substrate 110.

The substrate 110 is electrically conductive between the bond finger 111 and the second wiring pattern 113 and electrically connects the first wiring pattern 112 and the second wiring pattern 113, respectively. Via 114 is further formed. That is, the bond finger 111 and the first wiring pattern 112 of the substrate 110 are electrically connected to the second wiring pattern 113 through the conductive via 114, respectively.

The first wiring pattern 112 and the second wiring pattern 113 may be made of copper (Cu), titanium (Ti), nickel (Ni), palladium (Pd), and equivalent metals thereof. This is not a limitation.

The upper surface 110a and the lower surface 110b of the substrate 110 are formed to have a predetermined thickness so as to cover outer periphery of the first wiring pattern 112 and the second wiring pattern 113. A solder mask (not shown) for protecting the 112 and the second wiring pattern 113 from the external environment may be further formed, but is not limited thereto.

The first semiconductor die 120 has an upper surface 120a and a lower surface 120b opposite to the upper surface 120a, and a plurality of first bond pads 121 are formed on the lower surface 120b. The lower surface 120b of the first semiconductor die 120 is attached to the upper surface 110a of the substrate 110 through an anisotropic conductive film 122. In this case, the first bond pad 121 of the first semiconductor die 120 is formed to protrude to the bottom surface 120b of the first semiconductor die 120.

The anisotropic conductive film 122 is an adhesive type including a plurality of conductive balls 122a, and may be cured through heat treatment. Therefore, the first semiconductor die 120 is adhered to the substrate 110 due to pressure and heat treatment, wherein the first bond pad 121 of the first semiconductor die 120 is the anisotropic conductive film 122. The conductive ball 122a is electrically connected to the first wiring pattern 122 of the substrate 110. That is, the first bond pad 121 of the first semiconductor die 120 and the first wiring pattern 122 of the substrate 110 are electrically connected to each other through the conductive ball 122a. An adhesive component of the anisotropic conductive film 122 is adhered between the 110 and the first semiconductor die 120.

At least one of the first bond pads 121 of the first semiconductor die 120 is exposed to the bottom surface 110b of the substrate 110 through the center slot 110c of the substrate 110. The first bond pad 121 exposed through the center slot 110c of the substrate 100 may be formed on the bond finger 111 formed on the bottom surface 110b of the substrate 110 through a center conductive wire 130. Is electrically connected).

The center conductive wire 130 is a first bond pad exposed to the bottom surface 110b of the substrate 110 through the center slot 110c of the first bond pads 121 of the first semiconductor die 120. The 121 and the bond fingers 111 of the substrate 110 are electrically connected to each other. The center conductive wire 130 may use any one of gold (Au), aluminum (Al), and copper (Cu) or an alloy thereof, but is not limited thereto. The center conductive wire 130 is preferably formed of gold (Au), and has higher ductility and electrical conductivity than other metals, so that the center conductive wire 130 may be thinly formed. It is because it is easy at the time of wire bonding.

The center encapsulation 140 encapsulates the substrate 110, the first semiconductor die 120, and the center conductive wire 130 to protect them from an external environment. That is, the center encapsulant 140 is exposed to the bottom surface 110b of the substrate 110 through the center slot 110c of the substrate 110 and the center slot 110c of the substrate 110. The first semiconductor die 120 and the center conductive wire 130 are encapsulated. Therefore, the center encapsulant 140 also encapsulates the first bond pad 121 of the first semiconductor die 120.

The second semiconductor die 150 has an upper surface 150a and a lower surface 150b opposite to the upper surface 150a, and a plurality of second bond pads 151 are formed on the upper surface 150a. The lower surface 150b of the second semiconductor die 150 is attached to the upper surface 120a of the first semiconductor die 120 through an adhesive 152. The second bond pad 151 of the second semiconductor die 150 is electrically connected to the first wiring pattern 112 formed on the upper surface 110a of the substrate 110 through the conductive wire 160. . The adhesive 152 may use any one selected from a general liquid epoxy adhesive, an adhesive film, an adhesive tape, and an equivalent thereof, and the type of the adhesive 152 is not limited thereto.

The conductive wire 160 electrically connects the second bond pad 151 of the second semiconductor die 150 and the first wiring pattern 112 of the substrate 110 to each other. The conductive wire 160 is made of any one of gold (Au), aluminum (Al), and copper (Cu) or an alloy thereof, but is not limited thereto. The conductive wire 160 is preferably formed of gold (Au), which is higher in ductility and electrical conductivity than other metals, so that the conductive wire 160 may be thinly formed, and the conductive wire 160 may have high electrical conductivity even when thinly formed. This is because it is easy at the time of bonding.

The encapsulant 170 encapsulates the substrate 110, the first semiconductor die 120, the second semiconductor die 150, and the conductive wire 160 to protect them from the external environment. encapsulation). That is, the encapsulant 170 is formed to cover all of the top surface 110a of the substrate 110, the first semiconductor die 120, the second semiconductor die 150, and the conductive wire 160. Encapsulate.

The solder ball 180 is deposited on the second wiring pattern 113 formed on the bottom surface 110b of the substrate 110 to form the conductive via 114, the bond finger 111, and the center conductive wire 130. It is electrically connected to the first semiconductor die 120 through. The solder ball 180 is welded to the second wiring pattern 113 to form the second semiconductor die 150 through the conductive via 114, the first wiring pattern 112, and the conductive wire 160. Is electrically connected). The solder ball 180 may be formed of any one selected from tin / lead, lead-free tin, and equivalents thereof, but is not limited thereto. In the process of welding the solder ball 180 to the second wiring pattern 113, the volatile flux having a viscosity is applied to the second wiring pattern 113, and then the solder ball 180 is temporarily seated thereon. do. Subsequently, the solder ball 180 is strongly and electrically connected to the second wiring pattern 113 by putting the semiconductor package 100 into a furnace having a temperature of approximately 100 to 300 ° C. Of course, all of the flux in the furnace is volatilized and removed. The solder ball 180 is electrically connected to the first semiconductor die 120 or the second semiconductor die 150 through the substrate 110. Thus, the first semiconductor die 120 and the second semiconductor die 150 may be mounted on an external device (not shown) through the solder ball 180 to be electrically connected to the external device.

In the semiconductor package 100, the first semiconductor die 120 may be electrically connected through the substrate 110 and the center conductive wire 130, or may be electrically connected through the anisotropic conductive film 122. That is, the semiconductor package 100 may be formed of the first wiring pattern 112 and the first semiconductor die 120 of the substrate 110 by the conductive wires 130 through the region where the center slot 110c of the substrate 110 is formed. In addition to the first bond pads 121 being electrically connected to each other, the first wiring pattern 112 and the first semiconductor die 120 of the substrate 110 may be formed through the conductive balls 122a of the anisotropic conductive film 122. Since the first bond pads 121 are electrically connected, more first bond pads 121 may be electrically connected to the substrate 110. Therefore, the semiconductor package 100 can be applied to fine pitch.

In addition, since the semiconductor package 100 may be electrically connected through the anisotropic conductive film 122, the semiconductor package 100 may be electrically connected to the substrate 110 and the first semiconductor die 120 without a separate conductive operation. The present invention can also be applied to the connection between the substrate 110 and the first semiconductor die 120.

In the semiconductor package 100, the first bond pad 121 of the first semiconductor die 120 is electrically connected to the first wiring pattern 112 of the substrate 110 even in a region where the first semiconductor die 120 is bonded. Can eliminate space inefficiency.

2, a cross-sectional view illustrating a semiconductor package according to another embodiment of the present invention is shown.

As illustrated in FIG. 2, the semiconductor package 200 includes a substrate 210, a first semiconductor die 220, a second semiconductor die 150, a conductive wire 160, and an encapsulant 170.

The second semiconductor die 150, the conductive wire 160, and the encapsulant 170 of the semiconductor package 200 are the same as the semiconductor package 100 shown in FIG. 1. Therefore, the description will be given based on the substrate 210 and the first semiconductor die 220 which are different from the semiconductor package 100 in the semiconductor package 200.

The substrate 210 includes an upper surface 210a and a lower surface 210b opposite to the upper surface 210a. The substrate 210 includes a plurality of first wiring patterns 213 formed on the upper surface 210a and a plurality of second wiring patterns 214 formed on the lower surface 210b. The first wiring pattern 222 of the substrate 210 is formed to protrude to the upper surface 210a of the substrate 210.

The first wiring pattern 212 and the second wiring pattern 213 may be made of copper (Cu), titanium (Ti), nickel (Ni), palladium (Pd), and equivalent metals thereof. This is not a limitation.

The substrate 210 penetrates between the upper surface 110a and the lower surface 110b of the substrate 210 to form the first wiring pattern 112 and the substrate 210 formed on the upper surface 110a of the substrate 210. The conductive via 214 is further formed to electrically connect the second wiring pattern 113 formed on the bottom surface 110b of FIG.

The upper surface 210a and the lower surface 210b of the substrate 210 are formed to have a predetermined thickness so as to cover outer periphery of the first wiring pattern 212 and the second wiring pattern 213. A solder mask (not shown) for protecting the 212 and the second wiring pattern 213 from the external environment may be further formed, but is not limited thereto.

The first semiconductor die 220 has an upper surface 220a and a lower surface 220b opposite to the upper surface 220a, and a plurality of first bond pads 221 are formed on the lower surface 220b. The lower surface 220b of the first semiconductor die 220 is attached to the upper surface 210a of the substrate 210 through an anisotropic conductive film 222. In this case, the first bond pads 221 of the first semiconductor die 220 are formed to protrude to the bottom surface 220b of the first semiconductor die 220.

The anisotropic conductive film 222 is an adhesive type including the conductive balls 222a and may be cured through heat treatment. Therefore, the first semiconductor die 220 is adhered to the substrate 210 due to pressure and heat treatment, wherein the first bond pad 221 of the first semiconductor die 220 is formed of the anisotropic conductive film 222. The conductive ball 222a is electrically connected to the first wiring pattern 222 of the substrate 210. That is, the first bond pad 221 of the first semiconductor die 220 and the first wiring pattern 222 of the substrate 210 are electrically connected through conductive balls 222a. An adhesive component of the anisotropic conductive film 222 is adhered between the 210 and the first semiconductor die 220.

In the semiconductor package 200, the second wiring pattern 212 of the substrate 210 may be connected to an external device through an anisotropic conductive film, or the package may be stacked at multiple levels.

In the semiconductor package 200, the first semiconductor die 220 may be electrically connected to the substrate 210 through the anisotropic conductive film 222. That is, in the semiconductor package 200, the first bond pad 221 of the first semiconductor die 220 may have the first wiring pattern 212 of the substrate 210 through the conductive balls 222a of the anisotropic conductive film 222. Since it is electrically connected to the first bond pad 221 may be electrically connected to the substrate 210 without a separate conducting work. Therefore, the semiconductor package 200 may be applied to fine pitch and may also be applied to the connection of the highly integrated substrate 210 and the first semiconductor die 220.

In the semiconductor package 200, the first bond pad 221 of the first semiconductor die 220 is electrically connected to the first wiring pattern 212 of the substrate 210 even in a region where the first semiconductor die 220 is bonded. Can eliminate space inefficiency.

Referring to FIG. 3, there is shown a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

As shown in FIG. 3, the semiconductor package 300 includes a substrate 210, a first semiconductor die 220, a second semiconductor die 150, a conductive wire 160, an encapsulant 170, and a solder ball 380. ).

The substrate 210, the first semiconductor die 220, the second semiconductor die 150, the conductive wire 160, and the encapsulant 170 of the semiconductor package 300 may include the semiconductor package illustrated in FIG. 2. Same as 200. Therefore, the solder ball 380 different from the semiconductor package 200 in the semiconductor package 300 will be described mainly.

The solder ball 380 is deposited on the second wiring pattern 213 formed on the bottom surface 210b of the substrate 210 to form the conductive via 214, the first wiring pattern 211, and the anisotropic conductive film 122. Through) is electrically connected to the first semiconductor die 220. The solder ball 380 is welded to the second wiring pattern 213 to form the second semiconductor die 150 through the conductive via 214, the first wiring pattern 212, and the conductive wire 160. Is electrically connected). The solder ball 380 may be formed of any one selected from tin / lead, lead-free tin, and equivalents thereof, but is not limited thereto. In the process of welding the solder ball 380 to the second wiring pattern 213, a volatile flux having a viscosity is applied to the second wiring pattern 213, and then the solder ball 380 is temporarily seated thereon. do. Thereafter, the semiconductor package 300 is inserted into and taken out of a furnace having a temperature of approximately 100 to 300 ° C., so that the solder ball 380 is strongly and electrically connected to the second wiring pattern 213. Of course, all of the flux in the furnace is volatilized and removed. The solder ball 380 is electrically connected to the first semiconductor die 220 or the second semiconductor die 150 through the substrate 210. Thus, the first semiconductor die 220 and the second semiconductor die 150 may be mounted on an external device (not shown) through the solder ball 380 to be electrically connected to the external device.

In the semiconductor package 300, the first semiconductor die 220 may be electrically connected to the substrate 210 through the anisotropic conductive film 222. That is, in the semiconductor package 300, the first bond pads 221 of the first semiconductor die 220 may pass through the first wiring patterns 212 of the substrate 210 through the conductive balls 222a of the anisotropic conductive film 222. Since it is electrically connected to the first bond pad 221 may be electrically connected to the substrate 210 without a separate conducting work. Therefore, the semiconductor package 300 may be applied to fine pitch and may also be applied to the connection of the highly integrated substrate 210 and the first semiconductor die 220.

In the semiconductor package 300, the first bond pad 221 of the first semiconductor die 220 is electrically connected to the first wiring pattern 212 of the substrate 210 even in a region where the first semiconductor die 220 is bonded. Can eliminate space inefficiency.

What has been described above is only one embodiment for carrying out the semiconductor package according to the present invention, and the present invention is not limited to the above-described embodiment, and the present invention deviates from the gist of the present invention. Without this, anyone skilled in the art to which the present invention pertains will have the technical spirit of the present invention to the extent that various modifications can be made.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

3 is a cross-sectional view illustrating a semiconductor package in accordance with still another embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100, 200, 300; Semiconductor package

110, 210; Substrates 120 and 220; First semiconductor die

130; Center conductive wire 140; Center Encapsulant

150; Second semiconductor die 160; Conductive wire

170; Encapsulants 180, 380; Solder ball

Claims (6)

A substrate having a plurality of first wiring patterns formed on an upper surface thereof and a plurality of second wiring patterns formed on a lower surface thereof; A first semiconductor die adhered to an upper surface of the substrate through an anisotropic conductive film, and a plurality of first bond pads formed on a lower surface of the substrate be electrically connected to the first wiring pattern of the substrate through the anisotropic conductive film; A second semiconductor die adhered to an upper surface of the first semiconductor die and having a plurality of second bond pads formed on an upper surface thereof; A conductive wire electrically connecting between the second bond pad of the second semiconductor die and the first wiring pattern; And And an encapsulation for encapsulating the substrate, the first semiconductor die, the second semiconductor die, and the conductive wire. The method of claim 1,  The anisotropic conductive film is an adhesive including a plurality of conductive balls, and electrically connects between the first bond pad of the first semiconductor die and the first wiring pattern of the substrate through the conductive balls. Semiconductor package. The method of claim 1, The substrate is And a center slot, which is a slot penetrating through the upper surface and the lower surface, in the center portion of the substrate, and a plurality of bond fingers are formed on an outer circumference of the center slot on the lower surface. The method of claim 3, wherein And a center conductive wire electrically connecting between the bond finger of the substrate and the first bond pad of the first semiconductor die exposed through the center slot to the bottom surface of the substrate. The method of claim 4, wherein And a center encapsulation for encapsulating the center slot of the substrate, the first bond pad of the first semiconductor die electrically connected to the bond finger, and the center conductive wire. The method of claim 1, And a solder ball electrically connected to the second wiring pattern of the substrate.

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