KR20100064150A

KR20100064150A - Electro-static discharge protection circuit

Info

Publication number: KR20100064150A
Application number: KR1020080122582A
Authority: KR
Inventors: 김장후
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-12-04
Filing date: 2008-12-04
Publication date: 2010-06-14

Abstract

PURPOSE: An electrostatic discharge protective circuit is provided to prevent the generation of an operational failure due to the damage of an input/output driver by providing an electrostatic discharging path. CONSTITUTION: Main electrostatic discharging units(310, 312) provide a first electrostatic discharging path between a pad and a power-line. A data input/output driver unit is connected between the pad and the power-line and drives data which is input or output through the pad using power from the power-line. Sub electrostatic discharging units(320, 322) provide a second electrostatic discharging path between the pad and the power-line. The sub electrostatic discharging units are connected between the pad and the power-line and include a first MOS transistor(P32) which includes a gate connected with the power-line.

Description

Electrostatic Discharge Protection Circuit

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a main electrostatic discharge circuit and a sub electrostatic discharge circuit which is turned on at a low voltage to provide an electrostatic discharge path.

In general, static electricity refers to a phenomenon in which current flows instantaneously due to a very large voltage difference between two objects when two insulated objects come into contact with each other.

If static electricity flows through the semiconductor internal circuits, the internal circuits can be fatally damaged.

Therefore, the semiconductor device has an electrostatic discharge circuit that provides an electrostatic discharge path so that the internal circuit of the semiconductor device is not destroyed by the electrostatic current.

In addition, when static electricity flows into the data input / output pad, an electrostatic protection resistor is separately provided between the data input / output pad and the data input / output driver to prevent static electricity from flowing into the data input / output driver.

The static protection resistor should be small in order to match the high speed or low power characteristics of the product. Since the resistance value of the ESD protection has a trade-off relationship with the speed of the device, decreasing the resistance increases the speed of the device but is vulnerable to static electricity.

1 illustrates a conventional electrostatic discharge circuit.

Referring to FIG. 1, a first electrostatic discharge unit 110 is connected between a power supply voltage line 100 and a data input / output pad 104, and a ground voltage line 102 and a data input / output pad 104. The second electrostatic discharge unit 112 is connected therebetween.

The pull-up driver unit 120 is connected between the power supply voltage line 100 and the data input / output pad 104, and the pull-down driver unit 122 is connected to the ground voltage line 102 and the data input / output pad.

Connected between 104.

The first electrostatic discharge unit 110 is composed of a PMOS transistor P11 whose gate is connected to the power supply voltage line 100, and the second electrostatic discharge unit 112 is an NMOS connected to the ground voltage line 102. It consists of transistor N11.

PMOS transistor P11 and NMOS transistor N11 are not turned on and operated by channel formation like a conventional MOS transistor, but break down.

The breakdown phenomenon causes the internal NPN or PNP structure to act like a BJT, allowing a large amount of current to flow.

The pull-up driver unit 120 includes a first resistor R11 and a PMOS transistor P12 connected in series between the power supply voltage line 100 and the data input / output pad 104, and the pull-down driver unit 122 includes: The second resistor R12 and the NMOS transistor N12 are connected in series between the ground voltage line 102 and the data input / output pad 104.

The first resistor R11 and the second resistor R12 are data output resistors to protect the pull-up / pull-down drivers P12 and N12 and the data input / output pad 104 and the pull-up / pull-down driver.

It is connected between (P12, N12).

When static electricity flows into the data input / output pad 104, the pull-up / pull-down driver P12,

It may occur that the gate of N12) is in a floating state.

FIG. 2A illustrates an operating voltage of a data output driver with a gate floating, and FIG. 2B illustrates an operating voltage of a data output driver with a gate grounded.

2A and 2B, it can be seen that when the gate is floated, the operating voltage is lower than when the gate is grounded.

The operating voltage when the gate is floated is about 5 V as the voltage at point A of FIG. 2A, and the operating voltage when the gate is grounded is about 9 V as the voltage at point B of FIG. 2B.

Due to the current high speed and low power trend, the first resistor R11 and the second resistor R12 are designed to have a small size. As a result, a large amount of electrostatic current flows into the pull-up / pull-down drivers P12 and N12.

Also, when the gate is floated, the pull-up / pull-down drivers P12 and N12 operate before the electrostatic discharge parts 110 and 112 because the gate is operated at a low voltage level.

If the pull-up / pull-down drivers P12 and N12 operate before the electrostatic discharge units 110 and 112, the pull-up / pull-down drivers P12 and N12 may be damaged by static electricity.

The present invention provides a sub-electrostatic discharge circuit operating at a lower turn-on voltage than the data input / output driver in order to prevent the data input / output driver from operating and being damaged by static electricity before the main electrostatic discharge circuit operates. This prevents malfunction of the data input / output driver.

In order to prevent a malfunction of the data input / output driver, an electrostatic discharge circuit operating at a low operating voltage may include a main electrostatic discharge unit providing a first electrostatic discharge path between the pad and the power line; A data input / output driver unit connected between the pad and the power line to drive data input and output through the pad as power supplied from the power line; And a sub electrostatic discharge part providing a second electrostatic discharge path between the pad and the power line by breakdown when static electricity flows into the pad.

The sub electrostatic discharge part may include a first MOS transistor connected between the pad and the power line and having a gate connected to the power line.

The sub electrostatic discharge unit may further include a resistor connected between the first MOS transistor and the pad.

The sub electrostatic discharge unit may further include a current controller configured to control a current flowing from the power line to the first MOS transistor.

The current control unit may include a second MOS transistor connected between the power line and the gate of the first MOS transistor, and a gate connected to the power line.

The data input / output driver unit may include a second MOS transistor connected between the power line and the pad.

The data input / output driver unit may further include a resistor connected between the second MOS transistor and the pad.

The first MOS transistor has a shorter channel length than the second MOS transistor.

Another embodiment includes a first electrostatic discharge portion providing a first electrostatic discharge path between a power supply voltage line and a pad, and a second electrostatic discharge portion providing a second electrostatic discharge path between the pad and the ground voltage line. Main electrostatic discharge; And a third electrostatic discharge unit providing a first sub electrostatic discharge path between the power supply voltage line and the pad, and a fourth electrostatic discharge unit providing a second sub electrostatic discharge path between the pad and the ground voltage line. A sub electrostatic discharge part; A data input / output driver unit including a pull-up driver performing a pull-up operation between the pad and the power voltage line, and a pull-down driver performing a pull-down operation between the pad and the ground voltage line; And a current control unit controlling a current flowing between the power supply voltage line and the third electrostatic discharge unit and a current flowing between the ground voltage line and the fourth electrostatic discharge unit. It includes.

The third electrostatic discharge part includes a first PMOS transistor having a gate, a source, and a bulk connected to the power supply voltage line, and a drain connected to the pad, and the fourth electrostatic discharge part has a gate, a source, and a bulk connected to the ground voltage. And a first NMOS transistor connected to a line and a drain connected to the pad.

The third electrostatic discharge portion further includes a first resistor connected between the drain of the first PMOS transistor and the pad, and the fourth electrostatic discharge portion is connected between the drain and the pad of the first NMOS transistor. It further comprises a second resistor.

The pull-up driver includes a second PMOS transistor having a bulk and a source connected to the power supply voltage line, and a drain connected to the drain of the first PMOS transistor. The pull-down driver includes a bulk and source connected to the ground voltage line. And a second NMOS transistor connected to the drain of the first NMOS transistor.

The pull-up driver further includes a first resistor connected between the drain of the second PMOS transistor and the drain of the first PMOS transistor, and the pull-down driver further includes a drain of the second NMOS transistor and the first N & A transistor. And a second resistor connected between the drains of the MOS transistors.

Preferably, the gate of the first PMOS transistor is formed to have a shorter length than the gate of the second PMOS transistor, and the gate of the second NMOS transistor is formed to have a length shorter than that of the second NMOS transistor. .

The current controller includes: a first NMOS transistor having a drain, a gate, and a bulk connected to the power supply voltage line, and a source connected to the third electrostatic discharge unit; And a second NMOS transistor having a drain connected to the fourth electrostatic discharge unit, a gate connected to a source of the first NMOS transistor, and a bulk and source connected to the ground voltage line. do.

The first electrostatic discharge unit includes a PMOS transistor having a gate, a source, and a bulk connected to the power supply voltage line, and a drain connected to the pad, and the second electrostatic discharge unit includes a gate, a source, and a bulk connected to the ground voltage line. And an NMOS transistor connected to the drain and connected to the pad.

The present invention includes a sub-electrostatic discharge circuit having a lower turn-on voltage than a data input / output driver in the event of static electricity, thereby providing a faster static discharge path, whereby the data input / output driver is damaged by static electricity before the main static discharge circuit is operated. It is effective in preventing malfunction.

In order to solve the problems of the prior art described above, a sub-electrostatic discharge circuit which is turned on faster than the data input / output driver is operated at a low turn-on voltage to prevent the data input / output driver from operating before the main static protection circuit is operated. An electrostatic discharge circuit can be disclosed.

3 presents a preferred embodiment of the present invention.

3 shows the power supply voltage line 300, the ground voltage line 302, the data input / output pad 304, the main electrostatic discharge units 310 and 312, the sub electrostatic discharge units 320 and 322, the switching unit 330, and the data input. And output driver sections 332 and 334.

Referring to Figure 3 in detail as follows.

The main electrostatic discharge parts 310 and 312 include the first electrostatic discharge part 310 and the second electrostatic discharge part.

302.

The first electrostatic discharge unit 310 includes a PMOS transistor P31 having a gate, a source, and a bulk connected to the power supply voltage line 300 and a drain connected to the data input / output pad 304.

The second electrostatic discharge unit 312 includes an NMOS transistor N31 having a gate, a source, and a bulk connected to the ground voltage line 302, and a drain connected to the data input / output pad 304.

The sub electrostatic discharge parts 320 and 322 may include the third electrostatic discharge part 320 and the fourth electrostatic discharge part.

322.

The third electrostatic discharge part 320 includes a first resistor R31 and a first PMOS transistor P32 connected in series between the power supply voltage line 300 and the data input / output pad 304.

The fourth electrostatic discharge unit 322 includes a second resistor R32 and a second NMOS transistor N32 connected in series between the ground voltage line 302 and the data input / output pad 304.

The switch unit 330 includes a third NMOS transistor N33 and a fourth NMOS transistor N34 connected in series between the power supply voltage line 300 and the ground voltage line 302, and the third NMOS transistor. A source of N33 is connected to the gate of the first PMOS transistor P32, and a drain of the fourth NMOS transistor N34 is connected to the gate of the first NMOS transistor N32.

The data input / output driver unit 332 and 334 includes a pull-up driver unit 332 and a pull-down driver unit 334.

The pull-up driver 332 includes a third resistor R33 and a second PMOS transistor P33 connected in series between the power supply voltage line 300 and the first node ND1.

The pull-down driver 334 includes a fourth resistor R34 and a second NMOS transistor P35 connected in series between the ground voltage line 302 and the second node ND2.

Referring to Fig. 3, the operation principle is as follows.

First, a normal operation mode in which static electricity is not input to the data input / output pad 304 is as follows.

The third NMOS transistor N33 of the switch unit 330 receives the first voltage as the third electrostatic discharge unit.

Transfer to the gate of the first PMOS transistor (P32) (320).

When the gate of the first PMOS transistor P32 is directly connected to the power supply voltage line 300, a leakage current may occur. Therefore, when the gate of the first PMOS transistor P32 is connected to the power supply voltage line 300 through the third NMOS transistor N33, The gate is in a floating state and prevents leakage current.

Since a high level voltage is applied to the power supply voltage line 300, the third NMOS transistor N33 of the switch unit 330 is turned on to operate the first voltage of the first PMOS transistor P32. Pass it to the gate.

Since the first voltage having the high level is input to the gate, the first PMOS transistor P32 is not turned on and does not operate through channel formation like a general MOS transistor. This has the same effect as floating the gate of the first PMOS transistor P32 in normal operation.

Therefore, in the normal operation, the third electrostatic discharge unit 320 does not have any influence on the connection between the data input / output pad 304 and the pull-up driver unit 332.

Next, a case in which positive static electricity is applied to the data input / output pad 304 is as follows.

Since a high level voltage is applied to the power supply voltage line 300, the third NMOS transistor N33 of the switch unit 330 is turned on to operate the first voltage of the first PMOS transistor P32. Passes to the gate.

Since the first voltage having a high level is input to the gate, the first PMOS transistor P32 is not turned on and does not operate by channel formation like a general MOS transistor.

However, since an overvoltage is applied to the first PMOS transistor P32 due to the static electricity generated in the data input / output pad 304, a breakdown occurs and the first PMOS transistor P32 is turned on. .

The first PMOS transistor P32 is turned on by a break down to discharge static electricity from the data input / output pad 304 to the power supply voltage line 300.

In this case, when the overvoltage due to static electricity is also applied to the second PMOS transistor P33, a breakdown may occur and be turned on.

However, the first PMOS transistor P32 is designed to operate at a lower voltage than the second PMOS transistor P33 so that static electricity does not flow into the second PMOS transistor P33.

The design condition of the first PMOS transistor P32 for operating the first PMOS transistor P32 at a lower voltage than the second PMOS transistor P33 is to design a gate length smaller.

4A, 4B, and 4C show simulation results of the relationship between the gate length and the operating voltage.

Referring to Figures 4a, 4b, 4c as follows.

In the case of FIG. 4A, the gate length of the first PMOS transistor P32 and the first NMOS transistor N32 is 0.18 μm.

Point A represents the operating voltage of the first PMOS transistor P32, and its voltage level is about 7.43V.

In the case of FIG. 4B, the gate length of the first PMOS transistor P32 and the first NMOS transistor N32 is 0.15 μm.

Point B represents the operating voltage of the first PMOS transistor P32, and its voltage level is about 6.78V.

In the case of FIG. 4C, the gate length of the first PMOS transistor P32 and the first NMOS transistor N32 is 0.12 μm.

Point C represents the operating voltage of the first PMOS transistor P32, and its voltage level is about 4.55V.

As the gate length of the first PMOS transistor P32 and the first NMOS transistor N32 decreases from 0.18 μm to 0.12 μm, the operating voltage decreases.

By designing the first PMOS transistor P32 to have a smaller gate length than the second PMOS transistor P33, the first PMOS transistor P32 operates at a lower voltage level than the second PMOS transistor P33. .

Therefore, when the first PMOS transistor P32 is turned on and discharges static electricity to the power supply voltage line 300 before the second PMOS transistor 332 is turned on by the breakdown, the second PMOS transistor P33 is turned on. It will not turn on.

As such, the gate length of the first PMOS transistor P32 is set to the second PMOS transistor.

If designed smaller than P33, the pull-up driver 332 is protected from static electricity.

The operation principle when negative static electricity flows into the data input / output pad 304 is the same as the operation principle of the positive static electricity described above, which can be easily understood by those skilled in the art with reference to the above description. Description is omitted.

5 shows a simulation of the operating voltage with respect to the data output resistance.

Referring to FIG. 5, it is noted that the operating voltages of the second PMOS transistor P33 and the second NMOS transistor N35 are not large when the data output resistance is designed to 10 ohms or 20 ohms. Able to know.

If the resistance values of the third resistor R33 constituting the pull-up driver 332 and the fourth resistor R34 constituting the pull-down driver 334 are designed small, the operation speed of the semiconductor device is improved.

1 is a conventional electrostatic discharge circuit

Figure 2a shows the operating voltage of the gated data output buffer

Figure 2b is the operating voltage of the gated data output buffer

3 is an electrostatic discharge circuit of the present invention.

4A shows the operating voltage when the gate length is 0.18 um

4B shows an operating voltage when the gate length is 0.15 um

4C shows an operating voltage when the gate length is 0.12 um

5 is an operating voltage according to the data output resistance

Claims

A main electrostatic discharge unit providing a first electrostatic discharge path between the pad and the power line;

A data input / output driver unit connected between the pad and the power line to drive data input and output through the pad as power supplied from the power line; And

And a sub-electrostatic discharge part providing a second electrostatic discharge path between the pad and the power line by breakdown when static electricity flows into the pad.

The method of claim 1,

And the sub electrostatic discharge unit includes a first MOS transistor connected between the pad and the power line and having a gate connected to the power line.

The method of claim 2,

The sub-electrostatic discharge part further comprises a resistor connected between the first MOS transistor and the pad.

The method of claim 2,

The sub electrostatic discharge unit further comprises a current controller for controlling the current flowing from the power line to the first MOS transistor.

The method of claim 4, wherein

The current controller includes a second MOS transistor connected between the power line and the gate of the first MOS transistor, the gate is connected to the power line.

The method of claim 2,

The data input / output driver unit includes a second MOS transistor connected between the power line and the pad.

The method of claim 6,

The data input / output driver unit further comprises a resistor connected between the second MOS transistor and the pad.

The method of claim 6,

And the first MOS transistor has a shorter channel length than the second MOS transistor.

A main electrostatic discharge unit including a first electrostatic discharge unit providing a first electrostatic discharge path between the power supply voltage line and the pad, and a second electrostatic discharge unit providing a second electrostatic discharge path between the pad and the ground voltage line ;

And a third electrostatic discharge unit providing a first sub electrostatic discharge path between the power supply voltage line and the pad, and a fourth electrostatic discharge unit providing a second sub electrostatic discharge path between the pad and the ground voltage line. A sub electrostatic discharge part;

A data input / output driver unit including a pull-up driver performing a pull-up operation between the pad and the power voltage line, and a pull-down driver performing a pull-down operation between the pad and the ground voltage line; And

A current control unit controlling a current flowing between the power supply voltage line and the third electrostatic discharge unit and a current flowing between the ground voltage line and the fourth electrostatic discharge unit;

Electrostatic discharge circuit comprising a.

The method of claim 9,

The method of claim 10,

The third electrostatic discharge portion further includes a first resistor connected between the drain of the first PMOS transistor and the pad, and the fourth electrostatic discharge portion is connected between the drain and the pad of the first NMOS transistor. Electrostatic discharge circuit further comprising a second resistor.

The method of claim 10,

13. The method of claim 12,

A gate of the first PMOS transistor has a shorter length than that of the second PMOS transistor, and a gate of the second NMOS transistor has a length shorter than that of the second NMOS transistor .

The method of claim 9, wherein the current control unit,

A first NMOS transistor having a drain, a gate, and a bulk connected to the power supply voltage line, and a source connected to the third electrostatic discharge part; And

And a second NMOS transistor having a drain connected to the fourth electrostatic discharge unit, a gate connected to a source of the first NMOS transistor, and a bulk and source connected to the ground voltage line.

The method of claim 9,

The first electrostatic discharge unit includes a PMOS transistor having a gate, a source, and a bulk connected to the power supply voltage line, and a drain connected to the pad, and the second electrostatic discharge unit includes a gate, a source, and a bulk connected to the ground voltage line. And an NMOS transistor connected to the pad and having a drain connected to the pad.