KR20110130811A - Electrostatic discharge circuit - Google Patents

Electrostatic discharge circuit Download PDF

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Publication number
KR20110130811A
KR20110130811A KR1020100050318A KR20100050318A KR20110130811A KR 20110130811 A KR20110130811 A KR 20110130811A KR 1020100050318 A KR1020100050318 A KR 1020100050318A KR 20100050318 A KR20100050318 A KR 20100050318A KR 20110130811 A KR20110130811 A KR 20110130811A
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KR
South Korea
Prior art keywords
voltage
control node
voltage terminal
control
terminal
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KR1020100050318A
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Korean (ko)
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장태식
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주식회사 하이닉스반도체
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Priority to KR1020100050318A priority Critical patent/KR20110130811A/en
Publication of KR20110130811A publication Critical patent/KR20110130811A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits
    • H03K19/0136—Modifications for accelerating switching in bipolar transistor circuits by means of a pull-up or down element

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: An electrostatic discharge circuit is provided to prevent the destruction of an internal circuit by operating an electro-static discharge prevention circuit even when a power voltage is changed minutely. CONSTITUTION: In an electrostatic discharge circuit, a first controller(310) comprises diode chains(311~314) connected between a first voltage terminal(301) and a first control node and also includes a first control resistor. The first control resistor is connected between the first control node and the second voltage terminal(302). A second controller(320) comprises a first NMOS transistor(321) and a second resistor which is connected between the second control node and the second voltage terminal. A discharge unit(330) flows discharge current from the first voltage terminal to the second voltage terminal. The drain of the discharge unit is connected to the first voltage terminal.

Description

Electrostatic Discharge Circuit {ELECTROSTATIC DISCHARGE CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge circuit, and more particularly to an electrostatic discharge circuit that operates even with small changes in power supply voltage.

In general, electrostatic discharge (ELECTROSTATIC DISCHARGE) refers to a phenomenon in which current flows instantaneously due to a very large voltage difference between two objects when they are insulated from each other.

Since high voltages caused by these ESD currents can enter the semiconductor devices, internal circuits can be destroyed, so most semiconductor devices install an electrostatic discharge circuit (ELECTROSTATIC DISCHARGE CIRCUIT) between the input / output pad and the internal circuits to protect the internal circuits. .

The requirements of the electrostatic discharge circuit should not operate at the power supply voltage (VDD) in the normal operating range, and if the power supply voltage (VDD) rises above a certain voltage due to static electricity, etc., a discharge path is rapidly formed to make the ground voltage at the power supply voltage (VDD). The current must be discharged to the (VSS) stage to prevent the gate oxide of the transistor from being destroyed.

As the operating speed of semiconductor devices increases, gate lengths of transistors used in high-speed operation are gradually decreasing, and the thickness of the gate oxide is continuously thinning.

Recently, as the thickness of the gate oxide is lowered to 30 kPa or less, the possibility of destruction of the internal circuit by static electricity as well as power noise is increasing. Therefore, the electrostatic discharge circuit plays a role of protecting the internal circuit from power noise as well as static electricity. In addition, as described above, as the gate oxide (GATE OXIDE) is reduced in thickness, there is a growing need for an electrostatic discharge circuit that reacts sensitively to small changes in the power supply voltage VDD to perform a discharge operation.

1 is a configuration diagram of a conventional electrostatic discharge circuit.

As shown in FIG. 1, a conventional electrostatic discharge circuit includes a diode chain 111, 112, 113, and 114 connected between a power supply voltage VDD terminal 101 and a control node A, a control node A, and a ground. In response to the voltage of the control unit 110 and the control node A including the control resistor 115 connected between the voltage VSS terminal 102, the ground voltage VSS terminal from the power supply voltage VDD terminal 101. And a discharge unit 120 for flowing a discharge current to the 102. The discharge unit 120 is an NMOS transistor 121 whose drain is connected to the power supply voltage VDD terminal, the source is connected to the ground voltage VSS terminal, and the gate input is the voltage of the control node A.

Usually, the operating voltage of internal circuits such as semiconductor devices ranges from 1.2 to 3.5V. The diode chains 111, 112, 113, and 114 do not flow current in the range of such an operating voltage, thereby preventing the electrostatic discharge circuit from operating. Hereinafter, the principle and the discharge operation of the electrostatic discharge circuit will be described later in the description of FIG. 2.

It is an object of the present invention to provide an electrostatic discharge circuit that operates even with a small change in power supply voltage.

An electrostatic discharge circuit according to the present invention for achieving the above object comprises a diode chain connected between a first voltage terminal and the first control node and a first control resistor connected between the first control node and the second voltage terminal. 1 control unit; A drain is connected between the first voltage terminal, a source is connected to the second control node, and a gate input is between the first NMOS transistor, the second control node, and the second voltage terminal. A second control unit including a connected second control resistor; And a discharge unit including a discharge unit configured to flow a discharge current from the first voltage terminal to the second voltage terminal in response to the voltage of the second control node.

The discharge part may be a second NMOS transistor having a drain connected to the first voltage terminal, a source connected to the second voltage terminal, and a gate input of which is a voltage of the second control node.

In addition, the electrostatic discharge circuit according to the present invention for achieving the above object includes a first control resistor connected between a first voltage terminal and the first control node and a diode chain connected between the first control node and the second voltage terminal. A first control unit; A second control unit including a pull-up element configured to pull-up the second control node in response to the voltage of the first control node and a pull-down element configured to pull-down the second control node in response to the voltage of the first control node; And a discharge unit configured to flow a discharge current from the first voltage terminal to the second voltage terminal in response to the voltage of the second control node.

The pull-up device is a PMOS transistor having a source connected to the first voltage terminal, a drain connected to the second control node, and an input of a gate being a voltage of the first control node. And a first NMOS transistor connected to a second control node, a source connected to the second voltage terminal, and a gate input of which is a voltage of the first control node.

The discharge part may be a second NMOS transistor whose drain is connected to the first voltage terminal, a source is connected to the second voltage terminal, and a gate input is a voltage of the second control node.

According to the present invention, it is possible to prevent the internal circuit from being destroyed by operating the electrostatic discharge circuit even with a small change in the power supply voltage.

1 is a configuration diagram of a conventional electrostatic discharge circuit,
2 is a graph showing a snap back characteristic of a transistor;
3 is a configuration diagram of an electrostatic discharge circuit according to an embodiment of the present invention;
4 is a configuration diagram of another electrostatic discharge circuit according to another embodiment of the present invention.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a graph illustrating a snap back characteristic of a transistor.

The snapback phenomenon refers to a phenomenon in which a voltage is applied to a gate of a CMOS transistor and a drain-source current IDS increases rapidly as the drain-source voltage VDS of a transistor is gradually increased.

In general, the transistor is turned on when the gate-source voltage VGS is greater than the threshold voltage VT based on the NMOS transistor. In general, however, turning on the transistor is not enough current flow, which may damage the internal circuit. The purpose of the electrostatic discharge circuit is to discharge the current as soon as possible from the power supply voltage (VDD) to the ground voltage (VSS) in order to prevent damage to the internal circuit when there is a sudden voltage change in the power supply voltage (VDD).

Therefore, the snapback phenomenon is used in the discharge circuit. That is, a larger voltage must be applied to the gate than to turn on the transistor. The snapback phenomenon usually occurs when the voltage applied to the gate of the transistor is between 1/2 and 2/3 of the drain-source voltage VDS.

As described above in the description of FIG. 1, the discharge unit 120 of the electrostatic discharge circuit should not operate in the operating voltage range of the internal circuit. In addition, when the voltage of the power supply voltage VDD terminal rises above a certain voltage due to noise, the NMOS transistor 121 of the discharge unit 120 is referred to as an operation state in which a snapback phenomenon occurs instead of a simple turn-on state (hereinafter, referred to as a snapback mode). ) Must be operated.

Until now, the electrostatic discharge circuit has been designed to operate when the voltage at the power supply voltage (VDD) stage becomes 5V or more due to static electricity or noise. 2 shows the voltage of the control node A, that is, the drain-source voltage VDS when the gate voltage VG of the NMOS transistor 121 is 0.5V, 1.0V, 1.5V, and 2.0V, respectively. Indicates when to enter snapback mode. As shown in FIG. 2, when the drain-source (VDS) voltage is 5V or more, it can be seen that the transistor operates in the snapback mode in all cases where the gate voltage is 0.5V, 1.0V, 1.5V, and 2.0V.

However, as described above, even when the gate oxide of the transistor becomes thin, the electrostatic discharge circuit needs to operate even when the voltage at the power supply voltage VDD stage is about 4-5V. That is, even when the voltage of the power supply voltage VDD stage is about 4 to 5V, there is a need for the NMOS transistor 121 of the discharge unit 120 to operate in the snapback mode. As shown in FIG. 2, when the drain-source voltage VDS is 4 to 5V, the gate voltage of the NMOS transistor 121 should be about 2V in order for the NMOS transistor 121 to operate in the snapback mode. have.

In the electrostatic discharge circuit of FIG. 1, the gate voltage VG of the NMOS transistor 121 is adjusted using a voltage drop caused by the control resistor 115. The gate voltage VG value of the NMOS transistor 121 becomes the resistance value V of the current * control resistor 115 flowing through the control resistor 115. That is, the gate voltage VG of the NMOS transistor 121 is adjusted using the resistor 115 included in the controller 110.

In the conventional case, when the resistance value of the control resistor 115 is set such that the gate voltage VG of the NMOS transistor 121 becomes 2V when the power supply voltage VDD is 5V or more, there is no problem. However, when the control resistor 115 having the above resistance value is used when the power supply voltage VDD is relatively low at 4-5V, the gate voltage VG of the NMOS transistor 121 does not operate in the snapback mode at 1V. There is this. In addition, when the power supply voltage VDD is 4 to 5V, there is a problem in that abnormal operation is performed in high temperature and high voltage operation while increasing the resistance value of the control resistor 115 such that the gate voltage VG of the NMOS transistor 121 becomes 2V. Occurred.

3 is a configuration diagram of an electrostatic discharge circuit according to an embodiment of the present invention.

As shown in FIG. 3, the electrostatic discharge circuit according to the present invention includes a diode chain 311, 312, 313, and 314 connected between a first voltage terminal 301 and a first control node A and a first control node. The first control unit 310 including the first control resistor 315 connected between (A) and the second voltage terminal 302, the drain is connected to the first voltage terminal 301, the source is the second control node A second control resistor connected to (B) and connected between the first NMOS transistor 321 and the second control node B and the second voltage terminal 302, the gate input of which is the voltage of the first control node A; The second control unit 320 including the 322 and the discharge unit 330 for flowing a discharge current from the first voltage terminal 301 to the second voltage terminal 302 in response to the voltage of the second control node (B). ).

The discharge unit 330 includes a second NMOS transistor whose drain is connected to the first voltage terminal 301, a source is connected to the second voltage terminal 302, and an input of a gate is a voltage of the second control node B. 331).

First, when the voltage of the first voltage terminal 301 is in the range of 1.2 ~ 3.5V, the operating voltage of the internal circuit is as follows.

The value of the first control resistor 315 is set such that the voltage of the first control node 301 is about 4V and the voltage of the first control node is about 1V. At a voltage lower than 1V, the first NMOS transistor 321 is turned off. Accordingly, the first NMOS transistor 321 is turned off in the range of 1.2 to 3.5V at the first voltage terminal 301. Therefore, since the discharge control current does not flow through the second control resistor 322, there is no voltage drop, so the voltage of the second control node B becomes the ground voltage VSS.

Since the voltage of the second control node B is the ground voltage VSS, the second NMOS transistor 331 is turned off. Therefore, the discharge current does not flow. That is, when the voltage of the first voltage terminal 301 is about 1.2 to 3.5V, the electrostatic discharge circuit does not operate.

Next, when the voltage of the first voltage terminal 301 is in the range of 4-5V, the operation is as follows.

When the voltage of the first voltage terminal 301, that is, the power supply voltage VDD becomes about 4-5V due to static electricity or noise, the voltage of the first control node A becomes about 1V. This voltage relationship can be clearly set by adjusting the resistance value of the first control resistor 315. When the voltage of the first control node A becomes about 1V, the first NMOS transistor 321 is turned on. Therefore, the discharge control current flows from the first voltage terminal 301 to the second voltage terminal 302. As the discharge control current flows through the second control resistor 322, a voltage drop occurs. The value of the second control resistor 322 is set so that the value of the voltage of the second control node B due to the voltage drop is about 2V.

When the voltage of the second control node B becomes 2V, the second NMOS transistor 331 operates in the snapback mode. Therefore, a large discharge current flows from the first voltage terminal 301 to the second voltage terminal 302. That is, when the voltage of the first voltage terminal 301 is about 4-5V, a large discharge current flows and is discharged quickly. In this case, the problem of abnormal operation in high temperature and high pressure operation, which was a problem, is also solved.

In addition, since the electrostatic discharge circuit discharges when the voltage of the first voltage terminal 301 is 4 to 5V, the electrostatic discharge circuit naturally discharges even when the voltage of the first voltage terminal 301 is 5V or more.

The second NMOS transistor 331 has a width WIDTH greater than that of the first NMOS transistor 321. The width WIDTH of the gate GATE is related to the amount of current flowing through the NMOS transistor. When the gate voltage is the same, a larger drain-source current flows as the width GIDTH of the gate GATE increases. The first NMOS transistor 321 is not intended for discharging, but uses the drain-source current of the first NMOS transistor 321 and the second control resistor 322 to generate a voltage input to the gate of the second NMOS transistor 331. This eliminates the need to use an NMOS transistor with a wide gate width. However, since the second NMOS transistor 331 has a purpose of rapidly discharging the charge from the first voltage terminal 301 to the second voltage terminal 302, the width WIDTH of the gate GATE is increased by the gate of the first NMOS transistor 321. The drain-source current (ie, the discharge current) must be made larger by using a larger than the width of.

4 is a configuration diagram of an electrostatic discharge circuit according to another embodiment of the present invention. As shown in FIG. 4, the electrostatic discharge circuit according to the present invention includes a first control resistor 411 and a first control node A connected between the first voltage terminal 401 and the first control node A. FIG. Pulling up the second control node (B) in response to the voltage of the first control unit 410, the first control node (A) including the diode chain (412, 413, 414) connected between the second voltage terminal (402) A second control unit 420 including a pull-up element 421 for driving and a pull-down element 421 for pull-down driving the second control node B in response to a voltage of the first control node A and a second control; And a discharge unit 410 which discharges a discharge current from the first voltage terminal 401 to the second voltage terminal 402 in response to the voltage of the node B.

The voltage of the first voltage terminal 401 is a power supply voltage VDD, and the voltage of the second voltage terminal 402 is a ground voltage VSS.

The pull-up element 421 is a PMOS transistor whose source is connected to the first voltage terminal 401, the drain is connected to the second control node B, and the input of the gate is a voltage of the first control node A. The pull-down element 422 has a drain connected to the second control node B, a source connected to the second voltage terminal 402, and a gate input of which the voltage of the first control node A is the first NMOS transistor ( 422).

The discharge unit 430 has a drain connected to the first voltage terminal 401, a source connected to the second voltage terminal 402, and a second NMOS transistor 431 whose gate input is a voltage of the second control node B. )to be.

When the voltage of the first voltage terminal 401 is less than 4V, no current flows in the diode chains 412, 413, and 414, and when the voltage of the first voltage terminal 401 is 4V or more, the diode chains 412, 413, 414, Assume that the number of diodes is set so that current flows through

First, when the voltage of the first voltage terminal 301 is in the range of 1.2 ~ 3.5V, the operating voltage of the internal circuit is as follows.

When the voltage of the first voltage terminal 401 is less than 4V, since little current flows in the diode chains 412, 413, and 414, the voltage of the first control node A is near the voltage of the first voltage terminal 401. Increases. Accordingly, the PMOS transistor 421 is turned off and the NMOS transistor 422 is turned on so that the voltage of the second control node B is near the voltage of the second voltage terminal 402, that is, the ground voltage VSS by pull-down driving. Lowers. Therefore, the second NMOS transistor 431 is turned off and the discharge current does not flow.

Next, when the voltage of the first voltage terminal 301 is in the range of 4-5V, the operation is as follows.

When the voltage of the first voltage terminal 301 becomes 4V or more and current flows in the diode chains 412, 413, and 414, the voltage of the first control node A is lowered. When the voltage of the first control node A is lowered, the PMOS transistor 421 is turned on, the NMOS transistor 422 is turned off, and the second control node B is pulled up to drive the voltage to the first voltage terminal 401. ) Voltage, that is, near the power supply voltage VDD. Accordingly, the second NMOS transistor 431 operates in the snapback mode and a discharge current flows from the first voltage terminal 401 to the second voltage terminal 402.

Therefore, it can be seen that the electrostatic discharge circuit of FIG. 4 operates in the same manner as the electrostatic discharge circuit of FIG. 3.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

VDD: power supply voltage VSS: ground voltage
A: first control node B: second control node
301: first voltage terminal 302: second voltage terminal
310: first control unit 311, 312, 313, 314: diode chain
315: first control resistor 320: second control unit
321: first NMOS transistor 322: second control resistor
330: discharge unit 331: second NMOS transistor

Claims (8)

A first control unit including a diode chain connected between a first voltage terminal and a first control node and a first control resistor connected between the first control node and a second voltage terminal;
A drain is connected between the first voltage terminal, a source is connected to the second control node, and a gate input is provided between the first NMOS transistor, the second control node, and the second voltage terminal. A second control unit including a connected second control resistor; And
A discharge unit including a discharge unit configured to flow a discharge current from the first voltage terminal to the second voltage terminal in response to the voltage of the second control node.
Electrostatic discharge circuit comprising a.
The method of claim 1,
And wherein the voltage of the first voltage terminal is a power supply voltage and the voltage of the second voltage terminal is a ground voltage.
The method of claim 1,
And wherein the discharge portion is a second NMOS transistor whose drain is connected to the first voltage terminal, a source is connected to the second voltage terminal, and an input of a gate is a voltage of the second control node.
The method of claim 3, wherein
And the second NMOS transistor has a larger gate width than the first NMOS transistor.
A first control unit including a first control resistor connected between a first voltage terminal and a first control node and a diode chain connected between the first control node and a second voltage terminal;
A second control unit including a pull-up element configured to pull-up the second control node in response to the voltage of the first control node and a pull-down element configured to pull-down the second control node in response to the voltage of the first control node; And
A discharge unit configured to flow a discharge current from the first voltage terminal to the second voltage terminal in response to the voltage of the second control node;
Electrostatic discharge circuit comprising a.
6. The method of claim 5,
And wherein the voltage of the first voltage terminal is a power supply voltage and the voltage of the second voltage terminal is a ground voltage.
6. The method of claim 5,
The pull-up device is a PMOS transistor having a source connected to the first voltage terminal, a drain connected to the second control node, and an input of a gate being a voltage of the first control node. And a source connected to the second voltage terminal, a gate input, and a voltage of the first control node to the first NMOS transistor.
6. The method of claim 5,
And wherein the discharge portion is a second NMOS transistor whose drain is connected to the first voltage terminal, a source is connected to the second voltage terminal, and a gate input is a voltage of the second control node.
KR1020100050318A 2010-05-28 2010-05-28 Electrostatic discharge circuit KR20110130811A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190066498A (en) * 2017-12-05 2019-06-13 삼성전자주식회사 Electrostatic discharge (ESD) protection circuit and integrated circuit including the same
CN113793815A (en) * 2021-09-26 2021-12-14 杭州广立微电子股份有限公司 Wide-voltage-range high-speed multistage discharge circuit, test system and discharge method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190066498A (en) * 2017-12-05 2019-06-13 삼성전자주식회사 Electrostatic discharge (ESD) protection circuit and integrated circuit including the same
CN113793815A (en) * 2021-09-26 2021-12-14 杭州广立微电子股份有限公司 Wide-voltage-range high-speed multistage discharge circuit, test system and discharge method
CN113793815B (en) * 2021-09-26 2024-04-26 杭州广立测试设备有限公司 Wide-voltage-range high-speed multistage discharge circuit, test system and discharge method

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