KR20100059665A - Appratus for coding an image and method for coding the image - Google Patents

Abstract

PURPOSE: An apparatus and a method for coding an image are provided to improve the processing speed substantially when coding a variable length of an image. CONSTITUTION: A 2D DCT(Discrete Cosine Transform) unit(101) performs a DCT operation for inputted image data, and a zigzag scan unit(103) performs a zigzag scanning operation for every DCT coefficient block. A quantization unit(104) quantizes read DCT coefficient based on a preset quantization value, and an intermediate code generator(105) creates an intermediate code on the basis of the quantized DCT coefficient. Based on a non-zero coefficient and a zero run length, a variable-length coding unit(107) generates a Haffman code.

Description

Apparatus for coding an image and method for coding the image}

The present invention relates to a picture coding apparatus and a picture coding method.

As a compression method of still image data, there is a JPEG baseline method, and a half-man code is used for the variable length coding method of the JPEG baseline method. Coefficients that can be obtained by DCT transforming and quantizing image data divided into blocks of 8x8 pixels consist of zero (0) and nonzero values. Half-man coding uses a combination of the number of zeros (zero run length) when the coefficient is zero (zero coefficient) and a nonzero coefficient that is a nonzero coefficient following the zero coefficient in order of high frequency. Allocate short code. In this way, efficient encoding can be performed.

In the conventional halfman code, it is necessary to determine whether the DCT coefficient is zero or non-zero coefficient for each block for all data in the DCT coefficient block when encoding. For example, since the DCT coefficient block is an 8x8 block, which is 64 data, when encoding with half-man code, 64 blocks or more are usually required for one block. For example, Patent Literature 1 discloses a technique for shortening the processing time of a Halfman code.

[Patent Document 1] Japanese Patent Application Laid-Open No. 2003-333339

In conventional variable-length coding, the zero run length is calculated by enumerating consecutive zero coefficients, and one clock is required to enumerate one zero coefficient. In the technique of Patent Literature 1, in order to suppress the number of processing clocks in encoding, one coefficient is combined by combining zero run length and nonzero coefficients at the front of variable length coding that generates a variable length code from zero length and nonzero coefficients. Create In variable length coding, a variable length code is generated based on one generated coefficient. Therefore, in variable length coding of Patent Literature 1, the number of processing clocks for calculating the zero run length is unnecessary, and since the zero run length and the non-zero coefficient are directly input, the number of processing clocks at the time of encoding can be reduced.

In this method, however, the processing clock number is reduced when the zero coefficients are long, that is, when the zero run length is large. However, when the non-zero coefficient is large within one block, the processing clock number reduction effect is lowered. Moreover, when all the coefficients after quantization became nonzero coefficients, there was a problem that there was no effect of reducing the number of processing clocks.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems and various other problems, and the present invention provides a new and improved picture coding apparatus and a picture coding method capable of improving a substantial processing speed in variable length coding.

According to an aspect of the present invention to solve the above problems, an orthogonal transform unit for generating orthogonal transform coefficients by orthogonal transformation of the image data, a quantization unit for generating quantization coefficients by quantizing the orthogonal transform coefficients, the value of the quantization coefficients A zero run length indicating a continuous number of zero coefficients that are zero, a coefficient detector for detecting a non-zero coefficient whose quantization coefficient following the zero coefficient is not zero, and a non-zero coefficient or zero detected sequentially An intermediate code generation unit for generating intermediate codes by sequentially combining run lengths every two or more predetermined numbers, and assigning an identifier for identifying any of non-zero coefficients and zero run lengths for each non-zero coefficient and zero run length; Based on the non-zero coefficients or zero run lengths and identifiers of the intermediate codes, one non-zero coefficient and one zero run length are inputted, respectively. A variable length coding process is performed, and an image coding apparatus including a complementary coding unit comprising a predetermined number and a same number or more.

In the picture coding apparatus according to the present invention, each of the quantization unit, the coefficient detection unit, and the intermediate code generation unit is provided in plural, and each of the quantization unit and each coefficient detection unit includes the image data or the orthogonal transformed data. In addition, parallel processing may be performed through each of the intermediate code generators.

According to another aspect of the present invention, in order to solve the above problems, orthogonal transform of image data to generate orthogonal transform coefficients, quantized orthogonal transform coefficients to generate quantization coefficients, the value of the quantization coefficient is zero (0) A zero run length representing a continuous number of in zero coefficients and a value of a quantization coefficient following the zero coefficient detects a non-zero coefficient, and sequentially detects non-zero coefficients or zero run lengths every two or more predetermined numbers. In combination with each other, an intermediate code is generated for each of the non-zero coefficient and zero run length to generate an intermediate code that identifies which of the non-zero coefficient and zero run length. Nonzero coefficient or zero runlength of the code, and one nonzero coefficient and one zero runlength, respectively, based on the identifier It is input provides a picture coding method for performing variable-length coding process.

According to the present invention, the substantial processing speed can be improved in variable length coding.

EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described in detail with reference to an accompanying drawing. In addition, in the present specification and drawings, components having substantially the same functional configuration will be omitted by overlapping the same reference numerals.

(First Embodiment)

[Configuration of First Embodiment]

First, the picture coding apparatus 100 according to the first embodiment of the present invention will be described. 1 is a block diagram showing the configuration of the picture coding apparatus 100 according to the present embodiment. The image encoding apparatus 100 is, for example, a two-dimensional DCT unit 101, a first buffer 102, a zigzag scan unit 103, a quantization unit 104, and an intermediate code generation unit 105. And a second buffer 106, variable length encoder 107, and the like.

The two-dimensional DCT unit 101 generates a DCT coefficient by performing DCT transformation (Discrete Cosine Transform) (orthogonal transformation) on the input image data. The image data input here is, for example, data obtained by dividing an image signal output from an image pickup device into blocks of 8x8 pixels and blocking them. When the two-dimensional DCT unit 101 performs DCT conversion of image data, an 8x8 DCT coefficient block is generated for each 8x8 pixel block.

The first buffer 102 stores data of the DCT coefficient generated by the two-dimensional DCT unit 101 in units of DCT coefficient blocks.

The zigzag scan unit 103 reads the DCT coefficient from the first buffer 102 and transmits the read DCT coefficient to the quantization unit 104. The zigzag scan unit 103 performs a zigzag scan for each DCT coefficient block when reading the data of the DCT coefficient from the first buffer 102. Fig. 2 shows an 8 × 8 DCT coefficient block and is an explanatory diagram showing a zigzag scan in the DCT coefficient block. In the DCT coefficient block, the DCT coefficients generated by the two-dimensional DCT unit 101 are arranged in the order of 0 to 63 shown in FIG. The zigzag scan unit 103 reads the DCT coefficients first by giving priority to the low frequency region of the DCT coefficient block as shown by the arrow in Fig. 2 and gradually reads the DCT coefficients so as to become a high frequency region.

The quantization unit 104 quantizes the DCT coefficient read by the zigzag scan unit 103 by the zigzag scan to a predetermined quantization value. The quantization unit 104 sends the quantized DCT coefficient to the intermediate code generation unit 105. At this time, the quantized DCT coefficients are output to the quantization unit 104 and then directly transmitted to the intermediate code generation unit 105 without being temporarily stored in a buffer or the like.

The intermediate code generator 105 generates an intermediate code based on the quantized DCT coefficients. The intermediate code consists of a nonzero coefficient of DCT coefficients, zero run length, and each identifier (ID). The intermediate code generator 105 sends the generated intermediate code to the second buffer 106.

The second buffer 106 stores the intermediate code generated in the intermediate code generator 105.

The variable length encoder 107 reads the intermediate code from the second buffer 106 and determines the nonzero coefficient and the zero run length based on the nonzero coefficient and the ID representing the zero run length of the intermediate code. The variable length encoder 107 generates a half-man code based on a non-zero coefficient and zero run length, and outputs the generated half-man code. The variable length coding unit 107 of the present embodiment includes a plurality of code units corresponding to the number of intermediate codes included in one set (intermediate code set) as described later. For example, when two sets of intermediate codes included in one set may be provided, two code units of the variable length encoder 107 may be provided.

[Generation of intermediate code]

Next, generation of the intermediate code according to the present embodiment will be described.

The intermediate code is generated based on the quantized DCT coefficients. The quantized DCT coefficients consist of zero and nonzero values. Thus, the intermediate code generating section 105 is an example of the coefficient detecting section. First, the intermediate code generating section 105 discriminates the non-zero coefficient whose coefficient is a non-zero coefficient and the coefficient whose value is zero (zero coefficient). When the intermediate code generation unit 105 determines that the DCT coefficient is a nonzero coefficient, it outputs the value. The intermediate code generator 105 also outputs an identifier ID indicating that the output value is a nonzero coefficient. In the present embodiment, the ID indicating the nonzero coefficient is set to "1". The intermediate code generation unit 105 generates a set of intermediate codes by combining IDs of non-zero coefficients with IDs. The ID is added to the MSB (most significant bit) of the intermediate code.

On the other hand, when the intermediate code generating unit 105 determines that the DCT coefficient is the zero coefficient, the intermediate code generating unit 105 enumerates the number of zero coefficients that follow the non-zero coefficient until the next non-zero coefficient is determined. The intermediate code generator 105 then outputs the number of enumerated zero coefficients as zero run lengths. In addition, the intermediate code generator 105 outputs an identifier ID indicating that the output value is zero run length. In the present embodiment, an ID indicating zero run length is " 0 ". The intermediate code generation unit 105 generates a set of intermediate codes by combining the ID of the zero run length and the ID. The ID is added to the MSB (most significant bit) of the intermediate code.

Placement of Intermediate Code

Next, the arrangement of the intermediate codes stored in the second buffer 106 will be described with reference to FIG. 3. 3 is an explanatory diagram showing an arrangement of intermediate codes stored in the second buffer 106 of the present embodiment.

The second buffer 106 stores a plurality of intermediate codes consecutive in the time series at the lower part of the temporal sequence, and the second buffer 106 at the upper part of the temporal sequence. In this embodiment, two sets of intermediate codes are set as one set (intermediate code set). In FIG. 3, one set is represented by one line. "Coefficient data" of FIG. 3 shows the value of a non-zero coefficient, and "zero run length" shows the value of zero run length. In the present embodiment, the value of the non-zero coefficient or the zero run length of the intermediate code is represented by 11 bits. In addition, ID is represented by 1 bit. Therefore, in the present embodiment, one set of intermediate codes is represented by 12 bits, and one set of intermediate codes that combines two sets of intermediate codes is represented by 24 bits. Therefore, since one DCT coefficient block is composed of 64 DCT coefficients, the buffer capacity of the intermediate code is sufficient to have a maximum of 768 bits (= 12 bits × 64).

On the other hand, in Patent Document 1, one coefficient generated by combining the zero run length and the nonzero coefficient is expressed by 15 bits in which 4 bits representing the zero run length and 11 bits representing the nonzero coefficient are added together. Therefore, the buffer capacity of the coefficient is at most 960 bits (= 15 bits x 64). Therefore, the buffer capacity of the intermediate code of this embodiment is sufficient even if it is small compared with patent document 1.

An example of an intermediate code generated in the intermediate code generation unit 105 will be described with reference to FIG. 4. 4 is an explanatory diagram showing DCT coefficients A after quantization and intermediate codes B generated by DCT coefficients after quantization arranged in time series order.

The intermediate code consists of the value of the intermediate code (the value of the non-zero coefficient or the value of zero run length) and the ID as shown in Fig. 4B. In FIG. 4B, the zero run length value is indicated in gray. The value of the intermediate code can identify whether it is a value of nonzero coefficient or zero run length by an ID added to the MSB of the intermediate code.

[Read Intermediate Code]

Next, the intermediate code reading from the second buffer 106 by the variable length encoder 107 will be described with reference to FIG. 5. 5 is a block diagram showing a second buffer 106 and a variable length encoder 107 that reads an intermediate code from the second buffer 106. As shown in FIG.

The variable length coding unit 107 has a separation unit 110 as shown in FIG. The separating unit 110 separates the intermediate code (upper code) disposed above and the intermediate code (lower code) disposed below from the intermediate code set stored in the second buffer 106. In addition, the separation unit 110 includes a delay unit (D-type flip-flop) 111. The delay unit 111 inputs an upper code among the preceding intermediate code sets, and outputs the input upper code by delaying one clock. Thus, when the delayed upper code is zero run length, the delayed upper code and the lower code can be encoded. From the above, the separating unit 110 simultaneously outputs an upper code, a lower code, and an upper code delayed by one clock.

[Encoding by Variable Length Coding Unit 107]

Next, the encoding by the variable length encoder 107 will be described with reference to FIG. 6. Fig. 6 is a block diagram showing the variable length coding unit 107 of this embodiment. The lower code among the intermediate code sets input to the second buffer 106 is called C0, its ID is called ID0, the upper code is called C1, and its ID is called ID1. The upper code delayed by one clock is given d at the end, for example, C1_d, and its ID is indicated by ID1_d.

The variable length encoder 107 has selectors 121 and 122, a first code unit 131, a second code unit 132, and a connection unit 141 as shown in FIG. 6. When two intermediate codes included in one set (intermediate code set) are two sets, the variable length encoder 107 may include a first coder 131 and a second coder 132.

"A" in the input of the 1st code part 131 and the 2nd code part 132 represents the input of a non-zero coefficient, and "Z" represents the input of zero run length. The first coder 131 and the second coder 132 output a halfman code by referring to, for example, a two-dimensional halfman table based on the non-zero coefficient and zero run length. The half-man coding in the first coder 131 and the second coder 132 is based on the number of zeros (zero run length) when the coefficient is zero (zero coefficient) and a nonzero value following the zero coefficient. Combinations with non-zero coefficients are assigned shorter code lengths in order of frequent occurrence. In this way, efficient encoding can be performed.

The first coder 131 switches between the selectors 121 and 122 at the front end based on the combination of IDs included in the intermediate code to perform input processing of the input A and the input Z. FIG.

As shown in FIG. 6, the non-zero coefficient input to the input A of the 1st code part 131 is an upper code C1 or a lower code C0. The zero run length input to the input Z of the first coder 131 is 0, a lower code C0, or an upper code C1_d before one clock. The nonzero coefficient input to the input A of the second code part 132 is the high order code C1. The zero run length input to the input Z of the second coder 132 has a value of zero. The second code unit 132 operates only when both the upper code C1 and the lower code C0 of the intermediate code set are non-zero coefficients to output a half-man code.

The inputs A of the first coder 131 and the second coder 132 are non-zero coefficients. When there is a nonzero coefficient in the lower code C0 of the intermediate code set consisting of two sets of intermediate codes, the nonzero coefficient of the lower code C0 is input to the input A of the first code unit 131. When the lower code C0 has a nonzero coefficient and the higher code C1 also has a nonzero coefficient, the nonzero coefficient of the lower code C0 is input to the input A of the first code part 131 and the higher code. The nonzero coefficient of (C1) is input to the input A of the second code unit 132. When there is a zero run length in the lower code C0 and a nonzero coefficient in the upper code C1, the nonzero coefficient of the upper code C1 is input to an input A of the first code unit 131.

The input Z of the first code part 131 is zero run length, and is the zero run length immediately before the non-zero coefficient input to the input A of the first code part 131. For example, the input A of the first code unit 131 is a non-zero coefficient of the lower code C0, and there is zero run length in the upper code C1_d delayed immediately before the lower code C0. In this case, the zero run length of C1_d is input to the input Z of the first code unit 131. In addition, when the input A of the first code unit 131 is a nonzero coefficient of the lower code C0, and there is a nonzero coefficient in the higher code C1_d immediately delayed by the lower code C0, the input ( The zero run length immediately before the nonzero coefficient input to A) is zero. Therefore, the zero run length value = 0 is input to the input Z of the first code part 131. When the input A of the first code part 131 is a non-zero coefficient of the higher code C1, the zero run length of the lower code C0 is input to the input Z of the first code part 131. .

The input Z of the second code part 132 is zero run length, and is the zero run length immediately before the non-zero coefficient input to the input A of the second code part 132. When an input is made to the inputs A and Z of the second coder 132, both of the upper code C1 and the lower code C0 of the intermediate code set are non-zero coefficients. Therefore, since the zero run length immediately before the non-zero coefficient input to the input A of the second code part 132 is zero, the zero run length value = 0 is input to the input Z of the second code part 132. .

Input switching in the selectors 121, 122 is executed based on the ID included in the intermediate code. When the middle code set is input, the selectors 121 and 122 are input (A) by a combination of ID1, which is an ID of a higher code included in the intermediate code set, ID0, which is an ID of a lower code, and ID1_d, which is an ID of an upper code 1 clock before, and Switch the input of the input Z. 7 shows a relationship between the combination of IDs and the types of intermediate codes to be input. Fig. 7 is a table showing the relationship between the combination of IDs and the types of intermediate codes to be input.

For example, if the combination is (ID1, ID0, ID1_d) = (0, 1, 0), the upper code C1 is zero run length, the lower code C0 is nonzero coefficient, and the upper code C1_d one clock before. ) Is zero run length. In the example shown in Fig. 4, for example, the coefficient is a part of 0 → 0 → 0 → 0 → 6 → 0 → 0 → 0 (Fig. 4 (A)), and the intermediate code is the higher code C1_d before one clock. Is 4, lower code C0 is 6, and upper code C1 is 3 (FIG. 4B). At this time, according to FIG. 7, the lower code C0 is input to the first code unit 131 as the input A, and the upper code C1_d one clock before the input Z is input. The second coder 132 is not used.

For example, if the combination is (ID1, ID0, ID1_d) = (1, 0, 1), the upper code C1 is nonzero coefficient, the lower code C0 is zero run length, and the higher code C1_d one clock ago. ) Is the nonzero coefficient. In the example shown in FIG. 4, for example, the coefficient is a part of 2 → 0 → 1 (FIG. 4 (A)), and the intermediate code has 2 high codes C1_d before one clock and 2 low codes C0. , The higher code C1 is 1 (Fig. 4 (B)). At this time, according to FIG. 7, the upper code C1 is input to the first code unit 131 as the input A, and the lower code C0 is input to the input Z. As shown in FIG. The second coder 132 is not used.

For example, if the combination is (ID1, ID0, ID1_d) = (1, 1, 1), the upper code C1 has a nonzero coefficient, the lower code C0 has a nonzero coefficient, and the upper code (1 clock before) C1_d) is the nonzero coefficient. In the example shown in Fig. 4, for example, the coefficient is 1 → 1 → 2 as a part (Fig. 4 (A)), and the intermediate code has 1 higher code C1_d before 1 clock and 1 lower code C0. , The higher code C1 is 2 (Fig. 4 (B)). In this case, according to FIG. 7, the lower code C0 is input to the first coder 131 as the input A, and the value 0 is input as the input Z. FIG. The upper code C1 is input to the second coder 132 as the input A, and a value 0 is input as the input Z.

In addition, the combination which is not shown in FIG. 7 is a combination which does not appear. For example, if the upper code before one clock is zero run length (ID is 0), the lower code does not become zero run length and the ID of the lower code does not become zero. This is because the intermediate code becomes the intermediate code of the non-zero coefficient after zero run length.

The connection unit 141 combines the half-man code output from the first code unit 131 and the second code unit 132 in bit units. For example, when the half-man code output from the first code unit 131 is 11 bits and the half-man code output from the second code unit 132 is 5 bits, the connection unit 141 is a half-man code combined with 16 bits. Outputs

According to this embodiment, an intermediate code consisting of non-zero coefficients, zero run lengths, and respective identifiers (ID) of the DCT coefficients is generated at the front end of the variable length encoding. In addition, the variable length encoder 107 includes a plurality of code units, thereby reducing processing time required for encoding. For example, by combining two intermediate codes into a set of intermediate codes and providing two code units, the number of processing clocks required for encoding can be suppressed to 1/2 or less.

In addition, in the technique of Patent Document 1 described above, the coefficients after quantizing the image data are stored in the buffer once, followed by a zigzag scan and combining one of the zero run length and the nonzero coefficients to generate one coefficient. However, this processing procedure has a problem that the number of processing clocks increases in contrast to the case of quantization after a zigzag scan. On the other hand, according to this embodiment, since it is quantized after a zigzag scan, there is no problem that the number of processing clocks increases as in Patent Document 1.

[First Modified Example of First Embodiment]

Next, a first modified example of the picture coding apparatus 100 according to the first embodiment of the present invention will be described.

In the above-described image coding apparatus 100, the case where two sets of intermediate codes are set as one intermediate code set has been described. However, the present invention is not limited to the above examples. For example, three sets of intermediate codes may be set as one set, such as three sets of intermediate codes as one intermediate code set.

First, the case where three sets of intermediate codes are set as one intermediate code set will be described. In this case, the variable length encoder 107 may include three code units, that is, a first code unit 231, a second code unit 232, and a third code unit 233, as shown in FIG. 8. Can be. 8 is a block diagram showing a modification of the variable length coding unit 107 of the present embodiment.

First, the intermediate code generator 105 generates an intermediate code including a value of a nonzero coefficient or a value of a zero run length and an identifier ID based on the nonzero coefficient and zero run length. The generated intermediate code is sent to the variable length encoder 107 through the second buffer 106. In this modification, three sets of intermediate codes are set as one set (intermediate code set).

Next, the encoding by the variable length encoder 107 will be described. Of the intermediate code sets consisting of three sets of intermediate codes input to the second buffer 106, the lower intermediate codes are set to C0, C1, and C2, and each ID is set to ID0, ID1, and ID2. The most significant code delayed by one clock is appended with _d at the end, for example, C2_d and its ID as ID2_d.

As shown in FIG. 8, the variable length encoder 107 includes selectors 221, 222, 223, and 224, a first code unit 231, a second code unit 232, a third code unit 233, and a connection unit 241. It is provided. In the case where there are three sets of intermediate codes included in one set (intermediate code set), the variable length encoder 107 is composed of three code parts, so that the variable length encoder 107 is the first code part 231 and the second code. It has a code part 232 and the 3rd code part 233. As shown in FIG.

The first code unit 231, the second code unit 232, and the third code unit 233 may refer to a two-dimensional half-man table based on a non-zero coefficient and zero run length, for example, to obtain a half-man code. Output The first coder 231, the second coder 232, and the third coder 233 are switched from the selectors 221, 222, 223, and 224 based on a combination of IDs included in the intermediate code to input (A) and Input processing of input Z is performed.

As shown in FIG. 8, the non-zero coefficient input to the input A of the 1st code part 231 is the median code C1 or the lower code C0. The zero run length input to the input Z of the first coder 231 is 0, a lower code C0, or an upper code C2_d before one clock. The nonzero coefficient input to the input A of the second code part 232 is the higher code C2 or the median code C1. The zero run length input to the input Z of the second coder 232 is 0 or the median code C1. The nonzero coefficient input to the input A of the third code portion 233 is the higher code C2. The zero run length input to the input Z of the third coder 233 has a value of zero. The third coder 233 operates only when all of the intermediate codes C2, C1, and CO0 of the intermediate code set are non-zero coefficients, and outputs a half-man code.

The inputs A of the first code part 231, the second code part 232, and the third code part 233 are non-zero coefficients. The nonzero coefficient of the intermediate code set consisting of three sets of intermediate codes is the first code part 231 → the second code part 232 → the third code part 233 in the order of the lower nonzero coefficient to the upper nonzero coefficient. Are assigned to the input of the input (A). For example, the lower code C0 is zero run length, and when the median code C1 has a nonzero coefficient, the nonzero coefficient of the median code C1 is input to the input A of the first code part 231. Is entered. When the lower code C0 has a nonzero coefficient and the median code C1 also has a nonzero coefficient, the nonzero coefficient of the lower code C0 is input to an input A of the first code part 231, and the median. The nonzero coefficient of the code C1 is input to an input A of the second code portion 232. When all of the intermediate codes C2, C1, and C0 are nonzero coefficients, they are input to the input A of the first code part 231 in order from the nonzero coefficients of the lower intermediate codes, and the intermediate codes C1. The nonzero coefficient of is input to the input A of the second code part 232, and the nonzero coefficient of the higher code C2 is input to the input A of the third code part 233.

The input Z of the first code part 231 is zero run length, and is the zero run length immediately before the non-zero coefficient input to the input A of the first code part 231. For example, when the input A of the first code part 231 is a nonzero coefficient of the lower code C0, and there is zero run length in the upper code C2_d delayed by one clock immediately before the lower code C0, The zero run length of C2_d is input to the input Z of the first code unit 231. In addition, when the input A of the first code part 231 is a nonzero coefficient of the lower code C0, and there is a nonzero coefficient in the upper code C2_d delayed by one clock immediately before the lower code C0, the input ( The zero run length immediately before the nonzero coefficient input to A) is zero. Accordingly, the zero run length value = 0 is input to the input Z of the first code part 231. When the input A of the first code part 231 is a non-zero coefficient of the median code C1, the zero run length of the lower code C0 is input to the input Z of the first code part 231. .

The input Z of the second code part 232 is zero run length, which is the zero run length immediately before the non-zero coefficient input to the input A of the second code part 232. For example, when the input A of the second code part 232 is a nonzero coefficient of the higher code C2, and there is a nonzero coefficient in the immediately preceding infix code C1 of the higher code C2, the input A The zero run length just before the non-zero coefficient input to) is zero. Therefore, the zero run length value = 0 is input to the input Z of the second code part 232. When the input A of the second code part 232 is a non-zero coefficient of the median code C1, the zero run length value = 0 is input to the input Z of the second code part 232.

The input Z of the third code part 233 is zero run length, and is the zero run length immediately before the non-zero coefficient input to the input A of the third code part 233. An input is made to the inputs A and Z of the third coder 233 when the upper code C2, the middle code C1, and the lower code C0 of the intermediate code set are all non-zero coefficients. Therefore, since the zero run length immediately before the non-zero coefficient input to the input A of the third code part 233 is zero, the zero run length value = 0 is input to the input Z of the third code part 233. .

Input switching at the selectors 221, 222, 223, 224 is made based on the ID included in the intermediate code. The selectors 221, 222, 223, and 224, when an intermediate code set is input, a combination of an ID2 of an upper code, ID1 of an intermediate code, ID0 of an ID code, and ID2_d of an ID code 1 clock before the intermediate code set is input. The input of the input A and the input Z is switched by. 9 shows a relationship between the combination of IDs and the types of intermediate codes to be input. 9 is a table showing the relationship between the combination of IDs and the types of intermediate codes to be input.

For example, if the combination is (ID2, ID1, ID0, ID2_d) = (0,1,1,0), the upper code (C2) is zero run length, the infix code (C1) is nonzero coefficient, and the lower code (C0). ) Is a non-zero coefficient, and the higher code C2_d one clock before is zero run length. At this time, according to FIG. 9, the lower code C0 is input to the first coder 231 as the input A, and the upper code C2_d one clock before is input as the input Z. FIG. The lower code C1 is input to the second coder 232 as the input A, and the value 0 is input as the input Z. The third coder 233 is not used.

For example, if the combination is (ID2, ID1, ID0, ID1_d) = (1, 0, 1, 0), the upper code (C2) is non-zero coefficient, the median code (C1) is zero run length, and the lower code ( C0) is the non-zero coefficient, and the upper code C2_d before one clock is zero run length. At this time, according to FIG. 9, the lower code C0 is input to the first coder 231 as the input A, and the upper code C2_d one clock before the input Z is input. The upper code C2 is input to the second coder 232 as the input A, and the median code C1 is input to the input Z. The third coder 233 is not used.

For example, if the combination is (ID2, ID1, ID0, ID1_d) = (1,1,0,1), the upper code (C2) is the nonzero coefficient, the infix code (C1) is the nonzero coefficient, and the lower code (C0). ) Is zero run length, and the upper code C2_d one clock before is a nonzero coefficient. At this time, according to FIG. 9, the median code C1 is input to the first code part 231 as the input A, and the lower code C0 is input to the input Z. As shown in FIG. The upper code C2 is input to the second coder 232 as the input A, and the lower code C0 is input as the input Z. The third coder 233 is not used.

The connection unit 241 combines the half-man code output from the first code unit 231, the second code unit 232, and the third code unit 233 in units of bits. For example, the half-man code output from the first code part 231 is 11 bits, the half-man code output from the second code part 232 is 5 bits, and the half-man code is output from the third code part 233. When not output, the connection unit 241 outputs a combined 16-bit half-sign.

According to this modification, an intermediate code consisting of nonzero coefficients, zero run lengths, and respective identifiers (ID) of the DCT coefficients is generated at the front of the variable length encoding. By combining three intermediate codes into a set of intermediate codes and providing three code units, the number of processing clocks required for encoding can be reduced to 1/3 or less.

Second Modification of First Embodiment

Even in the case of one intermediate code set including four or more sets of mid codes, the same process can be performed as in the case of the intermediate code set including two or three sets of intermediate codes. For example, when four sets of intermediate codes are set as one intermediate code set, the variable length encoding unit 107 has four code units, that is, a first code unit 331 and a second code unit, as shown in FIG. 332, a third reference unit 333, and a fourth reference unit 334 may be provided. 10 is a block diagram showing a modification of the variable length encoder 107 to be encoded.

First, the intermediate code generator 105 generates an intermediate code including a value of the nonzero coefficient or a value of the zero run length and an ID based on the nonzero coefficient and the zero run length. The generated intermediate code is sent to the variable length encoder 107 through the second buffer 106. In this modification, four sets of intermediate codes are set as one set (intermediate code set).

Next, the encoding by the variable length encoder 107 will be described. Of the intermediate code sets consisting of four sets of intermediate codes input to the second buffer 106, the lower intermediate codes are set to C0, C1, C2, and C3, and each ID is set to ID0, ID1, ID2, and ID3. The most significant code delayed by one clock is appended with _d at the end, for example, C3_d and its ID as ID3_d.

As shown in FIG. 10, the variable length encoder 107 includes selectors 321, 322, 323, 324, 325, 326, a first code part 331, a second code part 332, a third code part 333, and a fourth code part. 334 and a connection portion 341. In the case where there are four sets of intermediate codes included in one set (intermediate code set), the variable length encoder 107 is composed of four code units because the variable length encoder 107 is composed of four code units. The 2nd code part 332, the 3rd code part 333, and the 4th code part 334 are provided.

The first code part 331, the second code part 332, the third code part 333, and the fourth code part 334 are based on a non-zero coefficient and zero run length, for example, only a two-dimensional half. Outputs the half-man code by referring to the table. The first coder 331, the second coder 332, the third coder 333, and the fourth coder 334 are selectors 321, 322, 323, 324, 325 and 326 based on a combination of IDs included in the intermediate code. The input processing of input A and Z is performed by switching from to.

As shown in FIG. 10, the non-zero coefficient input to the input A of the 1st code part 331 is intermediate code C1 or C0. The zero run length input to the input Z of the first coder 331 is 0, and the intermediate code C0 or (C3_d). The nonzero coefficient input to the input A of the second code part 332 is the intermediate code C3, C2 or code C1. The zero run length input to the input Z of the second coder 332 is 0, the intermediate code C2, or C1. The nonzero coefficient input to the input A of the third code part 333 is the intermediate code C3 or C2. The zero run length input to the input Z of the third coder 333 is 0 or an intermediate code C2. The nonzero coefficient input to the input A of the fourth code part 334 is the intermediate code C3. The zero run length input to the input Z of the fourth coder 334 has a value of zero. The fourth code part 334 operates only when all of the intermediate codes C3, C2, C1, and C0 of the intermediate code set are non-zero coefficients, and outputs a half-man code.

The input A of the 1st code part 331, the 2nd code part 332, the 3rd code part 333, and the 4th code part 334 is a non-zero coefficient. The nonzero coefficient of the intermediate code set consisting of four sets of intermediate codes is the first code part 331 → the second code part 332 → the third code part 333 in the order of the lower nonzero coefficient to the upper nonzero coefficient. ? Is assigned to the input of the input A in the order of the fourth code part 334.

The input Z of the first code part 331 is zero run length and is the zero run length immediately before the non-zero coefficient input to the input A of the first code part 331. The input Z of the second code part 332 is zero run length and is the zero run length immediately before the non-zero coefficient input to the input A of the second code part 332. The input Z of the third code part 333 is zero run length and is the zero run length immediately before the non-zero coefficient input to the input A of the third code part 333. The input Z of the fourth code part 334 is zero run length and is the zero run length immediately before the non-zero coefficient input to the input A of the fourth code part 334.

Input switching at selectors 321, 322, 323, 324, 325, 326 is made based on the ID included in the intermediate code. The selectors 321, 322, 323, 324, 325, 326 switch input (A) and input (Z) by a combination of ID3, ID2, ID1, ID0, and ID3_d included in the intermediate code set when the intermediate code set is input. 11 shows a relationship between the combination of IDs and the types of intermediate codes to be input. 11 is a table showing the relationship between the combination of IDs and the types of intermediate codes to be input.

For example, if the combination is (ID3, ID2, ID1, ID0, ID2_d) = (1,0,1,1,0), then C3 is nonzero coefficient, C2 is zero run length, C1 is nonzero coefficient, C0 The nonzero coefficient, C3_d before one clock, is zero run length. At this time, as shown in Fig. 11, C0 is input to the first code part 331 as the input A, and C3_d one clock before the input Z is input. C1 is input to the second coder 332 as the input A, and a value 0 is input to the input Z. C3 is input to the third coder 333 as the input A, and C2 is input to the input Z. The fourth code part 334 is not used.

The connection unit 341 combines the half-man code output from the first code unit 331, the second code unit 332, the third code unit 333, and the fourth code unit 334 in bit units. For example, the half-man code output from the first code part 331 is 11 bits, the half-man code output from the second code part 332 is 5 bits, and the third code part 333 and the fourth code part ( When the half-man code is not output in 334, the connection unit 341 outputs a half-man code in which 16 bits are combined.

According to this modification, an intermediate code consisting of non-zero coefficients, zero run lengths, and respective identifiers (ID) of the DCT coefficients is generated at the front of the variable length encoding. By combining four intermediate codes into one set of intermediate codes and providing four code units, the number of processing clocks required for encoding can be reduced to 1/3 or less.

(2nd Embodiment)

Next, with reference to FIG. 12, the image coding apparatus 200 which concerns on 2nd Embodiment of this invention is demonstrated. 12 is a block diagram showing the configuration of the picture coding apparatus 200 according to the present embodiment.

The image encoding apparatus 200 may be, for example, a two-dimensional DCT unit 401, first buffers 402-1, 402-2, zigzag scan units 403-1, 403-2, and quantization units 404-. 1,404-2, intermediate code generators 405-1 and 405-2, second buffers 406-1 and 406-2, and variable length encoder 407.

Unlike the picture coding apparatus 100 of the first embodiment, the picture coding apparatus 200 according to the present embodiment has angles from the first buffers 402-1 and 402-2 to the second buffers 406-1 and 406-2. The functional blocks are arranged in parallel in two systems. First buffers 402-1 and 402-2, zigzag scan units 403-1 and 403-2, quantization units 404-1 and 404-2, intermediate code generators 405-1 and 405-2, and The configuration and operation of the two buffers 406-1 and 406-2 are the first buffer 102, the zigzag scan unit 103, the quantization unit 104, and the intermediate code generator 105 of the first embodiment. Since it is the same as that of the second buffer 106, detailed description thereof will be omitted.

The two-dimensional DCT unit 401 performs DCT conversion on the image data to generate 8 × 8 DCT coefficient blocks for each 8 × 8 pixel block. The two-dimensional DCT unit 401 alternately outputs the generated DCT coefficient blocks to the first buffer 402-1 and the first buffer 402-2. 13 is a timing chart showing the operation of the picture coding apparatus 200 according to the present embodiment. "BLK" in FIG. 13 is an abbreviation of block.

The two-dimensional DCT unit 401 is executed at twice the speed, for example, than the two-dimensional DCT unit 101 of the first embodiment. For example, the two-dimensional DCT unit 401 processes one DCT coefficient block within 32 clocks.

Each functional block from the first buffers 402-1 and 402-2 to the second buffers 406-1 and 406-2 is configured in parallel to form a real 1DCT coefficient for processing from zigzag scan to intermediate code generation. A block can be processed within 32 clocks.

The variable length encoder 407 encodes only the half of the DCT coefficient based on the intermediate code. Since the variable length encoder 407 has a plurality of code units in the same way as the variable length encoder 107 of the first embodiment, the number of clocks required for encoding can be suppressed to 1/2 or less of the number of data. Therefore, even if the processing from the zigzag scan to the intermediate code generation and the actual 1DCT coefficient block are processed within 32 clocks, the variable length encoder 407 starts encoding the next DCT coefficient block after completing encoding of one DCT coefficient block. can do.

Therefore, according to the second embodiment, not only the encoding but also the encoding of the entire JPEG, for example, can be performed at twice the speed as in the first embodiment. 14 is a timing chart showing the operation of the conventional picture coding apparatus. Conventionally, the number of processing clocks of variable length coding is the same as the number of processing clocks of two-dimensional DCT.

In addition, when the processing from zigzag scan to intermediate code generation is parallel and executed in three or more systems, and the variable length encoder 407 has three or more code parts according to the system number, the entire JPEG process can be further shortened. have.

As mentioned above, although preferred embodiment of this invention was described in detail with reference to an accompanying drawing, this invention is not limited to the said example. Those skilled in the art to which the present invention pertains can clearly conceive of various changes or modifications within the scope of the technical idea described in the claims, and of course these also fall within the technical scope of the present invention. It is understood to belong.

1 is a block diagram showing the configuration of a picture coding apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a zigzag scan in 8x8 DCT coefficient blocks and DCT coefficient blocks.

3 is a diagram showing an arrangement of intermediate codes stored in the second buffer of the embodiment.

4 is a diagram illustrating a DCT coefficient A after quantization and an intermediate code B generated after the quantization DCT coefficients arranged in time series order.

5 is a block diagram illustrating a second buffer and a variable length encoder which reads an intermediate code from the second buffer.

6 is a block diagram showing a variable length coding unit of the embodiment.

7 is a diagram illustrating a relationship between a combination of IDs and types of intermediate codes to be input.

8 is a block diagram showing a modification of the variable length coding unit of the embodiment.

9 is a diagram illustrating a relationship between a combination of IDs and types of intermediate codes to be input.

Fig. 10 is a block diagram showing a modification of the variable length encoder which executes encoding.

11 is a diagram illustrating a relationship between a combination of IDs and types of intermediate codes to be input.

12 is a block diagram showing the structure of a picture coding apparatus according to a second embodiment of the present invention.

13 is a timing chart showing the operation of the picture coding apparatus of the embodiment.

14 is a timing chart showing the operation of the conventional picture coding apparatus.

** Brief description of symbols for the main parts of the drawing **

100,200 picture coding device

101,401 2-D DCT Part

102,402-1,402-2 First buffer

103,403-1,403-2 Zigzag Scan

104,404-1,404-2 Quantizer

105,405-1,405-2 intermediate code generator

106,406-1,406-2 Second buffer

107,407 variable length encoder

110 separation

111 delay

121,122,221,222,223,224,321,322,323,324,325,326 Selector

131,231,331 First Sign

132,232,332 Second Code

141,241,341 connections

233,333 Third Code

334 4th Code

Claims (3)

An orthogonal transform unit which orthogonally transforms the image data to generate orthogonal transform coefficients; A quantizer configured to quantize the quadrature transform coefficients to generate quantization coefficients; A zero run length indicating a continuous number of zero coefficients in which the value of the quantization coefficient is zero, and a coefficient detection unit detecting a non-zero coefficient in which the value of the quantization coefficient following the zero coefficient is not zero; The non-zero coefficient and the zero run length are each identified by an identifier that sequentially combines the non-zero coefficients or the zero run lengths which are sequentially detected every two or more predetermined numbers, and identifies which of the non-zero coefficients and the zero run lengths. An intermediate code generation unit configured to generate an intermediate code; One non-zero coefficient and one zero run length are respectively input based on the non-zero coefficient or the zero run length and the identifier of the intermediate code to perform a variable length encoding process, the number being at least equal to the predetermined number. And a plurality of encoding units formed of a plurality of encoding units. The apparatus of claim 1, wherein each of the quantization unit, the coefficient detection unit, and the intermediate code generation unit is provided in plurality. And the orthogonal transform data is processed in parallel through each of the quantization unit, each of the coefficient detection units, and each of the intermediate code generators. Orthogonally transforming the input image data to generate orthogonal transform coefficients, Quantizing the quadrature transform coefficients to generate quantization coefficients, Detecting a zero run length indicating a continuous number of zero coefficients in which the value of the quantization coefficient is zero, and a non-zero coefficient in which the value of the quantization coefficient following the zero coefficient is not zero; The non-zero coefficient and the zero run length are each identified by an identifier that sequentially combines the non-zero coefficients or the zero run lengths which are sequentially detected every two or more predetermined numbers, and identifies which of the non-zero coefficients and the zero run lengths. To generate intermediate code, Based on the non-zero coefficient of the intermediate code or the zero run length and the identifier, one non-zero coefficient and one zero run length are respectively input to each of the code parts, and a variable length encoding process is performed on each of the code parts. An image encoding method comprising the step of performing.

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